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KR900019169A - Multi-layer metallization process method of semiconductor device - Google Patents

Multi-layer metallization process method of semiconductor device Download PDF

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Publication number
KR900019169A
KR900019169A KR1019890007207A KR890007207A KR900019169A KR 900019169 A KR900019169 A KR 900019169A KR 1019890007207 A KR1019890007207 A KR 1019890007207A KR 890007207 A KR890007207 A KR 890007207A KR 900019169 A KR900019169 A KR 900019169A
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South Korea
Prior art keywords
film
lower metal
forming
metal wiring
insulating film
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KR1019890007207A
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KR910010223B1 (en
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이원규
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정몽헌
현대전자산업 주식회사
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Abstract

내용 없음No content

Description

반도체소자의 다층금속배선 공정방법Multi-layer metallization process method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 실리콘 기판에서 다층금속배선 공정전의 셀구성을 위한 기본공정후 하층금속배선을 구성하는 금속막을 형성한 단면도. 제3도는 금속배선을 위한 포토레지스트 패턴형성으로 실리콘 박막과 금속막을 건식식각에 의한 금속배선 패턴을 형성한후 포토레지스트를 제거한 상태의 단면도, 제4도는 금속배선층간의 절연을 위한 실리콘 산화막의 증착후 평탄화 공정에 의해 실리콘 산화막이 평탄화된 형태를 나타낸 단면도, 제7도는 상층금속막의 형성과 포토레지스트 패턴에 의한 상층금속 배선식각과 포토레지스트 제거후의 상층금속배선이 형성된 단면도.1 is a cross-sectional view of a metal film forming a lower metal wiring after a basic process for forming a cell before a multilayer metal wiring process in a silicon substrate. FIG. 3 is a cross-sectional view of a photoresist removed after forming a metal wiring pattern by dry etching a silicon thin film and a metal film by forming a photoresist pattern for metal wiring. FIG. 4 is a view after deposition of a silicon oxide film for insulation between metal wiring layers. Fig. 7 is a cross-sectional view showing a form in which a silicon oxide film is flattened by a planarization process.

Claims (1)

실리콘기판 상에 MOSFET, 소자분리 산화막 및 캐패시터등을 형성하고 그 상부에서 전체적으로 절연막을 형성한 다음, 반도체소자의 하층금속막 및 절연막이 순차적으로 형성하고 상기 절연막의 일정부분을 식각하여 비아콘택홀을 형성한후 상층금속막을 형성하여 하층금속막과 접속되도록 하는 다층금속배선 공정에 있어서, 상기 절연막의 일정부분을 식각하여 비아콘택을 형성할때 발생되는 하층금속막의 손상과, 하층금속막에 산화막이 발생됨에 따른 콘택저항의 불안정 형상을 방지하기 위하여, 상기 하층금속막 형성시 실리콘 박막을 동일반응기에서 하층금속막 표면에 형성한후 패턴공정으로 금속배선을 형성하고 상기 실리콘 박막 상부에 절연막을 형성하는 공정과, 상기 금속배선상의 절연막의 일정부분에 포토레지스트를 형성하고 일정부분 제거한후 상기 포토레지스트가 제거된 부분의 절연막도 제거하여 비아콘택홀을 형성한다음 다시 포토레지스트를 전부 제거하고 상기 비아콘택홀의 노출된 부분의 실리콘 박막을 선택적으로 제거하는 공정과, 상기 선택적으로 실리콘 박막이 제거되는 공정직후의 상기 노출된 하층금속배선 및 절연막 상부에 상층금속막을 형성하여 하층금속배선과 접속한후 패턴공정으로 상층금속배선을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 소자의 다층금속배선 공정 방법.MOSFET, device isolation oxide and capacitor are formed on the silicon substrate, and the insulating film is formed on the whole. Then, the lower metal film and the insulating film of the semiconductor device are sequentially formed, and a portion of the insulating film is etched to form the via contact hole. In the multilayer metal wiring process of forming an upper metal film to form an upper metal film and then connecting the lower metal film, damage to the lower metal film generated when etching a portion of the insulating film to form a via contact, and an oxide film is formed on the lower metal film. In order to prevent the unstable shape of the contact resistance according to the generation, the silicon thin film is formed on the surface of the lower metal film in the same reactor when forming the lower metal film, and then metal wiring is formed by a pattern process and an insulating film is formed on the silicon thin film. Forming a photoresist on a portion of the insulating film on the metal wiring; Removing the insulating layer of the portion where the photoresist is removed to form a via contact hole, and then removing all the photoresist and selectively removing the silicon thin film of the exposed portion of the via contact hole; A multi-layered metal of a semiconductor device, comprising a step of forming an upper metal layer on the exposed lower metal wiring and the insulating layer immediately after the thin film is removed and connecting to the lower metal wiring, and then forming an upper metal wiring by a pattern process. Wiring process method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890007207A 1989-05-30 1989-05-30 Multi-layer wiring method of semiconductor elements Expired KR910010223B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890007207A KR910010223B1 (en) 1989-05-30 1989-05-30 Multi-layer wiring method of semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890007207A KR910010223B1 (en) 1989-05-30 1989-05-30 Multi-layer wiring method of semiconductor elements

Publications (2)

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KR900019169A true KR900019169A (en) 1990-12-24
KR910010223B1 KR910010223B1 (en) 1991-12-21

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KR1019890007207A Expired KR910010223B1 (en) 1989-05-30 1989-05-30 Multi-layer wiring method of semiconductor elements

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KR910010223B1 (en) 1991-12-21

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