KR900014988A - Memory address allocation method and apparatus of data processing apparatus - Google Patents

Abstract

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Description

Memory address allocation method and apparatus of data processing apparatus

Since this is an open matter, no full text was included.

1 is a block diagram showing an embodiment of the present invention;

2 is a block diagram showing a specific example of the control module of FIG.

3 is a diagram showing the format of a physical address;

4 is a diagram showing the format of data set in the control register of FIG.

5 is a block diagram showing a specific example of the state setting circuit of the module selection circuit of FIG.

6 is a block diagram showing another specific example of a module selection circuit and a state setting circuit;

7 is a flowchart showing one embodiment of a memory address allocation method of the present invention.

Claims (6)

Each of the plurality of memory modules 4 includes at least one RAM unit 8, designates one of the plurality of memory modules, and sequentially orders the RAM units in the memory module. A first step for accessing and obtaining a mounting capacity of the memory module, a second step for performing the first step for all the memory modules, and a mounting capacity of each memory module obtained in the first and second steps And a third step of allocating an address to each of the memory modules based on the first address. 2. The method of claim 1 wherein the first step is executed in response to power up. 2. The first step of claim 1, wherein the first step is the same as the fourth step of writing data designated to an address of a feature of one RAM unit of one designated memory module, and the address written in the fourth step. A fifth staff that reads data from an address, a sixth staff that compares the data written by the fourth staff with the data read by the fifth staff, and determines whether there is a match, and the sixth staff According to the mismatch between the seventh step and the sixth step of repeating the fourth to sixth steps with respect to the other RAM units in the same memory module according to the matching of the steps of the memory modules, the mounting capacity of the memory module is determined And an eighth step of repeating the fourth to sixth steps with respect to another memory module. The memory of claim 1, wherein the third staff comprises a staff that sequentially allocates an address from a memory module having a maximum mounting capacity based on a mounting capacity of each memory module obtained in the first and second steps. Address assignment method. The memory module of claim 1, wherein each of the plurality of memory modules includes a register (6), and the third staff includes a step for setting an address assigned to each of the plurality of memory modules in the register (6). Memory address allocation method comprising. Each of the processing apparatus and each of the plurality of memory modules includes a plurality of memory modules 4 including at least one RAM unit 8, and a control module 3 connected between the processing apparatus and the plurality of memory modules. Means means for transmitting address and read / write data between the processing apparatus and the plurality of memory modules (9, 10, 13, 14) and one module for transmitting address and read / write data. A control register 16 having a first field specifying 14 RAM units of a second field and a second field specifying an access mode, and contents of the first field according to a mode designated by the second field. Means for applying to a memory module instead of said address, said processing apparatus including means for setting data in said control register, obtaining a mounting capacity of said memory module, and assigning an address to each memory module; Memory address assignment unit consisting of. ※ Note: The disclosure is based on the initial application.