KR900006898Y1 - Key Lock Circuit on Keyboard - Google Patents
Key Lock Circuit on Keyboard Download PDFInfo
- Publication number
- KR900006898Y1 KR900006898Y1 KR2019870023321U KR870023321U KR900006898Y1 KR 900006898 Y1 KR900006898 Y1 KR 900006898Y1 KR 2019870023321 U KR2019870023321 U KR 2019870023321U KR 870023321 U KR870023321 U KR 870023321U KR 900006898 Y1 KR900006898 Y1 KR 900006898Y1
- Authority
- KR
- South Korea
- Prior art keywords
- flip
- flop
- key
- output
- key lock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/023—Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
- G06F21/83—Protecting input, output or interconnection devices input devices, e.g. keyboards, mice or controllers thereof
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Input From Keyboards Or The Like (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
FF1∼FF6: 플립 플롭 AND1∼AND6: 앤드게이트FF 1 to FF 6 : flip flop AND 1 to AND 6 : and gate
INV1, INV2: 인버터 OR1: 오아게이트INV 1 , INV 2 : Inverter OR 1 : Oagate
KC : 키보드컨트롤러KC: Keyboard Controller
본 고안은 컴퓨터의 키보드에 관한것으로 특히 키잠금(Key Lock)기능을 수행하는 키보드의 키잠금회로에 관한것이다.The present invention relates to a keyboard of a computer, and more particularly to a key lock circuit of a keyboard that performs a key lock function.
종래에는 키보드의 키잠금 기능을 수행하기 위하여 기구적인 스위치를 사용한 키잠금 장치를 사용하였기때문에 제품개발시 금형을 추가시키기 위하여 개발비용이 상승될뿐 아니라 키(열쇠)를 보관해야 하는 번거로움이 있었고 또한 물리적인 키잠금장치를 사용함으로써 제품이 손상되어 미관상의 문제점도 있었다.In the past, since the key lock device using a mechanical switch was used to perform the key lock function of the keyboard, the development cost was increased to add a mold during product development, and there was a need to store keys (keys). In addition, there is aesthetic problems because the product is damaged by using a physical key lock device.
본 고안은 상기와 같은 문제점들을 해결하기 위하여 안출한 것인바, 키보드상의 N개의 키를 순차적으로 누름으로써 키잠금 기능을 수행하고 상기 키잠금에 사용된 키들을 역순으로 눌러줌으로써 키잠금을 해제할 수 있도록 함을 목적으로 한다.The present invention has been devised to solve the above problems, the key lock function by sequentially pressing the N keys on the keyboard can be released by pressing the keys used in the key lock in the reverse order. The purpose is to make it work.
이하 첨부된 도면에 의해서 본 고안을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 고안의 회로도로서 키보드(도시되지않음)로 부터 임의의 키(K0)(K1)입력을 받는 앤드게이트(AND1)는 플립플롭(FF1)의 클럭단(C)에 접속하고 상기 플립플롭(FF1)의 출력(Q)과 키(K2)로 부터 입력을 받는 앤드게이트(AND2)는 플립플롭(FF2)의 클럭단(C)에 접속하며 상기 플립플롭(FF2)의 출력(Q)과 키(K3)로 부터 입력을 받는 앤드게이트(AND3)는 플립플롭(FF3)의 클럭단(C)에 접속한다.FIG. 1 is a circuit diagram of the present invention. An AND gate AND 1 receiving an arbitrary key K 0 (K 1 ) input from a keyboard (not shown) is connected to a clock stage C of a flip-flop FF 1 . An AND gate AND 2 connected to the output Q of the flip-flop FF 1 and an input from the key K 2 is connected to the clock terminal C of the flip-flop FF 2 to connect the flip-flop. The AND gate AND 3 , which receives an input from the output Q of the (FF 2 ) and the key K 3 , is connected to the clock terminal C of the flip-flop FF 3 .
또한 상기 플립플롭(FF1)의 반전출력단(Q)과 키(K2)로 부터 입력을 받는 앤드게이트(AND4)는 플립플롭(FF4)의 클럭단(C)에 접속하고 상기 플립플롭(FF4)의 출력단(Q)과 키(K3)로 부터 입력을 받는 앤드게이트(AND5)는 플립플롭(FF5)의 클럭단(C)에 접속하되 상기 플립플롭(FF1∼FF5)의 입력(J)(K)은 전원(Vcc)과 접속시킨다.Also inverted output terminal (Q) and the key (K 2) the AND gate receiving the input from the (AND 4) is connected to the clock stage (C) of the flip-flop (FF 4) and the flip-flop of the flip-flop (FF 1) (FF 4) an output terminal (Q) of the key (K 3) the aND gate (aND 5) to receive an input from a flip-flop (FF 5) a clock stage (C), but connected to said flip-flop (FF 1 ~FF of 5 ) is connected to the power supply Vcc.
한편 상기 플립플롭(FF1)의 출력단(Q)과 반전출력단(Q)에 접속된 인버터(INV1)(INV2)는 상기 플립플롭(FF2∼FF5)의 리세트단자(R)에 접속하고 상기 플립플롭(FF3)(FF5)의 출력단(Q)으로 부터 입력을 받는 오아게이트(OR1)는 입력단(J)(K)이 전원(Vcc)과 접속된 플립플롭(FF6)의 클럭단(C)에 접속하며 상기 플립플롭(FF6)의 반전출력(Q)과 키 데이타의 입력을 받는 앤드게이트(AND6)는 키보드컨트롤러(KC)에 접속한다.On the other hand, the inverter INV 1 (INV 2 ) connected to the output terminal Q and the inverted output terminal Q of the flip-flop FF 1 is connected to the reset terminal R of the flip-flops FF 2 to FF 5 . An oragate OR 1 connected to and receiving an input from an output terminal Q of the flip-flop FF 3 (FF 5 ) has a flip-flop FF 6 having an input terminal J (K) connected to a power supply Vcc. The AND gate AND 6 , which is connected to the clock terminal C of the N s) and receives the inverted output Q of the flip-flop FF 6 and key data, is connected to the keyboard controller KC.
이하 이들의 작용효과를 설명한다.The effect of these will be described below.
시스템에 전원이 인가되고 초기상태에서 모든 플립플롭은 리세트(R)상태가 되므로 출력단(Q)은 로우상태이고 반전출력단(Q)은 하이상태가 된다.The power is applied to the system and in the initial state all flip-flops are reset (R), so the output stage (Q) is low and the inverted output stage (Q) is high.
키(K10)(K1)를 동시에 누르면 앤드게이트(AND1)의 출력이 하이로 되어 플립플롭(FF1)의 클럭단(C)에 인가되므로 상기 플립플롭(FF1)의 출력(Q)은 하이신호를 출력하며 이 하이신호는 인버터(INV1)에서 로우신호로 반전되어 플립플롭(FF4)(FF5)의 리세트단자(R)에 인가되어 리세트시키므로 상기 플립플롭(FF4)(FF5)의출력(Q)은 로우신호가 되어 오아게이트(OR1)의 한편에 인가되며, 연속하여 키(K2)와 키(K3)를 누르면 상기 플립플롭(FF1)의 출력(Q)이 하이이므로 앤드게이트(AND2)의 출력은 하이가 되어 플립플롭(FF2)의 클럭단(C)에 인가되고 상기 플립플롭(FF2)의 출력(Q)도 하이로 되어 앤드게이트(AND3)의 출력이 또한 하이로 플립플롭(FF3)의 클럭단(C)에 인가되므로 상기 플립플롭(FF3)의 출력(Q)이 하이가 되어 상기 오아게이트(OR1)의 다른 한편에 접속되며 상기 오아게이트(OR1)는 상기 플립플롭(FF3)(FF5)의 출력(Q)신호를 논리합한 하이신호를 출력 플립플롭(FF6)의 클럭단(C)에 인가되어 상기 플립플롭(FF6)의 반전 출력(Q)은 로우가 된다.The output of the key (K 10) pressing (K 1) at the same time is in the output of the AND gate (AND 1) high so applied to the clock stage (C) of the flip-flop (FF 1) the flip-flop (FF 1) (Q ) Outputs a high signal, which is inverted to a low signal by the inverter INV 1 and applied to the reset terminal R of the flip-flop FF 4 (FF 5 ) to reset the flip-flop FF. 4) (FF 5) output (Q) is a low signal Iowa gate is applied to the other hand of the (OR 1), continuously pressing the key (K 2) and the key (K 3) the flip-flop (FF 1) Since the output (Q) to the high output of the aND gate (aND 2) is to be at a high is applied to the clock stage (C) of the flip-flop (FF 2) the output (Q) of said flip-flop (FF 2) high the AND gate (AND 3) the output is also so applied to the clock stage (C) of the flip-flop (FF 3) to the high output (Q) of said flip-flop (FF 3) it is a high the Iowa gate (OR 1 of Fold on the other Is the Iowa gate (OR 1) is the flip-flop (FF 3) (FF 5) of the output (Q) is applied to a high signal to OR the signal to the clock stage (C) of the output flip-flop (FF 6) the flip The inverting output Q of the flop FF 6 goes low.
따라서 이 로우신호가 앤드게이트(AND6)의 한편에 인가되므로 상기 앤드게이트(AND6)의 다른 한펀에 인가되는 키 데이타는 키보드 컨트롤러(KC)에 전달되지 못하여 키잠금(Key Lock)상태에 놓이게 된다.Therefore, since the application on the other hand in a low signal is the AND gate (AND 6) the key data to be applied to the other hanpeon of the AND gate (AND 6) is placed in mothayeo be delivered to the keyboard controller (KC) key lock (Key Lock) state do.
이 상태에서 상기 키잠금을 해제하기 위하여 상기 키(K0)(K1)를 동시에 누르면 앤드게이트(AND1)를 통하여 플립플롭(FF1)에 인가된 신호가 반전출력(Q)을 로우에서 하이로 되며 이 하이신호를 인버터(INV2)를 거쳐 로우신호로 반전되어 플립플롭(FF2)(FF3)을 리세트(R)시키고 연속되는 키(K2)(K3)의 조작에 의해 상기(FF2)(FF3)은 아무런 영향을 받지 않는다.In this state, when the keys K 0 and K 1 are simultaneously pressed to release the key lock, the signal applied to the flip-flop FF 1 through the AND gate AND 1 causes the inverting output Q to be low. High signal is inverted to a low signal through the inverter INV 2 to reset the flip-flop FF 2 (FF 3 ) and to operate the consecutive keys K 2 (K 3 ). By this (FF 2 ) (FF 3 ) is not affected at all.
따라서 상기 플립플롭(FF3)의 출력은 로우가 되어 오아게이트(OR1)에 인가되지만 상기 플립플롭(FF6)의 클럭(C)단자는 로우에서 하이가 될때만 반전출력(Q)을 반전시키므로 상기 플립플롭(FF6)의 반전출력(Q)은 여전히 로우상태로 남아있게 된다.Accordingly, the output of the flip-flop FF 3 goes low and is applied to the OR gate OR 1 , but the inverting output Q is inverted only when the clock C terminal of the flip-flop FF 6 goes low from high. Inverting output Q of the flip-flop FF 6 is still low.
한편 상기 키(K2)의 누름에 의하여 앤드게이트(AND4)의 출력이 하이가 되고 이 하이신호는 플립플롭(FF4)의 출력신호(Q)를 하이로 만들며 이어서 상기 키(K3)의 누름에 의해 앤드게이트(AND5)역시 출력이 하이이고 이 하이신호는 플립플롭(FF6)의 클럭(C)단에 영향을 주어 상기 플립플롭(FF6)의 반전출력단(Q)을 로우에서 하이로 반전시키고 이에따라 키데이타 신호는 앤드게이트(AND6)를 통하여 키보드 컨트롤러(KC)에 전달되므로 키잠금상태는 풀린상태가 되는 것이다.On the other hand, by pressing the key K 2 , the output of the AND gate AND 4 becomes high, and this high signal makes the output signal Q of the flip-flop FF 4 high, followed by the key K 3 . aND gate by a press (aND 5) also output is high and a high signal by influencing the clock (C) terminal of the flip-flop (FF 6) low the inverted output terminal (Q) of said flip-flop (FF 6) The key lock state is released by inverting from high to accordingly and the key data signal is transmitted to the keyboard controller KC through the AND gate AND 6 .
상기한 바와같이 본 고안은 임의의 두키를 동시에 누른후 다시 임의의 키를 순서대로 누르면 키잠금상태가 되고 다시한번 그 동작을 그대로 반복하면 키 잠금 상태가 해제되는 효과가 있는 것이다.As described above, the present invention has a key locking state by pressing any two keys at the same time and then pressing any key again in sequence, and once again, the key lock state is released.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870023321U KR900006898Y1 (en) | 1987-12-28 | 1987-12-28 | Key Lock Circuit on Keyboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870023321U KR900006898Y1 (en) | 1987-12-28 | 1987-12-28 | Key Lock Circuit on Keyboard |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890014178U KR890014178U (en) | 1989-08-10 |
| KR900006898Y1 true KR900006898Y1 (en) | 1990-08-02 |
Family
ID=19270848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870023321U Expired KR900006898Y1 (en) | 1987-12-28 | 1987-12-28 | Key Lock Circuit on Keyboard |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR900006898Y1 (en) |
-
1987
- 1987-12-28 KR KR2019870023321U patent/KR900006898Y1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| KR890014178U (en) | 1989-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910010529A (en) | Shift register device | |
| JPS5284938A (en) | Logic circuit | |
| EP0330971A3 (en) | Flip-flop circuit | |
| KR840000114A (en) | Phase comparator | |
| KR900006898Y1 (en) | Key Lock Circuit on Keyboard | |
| KR910007266A (en) | Clock and Control Signal Generation Circuit | |
| JPS5477533A (en) | Signal generating device | |
| JPS5478926A (en) | Digital set circuit | |
| GB1464842A (en) | Resettable toggle flip-flop | |
| SU943693A1 (en) | Data input device | |
| JPS562047A (en) | Debugging unit | |
| KR940001487Y1 (en) | Noise-Free Circuit of Clock Signal | |
| SU809352A1 (en) | Information recording apparatus | |
| JPS6461813A (en) | Key matrix switching circuit | |
| RU1790012C (en) | Device for input of information | |
| JPS5534763A (en) | Keyboard input device | |
| KR930004892Y1 (en) | Latching circuit | |
| JPS5450231A (en) | Encode circuit for contactless switch | |
| SU1251059A1 (en) | Information input device | |
| JPS6424516A (en) | Crc check circuit | |
| KR940006928Y1 (en) | Counter circuit with random initial value | |
| SU1037233A1 (en) | Data input device | |
| GB1501452A (en) | Digital signal sampling circuit | |
| JPS5638653A (en) | Semiconductor integrated circuit having conventionality | |
| JPS5473520A (en) | Keyboard input circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19871228 |
|
| UA0201 | Request for examination |
Patent event date: 19871228 Patent event code: UA02012R01D Comment text: Request for Examination of Application |
|
| UG1501 | Laying open of application | ||
| UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19900630 |
|
| E701 | Decision to grant or registration of patent right | ||
| UE0701 | Decision of registration |
Patent event date: 19901101 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
|
| REGI | Registration of establishment | ||
| UR0701 | Registration of establishment |
Patent event date: 19910201 Patent event code: UR07011E01D Comment text: Registration of Establishment |
|
| UR1002 | Payment of registration fee |
Start annual number: 1 End annual number: 3 Payment date: 19910201 |
|
| UR1001 | Payment of annual fee |
Payment date: 19930330 Start annual number: 4 End annual number: 4 |
|
| UR1001 | Payment of annual fee |
Payment date: 19940801 Start annual number: 5 End annual number: 5 |
|
| UR1001 | Payment of annual fee |
Payment date: 19950727 Start annual number: 6 End annual number: 6 |
|
| UR1001 | Payment of annual fee |
Payment date: 19960730 Start annual number: 7 End annual number: 7 |
|
| UR1001 | Payment of annual fee |
Payment date: 19970724 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 19980728 Year of fee payment: 9 |
|
| UR1001 | Payment of annual fee |
Payment date: 19980728 Start annual number: 9 End annual number: 9 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| UC1903 | Unpaid annual fee |