[go: up one dir, main page]

KR900006809Y1 - Control and noise reduction circuit of double deck cassette - Google Patents

Control and noise reduction circuit of double deck cassette Download PDF

Info

Publication number
KR900006809Y1
KR900006809Y1 KR2019850017290U KR850017290U KR900006809Y1 KR 900006809 Y1 KR900006809 Y1 KR 900006809Y1 KR 2019850017290 U KR2019850017290 U KR 2019850017290U KR 850017290 U KR850017290 U KR 850017290U KR 900006809 Y1 KR900006809 Y1 KR 900006809Y1
Authority
KR
South Korea
Prior art keywords
resistor
output
grounded
switch
nand gate
Prior art date
Application number
KR2019850017290U
Other languages
Korean (ko)
Other versions
KR870011158U (en
Inventor
박영선
Original Assignee
삼성전자 주식회사
정재은
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 정재은 filed Critical 삼성전자 주식회사
Priority to KR2019850017290U priority Critical patent/KR900006809Y1/en
Publication of KR870011158U publication Critical patent/KR870011158U/en
Application granted granted Critical
Publication of KR900006809Y1 publication Critical patent/KR900006809Y1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/24—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Amplifiers (AREA)

Abstract

내용 없음.No content.

Description

더블데크 콘트롤 및 잡음 제거회로Double Deck Control and Noise Canceling Circuit

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 스위치(T1,T2,R/P)의 조합 데이터와 그 기능과의 관계를 나타낸 표.2 is a table showing the relationship between the combined data of the switches (T 1 , T 2 , R / P) and their functions.

제3도는 제1도의 각 지점(A∼E)의 타임 챠트.3 is a time chart of the points A to E of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

R1,R14: 저항 T1,T2: 플레이 버튼 스위치R 1 , R 14 : Resistor T 1 , T 2 : Play Button Switch

R/P, SW : 레코드/플레이 스위치 S : 전원스위치R / P, SW: Record / Play Switch S: Power Switch

D1,D4: 다이오드 TR1,TR3: 트랜지스터D 1 , D 4 : Diode TR 1 , TR 3 : Transistor

C1,C4: 콘덴서 ND1,ND4: 낸드게이트C 1 , C 4 : Condenser ND 1 , ND 4 : NAND Gate

NR1, NR4: 노아게이트 Q1: 테이프 1뮤트 단자NR 1 , NR 4 : Noah gate Q 1 : Tape 1 mute terminal

Q2: 출력 뮤트 단자 Q3,Q4: 더빙 제어단자Q 2 : Output mute terminal Q 3 , Q 4 : Dubbing control terminal

본 고안은 더블 데크 콘트롤(Double Deck Control) 및 잡음제거(pop noise mute)회로에 관한 것이다.The present invention relates to a double deck control and pop noise mute circuit.

종래의 카세트 더블 데크의 각 기능을 선택함에 있어서 각 기능 스위치를 일일이 조작해야 하는 불편성과 전원의 공급 및 차단시에 잡음이 생기는 단점이 있었다.In selecting the functions of the conventional cassette double deck, there are disadvantages in that each function switch has to be operated manually and noise occurs when power is supplied and cut off.

따라서 본 고안의 목적은 더블데크의 각 기능을 고안된 논리회로에 의해 자동으로 제어하고 잡음을 제거하는 데 있다.Therefore, the purpose of the present invention is to automatically control each function of the double deck by the designed logic circuit and to remove noise.

이하, 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

제1도는 전원(Vcc)은 콘덴서(C1)를 거쳐서 접지에 연결하고, 전원(Vcc)과 연결된 저항(R3)은 접지된 스위치(T1)과 연결하고, 노아게이트(NR1)의 출력과 다이오드(D1)(D2)를 접지시킨 저항(R4)과 병렬연결하여 출력된 데이타를 입력으로 하는 앤드게이트(ND1)를 거쳐서 테이프 1뮤트단자(Q1)에 인가하고, 전원(Vcc)과 연결된 저항(R2)은 접지된 스위치(T2)와 연결하고 저항(R2)을 거친 출력과 저항(R3)을 거친 출력이 앤드게이트(ND2)를 통하여 출력된 데이터와 접지된 콘덴서(C2)에 연결된 전원(Vcc) 및 저항(R5)(R8)을 거친 출력데이터는 앤드게이트(ND3)(ND4)와 저항(R7) 및 트랜지스터(TR3)를거쳐서 출력뮤트(Mute) 단자(Q2)에 인가되고, 접지된 레코드/플레이 스위치(R/P SW)와 연결된 저항(R1)과 저항(R2)(R3)을 거친 출력은 노아게이트(NR2)(NR3)(NR4)를 거쳐서 더빙(Dubbing) 제어단자(Q3)에 인가되고, 상기 낸드게이트(ND4)의 출력과 연결된 저항(R9)(R10)은 저항(R9)을 거친 출력에 따라 전원(Vcc)을 도통시키게 하는 트랜지스터(TR2)를 거쳐서 더빙 제어단자(Q4)에 인가되고, 전원스위치(S)는 저항(R12)을 접지된 저항(R13)과 접지된 콘덴서(C4)와 병렬연결하여 역방향 다이오드(D3)의 출력을 다이오드(D4)에 연결하고, 다이오드(D4)를 접지된 콘덴서(C3)와 병렬연결하여 저항(R14)을 거치고 전원(Vcc)은 저항(R11)을 거쳐서 트랜지스터(TR1)와 연결시킨 회로도이다.1 shows a power supply Vcc connected to ground via a condenser C 1 , a resistor R 3 connected to a power supply Vcc connected to a grounded switch T 1 , and a no-gate NR 1 . The output is connected to the tape 1 mute terminal (Q 1 ) via an AND gate (ND 1 ) for inputting the output data by connecting the output (D 1 ) (D 2 ) to the ground (R 4 ) in parallel. The resistor (R 2 ) connected to the power supply (Vcc) is connected to the grounded switch (T 2 ) and the output through the resistor (R 2 ) and the output through the resistor (R 3 ) are output through the AND gate (ND 2 ). Data and output data through the power supply (Vcc) and resistor (R 5 ) (R 8 ) connected to the grounded capacitor (C 2 ) are connected to the gate (ND 3 ) (ND 4 ), resistor (R 7 ) and transistor (TR). The output is applied to the output mute terminal (Q 2 ) via 3 ), and then through the resistor (R 1 ) and resistor (R 2 ) (R 3 ) connected to the grounded record / play switch (R / P SW). is a NOR gate (NR 2) (NR 3) (NR 4) Through dubbing (Dubbing) control is applied to the terminal (Q 3), an output and a resistor (R 9) connected (R 10) is a power supply (Vcc) in accordance with the rough output resistance (R 9) of said NAND gate (ND 4) Is applied to the dubbing control terminal (Q 4 ) via a transistor (TR 2 ) for conducting electrical current, and the power switch (S) connects the resistor (R 12 ) to the grounded resistor (R 13 ) and the grounded capacitor (C 4 ). The parallel connection connects the output of the reverse diode (D 3 ) to the diode (D 4 ), and connects the diode (D 4 ) in parallel with the grounded capacitor (C 3 ) through the resistor (R 14 ) and the power supply (Vcc) The circuit diagram is connected to the transistor TR 1 via a resistor R 11 .

제2도는 전원스위치(S)에 의한 각 지점(A∼E)의 챠임챠트(Time Chart)이고, 제3도는 스위치(T1,T2,R/P SW)의 조합 데이터에 따른 그 출력되는 기능과의 관계를 나타낸 표이다.2 is a time chart of each point A to E by the power switch S, and FIG. 3 is outputted according to the combination data of the switches T 1 , T 2 and R / P SW. This table shows the relationship with functions.

다음은 상기와 같이 구성된 본 고안의 회로동작에 관한 것이다.The following relates to a circuit operation of the present invention configured as described above.

제2도에서와 같이 더블데크 제어동작상태는 스위치(TS1)(R/PSW)의 데이터가 전부 "0"일때 스위치(T1)(T2)가 "ON"되고, 레코드/플레이스위치(R/P SW)는 레코드 단자(R)에 연결되고, 전원(Vcc)과 연결된 저항(R3)을 거쳐 흐르는 전류는 접지에 흘러 노아게이트(NR1)에 입력전압이 "L"이 되어 출력이 "H"가 된다.As shown in FIG. 2, the double deck control operation state is that when the data of the switch TS 1 (R / PSW) is all "0", the switch T 1 (T 2 ) is "ON", and the record / play switch ( The R / P SW is connected to the record terminal R, and the current flowing through the resistor R 3 connected to the power supply Vcc flows to the ground, and the input voltage becomes “L” at the noar gate NR 1 . Becomes "H".

저항(R2)을 거쳐서 흐르는 전류와 저항(R1)을 거쳐서 흐르는 전류는 스위치(T2)(R/P SW)에 접지되어 흐르고 노아게이트(NR2)(NR3)와 낸드게이트(ND4)를 거쳐서 출력된 전압은 "L"이 되지만 저항(R9)을 거쳐서 흐르는 전류가 트랜지스터(TR2)를 동작시킨다. 다이오드(D2)의 출력과 노아게이트(NR1)의 출력을 낸드게이트(ND4)을 거쳐 테이프 1뮤트단자(Q1)에 "L"로 출력되고, 저항(R2)(R3)을 거쳐 흐르는 전류는 낸드게이트(ND2)(ND3)와 노아게이트(NR4) 및 저항(R7)을 거쳐 "H"가 되어 트랜지스터(TR3)이 도통되어 출력뮤트단자(Q2)가 "L"로 출력되고, 상기 낸드게이트(ND4)의 출력이 더빙제어단자(Q3)에 인가되어 "L"로 출력되고, 트랜지스터(TR2)의 출력이 더빙제어단자(Q4)에 인가되어 "H"로 출력되어서 더블데크의 테이프 1뮤트단자는 플레이되고 테이프 2뮤트단자는 동작되어 녹음된다.The current flowing through the resistor R 2 and the current flowing through the resistor R 1 are grounded to the switch T 2 (R / P SW), and the NOR gate NR 2 (NR 3 ) and the NAND gate (ND). The voltage output via 4 ) becomes "L", but the current flowing through the resistor R 9 operates the transistor TR 2 . The output of the diode D 2 and the output of the noar gate NR 1 are output as “L” to the tape 1 mute terminal Q 1 through the NAND gate ND 4 , and the resistor R 2 (R 3 ). The current flowing through the NAND gate ND 2 (ND 3 ), the noah gate NR 4 , and the resistor R 7 becomes “H” so that the transistor TR 3 conducts and the output mute terminal Q 2 is applied. Is output as "L", the output of the NAND gate ND 4 is applied to the dubbing control terminal Q 3 , and is output as "L", and the output of the transistor TR 2 is the dubbing control terminal Q 4 . It is output to "H", and the tape 1 mute terminal of the double deck is played and the tape 2 mute terminal is operated to record.

만일, 스위치(T1)(T2)가 "ON"되고 레코드/플레이 스위치(R/P SW)는 플레이단자(P)에 연결되면, 전원(Vcc)은 저항(R3)를 거쳐 노아게이트(NR1)에 "H"로 출력되고, 저항(R2)을 거쳐서 다이오드(D1)의 "L"출력과 저항(R1) 및 노아게이트(NR2)(NR3)와 낸드게이트(ND3)의 출력이 "H"가 되어서 트랜지스터(TR2)가 작동되지 않아 다이오드(D2)의 출력이 "L"가 되어서 다이오드(D2)의 "L"출력이 낸드게이트(ND1)를 거쳐 테이프 1뮤트단자(Q1)에 "H"가 출력되고, 저항(R2)(R3)이 흐르는 전원(Vcc)이 낸드게이트(ND2)(ND3)와 노아게이트(NR4) 및 저항(R7)을 거쳐서 "H"가 되어 트랜지스터(TR3)를 작동시켜 출력뮤트단자(Q2)에 "L"이 출력되고, 전원(Vcc)이 저항(R1∼R3) 및 노아게이트(NR2∼NR3)와 낸드게이트(ND4)를 거쳐서 더빙제어단자(Q3)에 "H"가 출력되고, 상기한 낸드게이트(TR2)의 출력이 더빙제어단자(Q4)에 인가되어 "L"이 출력되어서 테이프 1데크와 테이프 2데크가 동시에 플레이되고 테이프 1데크는 뮤트된다.If the switch T 1 (T 2 ) is turned “ON” and the record / play switch R / P SW is connected to the play terminal P, the power supply Vcc passes through the resistor R 3 to the noah gate. It is output as "H" to NR 1 , and through the resistor R 2 , the "L" output of the diode D 1 , the resistor R 1 , the noble gate NR 2 (NR 3 ) and the NAND gate ( ND 3) outputs an "L" output of the diode (D 2) output is not be the "L" of the transistor (TR 2) does not work, the diode (D 2) be a "H" of this NAND gate (ND 1) the through "H" on the tape 1 muting terminal (Q 1) are output, and a resistance (R 2) (R 3) is flowing in the power (Vcc) is a NAND gate (ND 2) (ND 3) and NOR gate (NR 4 ) And the resistor (R 7 ) become " H " to operate the transistor TR 3 to output " L " to the output mute terminal Q 2 , and the power supply Vcc is the resistor R 1 to R 3 . and a NOR gate (NR 2 ~NR 3) and NAND gate (ND 4) through the output and the "H" in the dubbing control terminal (Q 3), the one to the NAND Bit output of the (TR 2) dubbing is applied to the control terminal (Q 4) "L" By this output, the tape deck 1 and the tape deck 2 is played at the same time the tape deck 1 is muted.

다음의 여러동작은 상술한 바와같이 동작되어서 스위치(T1)(T2)(R/P SW)에 따른 그 기능의 출력데이터를 제2도의 표와같이 얻을 수 있다.The following several operations are operated as described above to obtain output data of the function according to the switches T 1 (T 2 ) (R / P SW) as shown in the table of FIG.

한편, 폽 노이즈 뮤트(Pop Noise Mute) 동작은, 1) 전원스위치(S)가 "ON"될때, 다이오드(D4)를 통한 "+"전류는 콘덴서(C3)를 충전시킨 후 저항(R4)를 통하여 흐르게 되고 역방향 다이오드(D3)를 통한 "-" 전류는 콘덴서(C4)를 충전시킨 후 저항(R12)을 통해 흐르게 된다.On the other hand, the Pop Noise Mute operation is performed in the following manner: 1) When the power switch S is "ON", the "+" current through the diode D 4 charges the capacitor C 3 and then the resistor R 4 ) and "-" current through the reverse diode (D 3 ) flows through the resistor (R 12 ) after charging the capacitor (C 4 ).

그러나 콘덴서(C3∼C4) 용량의 차(C3∼C4)때문에 "+" 전류가 콘덴서(C3)에 충전되는 시간보다 빨리 콘덴서(C4)를 충전한 "-" 전류가 콘덴서(C3)에 충전될때까지 "A" 지점의 출력이 "L"가 되어 트랜지스터(TR1)는 동작이 안되지만 콘덴서(C2)에 의해 "B" 지점의 출력이 점차 증가한다.However, the capacitor (C 3 ~C 4) the capacity of the car (C 3 ~C 4) Since "+" current of the capacitor (C 3) charged by the fast capacitor (C 4) than the time charged to the "-" current of the capacitor The output of the "A" point becomes "L" until it is charged to (C 3 ), so that the transistor TR 1 does not operate, but the output of the "B" point gradually increases by the capacitor C 2 .

그러므로 저항(R8)에 "H"값이 입력되어 낸드게이트(ND3)의 출력("C" 지점)이 "H"가 되고 노아게이트(NR4)를 거친 저항(R7)의 출력("D" 지점)이 "H"가 되어 저항(R6)에 전류가 흐르게 되어서 트랜지스터(TR3)가 도통되어 출력뮤트단자(Q2)에는 "L"가 나타난다.Therefore, the value "H" is input to the resistor R 8 so that the output of the NAND gate ND 3 (point "C") becomes "H" and the output of the resistor R 7 passing through the noah gate NR 4 ( The point "D" becomes "H" so that a current flows in the resistor R 6 so that the transistor TR 3 conducts, and "L" appears in the output mute terminal Q 2 .

따라서 잡음은 없어지고 순수한 출력만이 콘덴서(C3)가 충전된 후 나타나게 된다.Therefore, the noise disappears and only the pure output appears after the capacitor C 3 is charged.

2) 전원스위치(S)가 "OFF"될때, 전원스위치(S)가 "OFF"되면 순간적으로 콘덴서(C1)(C2)에 충전된 전류가 저항(R6)(R8)을 통하여 트랜지스터(TR3)를 도통시켜 잡음의 출력을 방지한다.2) When the power switch S is "OFF", when the power switch S is "OFF", the current charged in the capacitor (C 1 ) (C 2 ) is instantaneously through the resistor (R 6 ) (R 8 ) The transistor TR 3 is turned on to prevent the output of noise.

그리고 콘덴서(C3)에 충전된 전류는 트랜지스터(TR1)를 순간적으로 도통시켜 이중으로 잡음을 방지한다.The current charged in the capacitor C 3 conducts the transistor TR 1 momentarily to prevent noise.

이때 제3도에서 각 지점(A∼E)의 타임챠트를 참고하면 명확히 알 수 있다.At this time, it can be clearly seen by referring to the time chart of each point A to E in FIG.

상술한 바와같이 더빙데크(DEBBING DECK)의 각 기능을 하나하나 조작치 않고 본 고안의 회로에 의거하여 제어하면서 전원의 공급 및 차단시에 잡음을 제거할 수 있어서 제품을 고급화할 수 있는 장점이 있다.As described above, it is possible to remove noise during power supply and interruption while controlling based on the circuit of the present invention without operating each function of the DEBBING DECK one by one, thereby improving the product. .

Claims (1)

접지된 콘덴서(C1)와 연결한 전원(Vcc)을 저항(R3)을 거쳐서 접지된 스위치(T1)과 연결하고, 노아게이트(NR1)의 출력데이타와 다이오드(D1∼D2)를 접지시킨 저항(R4)과 병렬연결하여 출력된 데이터를 입력으로 하는 낸드게이트(ND1)를 거쳐서 테이프 1뮤트 단자(Q1)에 인가하는 회로부와, 전원(Vcc)과 연결된 저항(R2)은 접지된 스위치(T2)와 연결하고 저항(R2)을 거친 출력과 저항(R3)을 거친 출력이 낸드게이트(ND2)를 통하여 출력된 데이터와 접지된 콘덴서(C2)에 연결된 전원(Vcc) 및 저항(R5)(R8)을 거친 데이터는 낸드게이트(ND3)와 노아게이트(NR4)는 저항(R7) 및 트랜지스터(TR3)를 거쳐서 출력뮤트단자(Q2)에 인가되는 회로부와, 접지된 레코드/플레이스위치(R/P SW)와 연결된 저항(R1)과 저항(R2∼R3)을 거친 출력은 노아게이트(NR2∼NR3)와 낸드게이트(ND4)를 거쳐서 더빙 제어단자(Q3)에 인가하는 회로부와, 상기 낸드게이트(ND4)의 출력과 연결된 저항(R9∼R10)을 거친 출력에 따라 전원(Vcc)을 도통시키게 하는 트랜지스터(TR2)를 거쳐서 더빙제어단자(Q4)에 인가하는 회로부와, 전원스위치(S)는 저항(R12)을 접지된 저항(R13)과 접지된 콘덴서(C4)와 병렬 연결하여 역방향 다이오드(D3)의 출력을 다이오드(D4)에 연결하고 다이오드(D4)의 출력을 접지된 콘덴서(C3)와, 병렬연결하여 저항(R14)을 거치고 전원(Vcc)은 저항(R11)을 거쳐서 트랜지스터(TR1)와 연결시킨 회로부 등으로 구성된 것을 특징으로 하는 더블데크 콘트롤 및 잡음제거 회로.The power supply (Vcc) connected to the grounded capacitor (C 1 ) is connected to the grounded switch (T 1 ) via a resistor (R 3 ), and the output data of the noble gate (NR 1 ) and the diode (D 1 to D 2). ) Is connected in parallel with the grounded resistor (R 4 ) and the circuit section is applied to the tape 1 mute terminal (Q 1 ) through the NAND gate (ND 1 ) for inputting the output data, and the resistor ( R 2 ) is connected to the grounded switch (T 2 ) and the output via the resistor (R 2 ) and the output via the resistor (R 3 ) through the NAND gate (ND 2 ) and the grounded capacitor (C 2) Data passed through power supply (Vcc) and resistor (R 5 ) (R 8 ) connected to NAND gate (ND 3 ) and NOR gate (NR 4 ) are output muted through resistor (R 7 ) and transistor (TR 3 ). The output via the circuit part applied to the terminal Q 2 , the resistor R 1 connected to the grounded record / play switch R / P SW, and the resistors R 2 to R 3 are noar gates NR 2 to NR. 3 ) and And circuitry for applying to the NAND gate dubbing control terminal (Q 3) via an (ND 4), the power supply (Vcc) in accordance with an output resistance (R 9 ~R 10) connected to said NAND gate (ND 4) to output the rough The circuit portion applied to the dubbing control terminal Q 4 via the transistor TR 2 to conduct, and the power switch S has a resistor R 12 grounded to a resistor R 13 and a grounded capacitor C 4 . and parallel connection by going through a reverse diode (D 3) connected to the output diode (D 4) and a diode (D 4) and a grounded output capacitor (C 3), the parallel connection of the resistance (R 14) power ( Vcc) is a double deck control and noise reduction circuit comprising a circuit portion connected to the transistor (TR 1 ) through a resistor (R 11 ).
KR2019850017290U 1985-12-21 1985-12-21 Control and noise reduction circuit of double deck cassette KR900006809Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019850017290U KR900006809Y1 (en) 1985-12-21 1985-12-21 Control and noise reduction circuit of double deck cassette

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019850017290U KR900006809Y1 (en) 1985-12-21 1985-12-21 Control and noise reduction circuit of double deck cassette

Publications (2)

Publication Number Publication Date
KR870011158U KR870011158U (en) 1987-07-15
KR900006809Y1 true KR900006809Y1 (en) 1990-07-28

Family

ID=19247405

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019850017290U KR900006809Y1 (en) 1985-12-21 1985-12-21 Control and noise reduction circuit of double deck cassette

Country Status (1)

Country Link
KR (1) KR900006809Y1 (en)

Also Published As

Publication number Publication date
KR870011158U (en) 1987-07-15

Similar Documents

Publication Publication Date Title
KR900006809Y1 (en) Control and noise reduction circuit of double deck cassette
US4318006A (en) Switching system
JP3089873B2 (en) Output circuit
KR840001563Y1 (en) Recording muting circuit using pause switch
KR900002630Y1 (en) Noise reduction system of double deck cassette tape recorder
JPH018026Y2 (en)
JPH0416243Y2 (en)
JPH0425661Y2 (en)
JPS6040966Y2 (en) Tape recorder muting circuit
KR850002940Y1 (en) Pause circuit for non-signal
KR880004218Y1 (en) Function selection automatic switching circuit in audio equipment
JPH042502Y2 (en)
KR860000364Y1 (en) Switching circuit for automatic music selecting and editing
KR880000037Y1 (en) Muting circuit in double deck recorder
KR930003725Y1 (en) Muting circuit of cdp
KR870002317Y1 (en) Malfunction prevention circuit in electronic drive cassette deck
KR860001399B1 (en) Fader circuit of tape recorder
JPS6112581Y2 (en)
US5019921A (en) Pop noise removing circuit for a double deck cassette tape recorder
KR910001941Y1 (en) Condenser microphone muting circuit
KR860000598Y1 (en) High-load percepting circuit of direct current motor
KR890004239Y1 (en) Multi-function muting circuit
KR880000038Y1 (en) Muting circuit in devices with recording and playback functions
KR920004062Y1 (en) Malfunction protection circuit for muting circuit
KR940002016Y1 (en) Hi-fi signal and normal signal automatic switching circuit of vcr

Legal Events

Date Code Title Description
UA0108 Application for utility model registration

Comment text: Application for Utility Model Registration

Patent event code: UA01011R08D

Patent event date: 19851221

UG1501 Laying open of application
A201 Request for examination
UA0201 Request for examination

Patent event date: 19871106

Patent event code: UA02012R01D

Comment text: Request for Examination of Application

Patent event date: 19851221

Patent event code: UA02011R01I

Comment text: Application for Utility Model Registration

UG1604 Publication of application

Patent event code: UG16041S01I

Comment text: Decision on Publication of Application

Patent event date: 19900630

E701 Decision to grant or registration of patent right
UE0701 Decision of registration

Patent event date: 19901027

Comment text: Decision to Grant Registration

Patent event code: UE07011S01D

REGI Registration of establishment
UR0701 Registration of establishment

Patent event date: 19910109

Patent event code: UR07011E01D

Comment text: Registration of Establishment

UR1002 Payment of registration fee

Start annual number: 1

End annual number: 3

Payment date: 19910109

UR1001 Payment of annual fee

Payment date: 19930326

Start annual number: 4

End annual number: 4

UR1001 Payment of annual fee

Payment date: 19940628

Start annual number: 5

End annual number: 5

UR1001 Payment of annual fee

Payment date: 19950529

Start annual number: 6

End annual number: 6

UR1001 Payment of annual fee

Payment date: 19960627

Start annual number: 7

End annual number: 7

FPAY Annual fee payment

Payment date: 19961231

Year of fee payment: 8

UR1001 Payment of annual fee

Payment date: 19961231

Start annual number: 8

End annual number: 8

LAPS Lapse due to unpaid annual fee
UC1903 Unpaid annual fee