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KR900001598B1 - The decoder circuit of semiconductor memory device - Google Patents

The decoder circuit of semiconductor memory device

Info

Publication number
KR900001598B1
KR900001598B1 KR8603882A KR860003882A KR900001598B1 KR 900001598 B1 KR900001598 B1 KR 900001598B1 KR 8603882 A KR8603882 A KR 8603882A KR 860003882 A KR860003882 A KR 860003882A KR 900001598 B1 KR900001598 B1 KR 900001598B1
Authority
KR
South Korea
Prior art keywords
signal
power source
memory device
semiconductor memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR8603882A
Other languages
English (en)
Other versions
KR860009418A (ko
Inventor
Masanobu Yosida
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of KR860009418A publication Critical patent/KR860009418A/ko
Application granted granted Critical
Publication of KR900001598B1 publication Critical patent/KR900001598B1/ko
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
KR8603882A 1985-05-20 1986-05-19 The decoder circuit of semiconductor memory device Expired KR900001598B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60107826A JPS61265794A (ja) 1985-05-20 1985-05-20 半導体記憶装置のデコ−ダ回路
JP60-107826 1985-05-20

Publications (2)

Publication Number Publication Date
KR860009418A KR860009418A (ko) 1986-12-22
KR900001598B1 true KR900001598B1 (en) 1990-03-15

Family

ID=14469015

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8603882A Expired KR900001598B1 (en) 1985-05-20 1986-05-19 The decoder circuit of semiconductor memory device

Country Status (5)

Country Link
US (1) US4730133A (ko)
EP (1) EP0202910B1 (ko)
JP (1) JPS61265794A (ko)
KR (1) KR900001598B1 (ko)
DE (1) DE3680822D1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366789A (ja) * 1986-09-09 1988-03-25 Mitsubishi Electric Corp Ｃｍｏｓ行デコ−ダ回路
US4851716A (en) * 1988-06-09 1989-07-25 National Semiconductor Corporation Single plane dynamic decoder
JP2555165B2 (ja) * 1988-10-27 1996-11-20 富士通株式会社 ナンド回路
US5157283A (en) * 1988-12-23 1992-10-20 Samsung Electronics Co., Ltd. Tree decoder having two bit partitioning
JPH04184793A (ja) * 1990-11-20 1992-07-01 Nec Corp 半導体デコード装置
US5396459A (en) * 1992-02-24 1995-03-07 Sony Corporation Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line
US6384623B1 (en) 1993-01-07 2002-05-07 Hitachi, Ltd. Semiconductor integrated circuits with power reduction mechanism
KR100281600B1 (ko) * 1993-01-07 2001-03-02 가나이 쓰도무 전력저감 기구를 가지는 반도체 집적회로
US7388400B2 (en) * 1993-01-07 2008-06-17 Elpida Memory, Inc. Semiconductor integrated circuits with power reduction mechanism
US5389836A (en) * 1993-06-04 1995-02-14 International Business Machines Corporation Branch isolation circuit for cascode voltage switch logic
US5995016A (en) * 1996-12-17 1999-11-30 Rambus Inc. Method and apparatus for N choose M device selection
CN104993574B (zh) * 2015-07-06 2017-06-06 上海巨微集成电路有限公司 一种适用于otp存储器的电源切换电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5931253B2 (ja) * 1972-08-25 1984-08-01 株式会社日立製作所 デプレツシヨン型負荷トランジスタを有するｍｉｓｆｅｔ論理回路
JPS50105031A (ko) * 1974-01-23 1975-08-19
JPS5979487A (ja) * 1982-10-27 1984-05-08 Nec Corp デコ−ダ回路
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置

Also Published As

Publication number Publication date
DE3680822D1 (de) 1991-09-19
KR860009418A (ko) 1986-12-22
JPS61265794A (ja) 1986-11-25
US4730133A (en) 1988-03-08
EP0202910A3 (en) 1989-05-24
EP0202910B1 (en) 1991-08-14
EP0202910A2 (en) 1986-11-26

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040310

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee