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KR890007400A - 트렌치 에칭법 - Google Patents

트렌치 에칭법 Download PDF

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Publication number
KR890007400A
KR890007400A KR1019880013917A KR880013917A KR890007400A KR 890007400 A KR890007400 A KR 890007400A KR 1019880013917 A KR1019880013917 A KR 1019880013917A KR 880013917 A KR880013917 A KR 880013917A KR 890007400 A KR890007400 A KR 890007400A
Authority
KR
South Korea
Prior art keywords
substrate
trench etching
etching
mask pattern
trench
Prior art date
Application number
KR1019880013917A
Other languages
English (en)
Other versions
KR910009611B1 (ko
Inventor
다구시 모또야마
나오미찌 아베
사도루 미하라
Original Assignee
야마모두 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마모두 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모두 다꾸마
Publication of KR890007400A publication Critical patent/KR890007400A/ko
Application granted granted Critical
Publication of KR910009611B1 publication Critical patent/KR910009611B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

트렌치 에칭법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a-2d도는 본 발명의 방법의 실시예의 횡단면도.
제3도는 실리콘 기판의 영역 A 및 B의 에칭 시간과 트렌치 깊이간의 관계를 나타낸 그래프.

Claims (4)

  1. 기판을 준비하는 단계와, 기판상에 상기 기판의 재료와 다른 재료를 갖는 트렌치 에칭을 위한 마스크 패턴을 형성시키는 단계와, 트렌치 에칭이 완료됨을 판단하기 위하여 마스크 패턴 및 실리콘 기판의 에칭비율을 사용하여 상기 마스크 패턴과 상기 기판을 에칭함으로써 발생되는 스펙트럼 분석의 결과의 변화를 검출하는 단계로 구성되는 트렌치 에칭법.
  2. 제1항에 있어서, 상기 기판이 실리콘 기판인 트렌치 에칭법.
  3. 제1항에 있어서, 상기 마스크 패턴이 포스포-실리케이트 유리 또는 실리콘의 열산화물인 트렌치 에칭법.
  4. 제1항에 있어서, 상기 트렌치 에칭이 반응이온 에칭에 의해서 행해지는 트렌치 에칭법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880013917A 1987-10-29 1988-10-25 트렌치 에칭법 KR910009611B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62274779A JPH01117034A (ja) 1987-10-29 1987-10-29 トレンチエッチング方法
JP?62-274779 1987-10-29
JP62-274779 1987-10-29

Publications (2)

Publication Number Publication Date
KR890007400A true KR890007400A (ko) 1989-06-19
KR910009611B1 KR910009611B1 (ko) 1991-11-23

Family

ID=17546444

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880013917A KR910009611B1 (ko) 1987-10-29 1988-10-25 트렌치 에칭법

Country Status (5)

Country Link
US (1) US5030316A (ko)
EP (1) EP0314522B1 (ko)
JP (1) JPH01117034A (ko)
KR (1) KR910009611B1 (ko)
DE (1) DE3889709T2 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4029912A1 (de) * 1990-09-21 1992-03-26 Philips Patentverwaltung Verfahren zur bildung mindestens eines grabens in einer substratschicht
FR2669466B1 (fr) * 1990-11-16 1997-11-07 Michel Haond Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant.
EP0511448A1 (en) * 1991-04-30 1992-11-04 International Business Machines Corporation Method and apparatus for in-situ and on-line monitoring of a trench formation process
US5281305A (en) * 1992-05-22 1994-01-25 Northrop Corporation Method for the production of optical waveguides employing trench and fill techniques
US5465859A (en) * 1994-04-28 1995-11-14 International Business Machines Corporation Dual phase and hybrid phase shifting mask fabrication using a surface etch monitoring technique
US5998301A (en) * 1997-12-18 1999-12-07 Advanced Micro Devices, Inc. Method and system for providing tapered shallow trench isolation structure profile
TW398053B (en) * 1998-07-31 2000-07-11 United Microelectronics Corp Manufacturing of shallow trench isolation
DE10004394A1 (de) * 2000-02-02 2001-08-16 Infineon Technologies Ag Verfahren zur Grabenätzung in Halbleitermaterial
US20200135898A1 (en) * 2018-10-30 2020-04-30 International Business Machines Corporation Hard mask replenishment for etching processes
CN110316971B (zh) * 2019-07-03 2021-09-24 Tcl华星光电技术有限公司 蚀刻混切玻璃基板的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496425A (en) * 1984-01-30 1985-01-29 At&T Technologies, Inc. Technique for determining the end point of an etching process
JPS60251626A (ja) * 1984-05-28 1985-12-12 Mitsubishi Electric Corp エツチングの終点検出方法
JPS61115326A (ja) * 1984-11-12 1986-06-02 Oki Electric Ind Co Ltd 半導体基板のエツチング方法
JPS61232620A (ja) * 1985-04-09 1986-10-16 Matsushita Electronics Corp 半導体基板エツチング方法
JPS61232619A (ja) * 1985-04-09 1986-10-16 Matsushita Electronics Corp 半導体基板エツチング方法

Also Published As

Publication number Publication date
EP0314522B1 (en) 1994-05-25
US5030316A (en) 1991-07-09
JPH01117034A (ja) 1989-05-09
EP0314522A3 (en) 1990-04-18
KR910009611B1 (ko) 1991-11-23
DE3889709T2 (de) 1994-09-08
DE3889709D1 (de) 1994-06-30
EP0314522A2 (en) 1989-05-03

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