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KR890007298A - Nonvolatile memory - Google Patents

Nonvolatile memory Download PDF

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Publication number
KR890007298A
KR890007298A KR1019880014096A KR880014096A KR890007298A KR 890007298 A KR890007298 A KR 890007298A KR 1019880014096 A KR1019880014096 A KR 1019880014096A KR 880014096 A KR880014096 A KR 880014096A KR 890007298 A KR890007298 A KR 890007298A
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South Korea
Prior art keywords
transistor
test mode
blm
turned
common connection
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KR1019880014096A
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Korean (ko)
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KR910007438B1 (en
Inventor
노브아키 오츠카
준이치 미야모토
시게루 아츠미
Original Assignee
원본미기재
가부시키가이샤 도시바
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Publication of KR910007438B1 publication Critical patent/KR910007438B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

불휘발성 기억장치Nonvolatile memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 신회성시험모우드(stress test mode)가 이루어질때 제1도의 반도체기억장치에 포함되는 비트선의 회로구성을 도시해 놓은 회로도,2 is a circuit diagram showing a circuit configuration of a bit line included in the semiconductor memory device of FIG. 1 when a stress test mode is performed;

제3도는 스트레스시험모우드가 이루어질때 제1도의 반도체기억장치에 포함되는 비트선 및 불량선의 회로구성을 도시해 놓은 회로도,3 is a circuit diagram showing the circuit configuration of the bit line and the bad line included in the semiconductor memory device of FIG. 1 when the stress test mode is made;

제4도는 본 발명의 1실시예에 관한 반도체기억장치를 도시해 놓은 회로도.4 is a circuit diagram showing a semiconductor memory device according to one embodiment of the present invention.

Claims (9)

일단과 타단을 각각 갖는 복수의 비트선(BL1∼BLm)과, 복수의 워드선(WL1∼WL), 매트릭스 형상으로 배열되고 상기 비트선(BL1∼BLm)과 워드선(WL∼WLn)중 해당된 한선에 각각 접속되는 불휘발성 반도체 메모리셀(M11∼Mmn)상기 비트선(BL1∼BLm)과 워드선(WL1∼WLn)을 선택하는 수단(5-1)(5-2)(6)및, 프로그래밍모우드시 턴온되고 데이터프로그래밍모우드시 반도체기억장치에 설정되도록 상기 비트선(BL1∼BLm)의 일단에 접속되는 제1 트랜지스터(7)로 이루어지도록 된 불휘발성기억장치에 있어서, 상기 제 1트랜지스터(7)가 턴오프될 때 한트랜지스턴스가 턴온되고 상기 제 1트랜지스터(7)의 상호 콘덕턴스보다 더 작은 상호콘덕턴스를 각각 갖으므로 시험모우드로 설정되도록 상기 비트선(BL1∼BLm)의 타단에 접속되는 복수의 제 2트랜지스터(10)와, 상기 제 2트래지스터(10)를 거쳐 상기 비트선(BL1∼BLm)에 접속되는 공통 접속선(17) 및, 시험모우드시 상기 비트선(BL1∼BLm)으로 스트레스전압을 공급하도록 상기 공통접속선(17)에 접속되는 접속수단(11)으로 구성된 것을 특징으로 하는 불휘발성 기억장치.A plurality of bit lines BL1 to BLm, one of the plurality of word lines WL1 to WL, and a matrix, each having one end and the other end, and corresponding to one of the bit lines BL1 to BLm and word lines WL to WLn. Means for selecting the bit lines BL1 to BLm and the word lines WL1 to WLn respectively connected to the non-volatile semiconductor memory cells M11 to Mmn respectively connected to the adjacent one line; And a first transistor (7) connected to one end of the bit lines (BL1 to BLm) so as to be turned on during programming mode and set in a semiconductor memory device during data programming mode. When (7) is turned off, since one transistor is turned on and each has a mutual conductance smaller than the mutual conductance of the first transistor 7, the other ends of the bit lines BL1 to BLm are set to the test mode. A plurality of second transistors 10 and the second transistors 10 connected to The common connection line 17 connected to the bit lines BL1 to BLm, and the connection means connected to the common connection line 17 to supply a stress voltage to the bit lines BL1 to BLm during a test mode ( 11) nonvolatile memory, characterized in that consisting of. 제1항에 있어서, 프로그래밍전압이 프로그래밍 모우드시 상기 제 1트랜지스터(7)를 거쳐 상기 비트선(BL1∼BLm)에 인가되도록 된 것을 특징으로하는 불휘발성 기억장치.A nonvolatile memory device according to claim 1, wherein a programming voltage is applied to said bit lines (BL1 to BLm) via said first transistor (7) during a programming mode. 제1항에 있어서, 상기 공통접속선(17)에 스트레스전압을 인가하기 위한 상기 접속수단(11)이 시험모우드시 인가되는 고전압을 스트레스전압으로 변환시키는 전환수단(12)(13)으로 이루어져 상기 공통접속선(17)에 스트레스전압을 인가할 수 있도록 된 것을 특징으로 하는 불휘발성 기억장치.The method according to claim 1, wherein the connecting means (11) for applying a stress voltage to the common connection line (17) comprises switching means (12) (13) for converting a high voltage applied during a test mode into a stress voltage. A nonvolatile memory device characterized in that a stress voltage can be applied to a common connection line (17). 제1항에 있어서, 상기 전압전화수단(11)이 고전압을 공급받도록 접속되면서 시험모우드시 턴온되는 제3트랜지스터(12)와, 직렬로 상기 제 3트랜지스터(12)에 접속되면서 시험모우드시 턴온되는 제 4트랜지스터(14), 상기 메모리 메모리셀(M11∼Mmn)과 같이 실질적으로 동일구성으로 형성되고 상기 제 4트랜지스터(14)와 접지사이에 접속되며 시험모우드시 프로그래밍모우드로 설정되는 모의 메모리셀(15)로 구성되고, 상기 공통접속점(17)이 상기 제3 및 제 4트랜지스터(12)(14)사이에 접속점(C)에 접속되며, 스트레스전압이 시험모우드시 상기 공통 접속선(17)에 인가되도록 된 것을 특징으로 하는 불휘발성 기억장치.The third transistor 12, which is turned on in the test mode while being connected to receive the high voltage, is connected to the third transistor 12 in series and turned on in the test mode. A simulated memory cell formed of substantially the same configuration as the fourth transistor 14 and the memory memory cells M11 to Mmn, connected between the fourth transistor 14 and ground, and configured as a programming mode during a test mode. 15), the common connection point 17 is connected to the connection point C between the third and fourth transistors 12 and 14, and a stress voltage is applied to the common connection line 17 in the test mode. Non-volatile memory, characterized in that to be applied. 제1항에 있어서, 상기 제 2트랜지스터(10)가 시험모우드시 시험신호에 응답해서 턴온되는 것을 특징으로하는 불휘발성 기억장치.The nonvolatile memory device according to claim 1, wherein said second transistor (10) is turned on in response to a test signal during a test mode. 제5항에 있어서, 고전압레벨의 고전압시험신호로 시험신호를 전환시키는 전환수단(16)이 추가로 구성되고, 상기 전압전환수단(11)이 고전압시험신호에 응답해서 할성화되는 것을 특징으로 하는 불휘발성 기억장치.6. A switching device (16) according to claim 5, characterized in that a switching means (16) for converting the test signal into a high voltage test signal of a high voltage level is further configured, and said voltage switching means (11) is active in response to the high voltage test signal. Nonvolatile Memory. 제6항에 있어서, 상기 전압전환수단(11)이 고전압을 공급하받도록 접속되면서 시험모우드시 턴온되는 제 3트랜지스터(12)와, 직렬로 상기 제 3트랜지스터(12)에 접속되면서 시험모우드시 턴온되는 제 4트랜지스터(14), 상기 메모리셀(M11∼Mmn)과 같이 실질적으로 동일구성으로 형성되고 상기 제 4트랜지스터(14)와 접지사이에 접속되며 시험모우드시 프로그래밍모우드로 설정되는 모의 메모리셀(15)로 구성되고, 상기 공통접속점(17)이 상기 제3 및 제 4트랜지스터(12)(14)사이의 접속점(C)에 접속되며, 스트레스전압이 시험모우드시 상기 공통 접속선(17)에 인가되도록 된 것을 특징으로 하는 불휘발성 기억장치.The method of claim 6, wherein the voltage switching means 11 is connected to supply a high voltage, the third transistor 12 which is turned on in the test mode, and connected in series with the third transistor 12 in turn on the test mode A simulated memory cell formed of substantially the same configuration as the fourth transistor 14 and the memory cells M11 to Mmn connected between the fourth transistor 14 and the ground and configured as a programming mode during a test mode. 15), the common connection point 17 is connected to the connection point C between the third and fourth transistors 12 and 14, and a stress voltage is applied to the common connection line 17 in the test mode. Non-volatile memory, characterized in that to be applied. 제1항에 있어서, 상기 제 2트랜지스터(10)가 리셋트신호에 응답해서 턴온되고, 상기 비트선(BL1∼BLm)이 상기 제 2트랜지스터(10)와 상기 공통접속선(17)순으로 거쳐 접지됨으로 리셋트되는 것을 특징으로 하는 불휘발성 기억장치.The second transistor 10 of claim 1, wherein the second transistor 10 is turned on in response to a reset signal, and the bit lines BL1 to BLm pass through the second transistor 10 and the common connection line 17 in order. Non-volatile memory, characterized in that reset to grounded. 제8항에 있어서, 상기 공통접속선(17)과 접지사이에 접속되면서 리셋트신호에 응답해서 턴온되는 스위칭수단(22)을 추가로 이루는 것을 특징으로 하는 불휘발성 기억장치.9. The nonvolatile memory device according to claim 8, further comprising switching means (22) connected between the common connection line (17) and ground and turned on in response to a reset signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880014096A 1987-10-28 1988-10-28 Nonvolatile Memory KR910007438B1 (en)

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Application Number Priority Date Filing Date Title
JP62-272119 1987-10-28
JP87-272119 1987-10-28
JP62272119A JPH01113999A (en) 1987-10-28 1987-10-28 Stress test circuit for non-volatile memory

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KR890007298A true KR890007298A (en) 1989-06-19
KR910007438B1 KR910007438B1 (en) 1991-09-26

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US (1) US4999813A (en)
EP (1) EP0314180B1 (en)
JP (1) JPH01113999A (en)
KR (1) KR910007438B1 (en)
DE (1) DE3882898T2 (en)

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DE3882898T2 (en) 1993-11-18
EP0314180A3 (en) 1990-12-19
EP0314180B1 (en) 1993-08-04
EP0314180A2 (en) 1989-05-03
KR910007438B1 (en) 1991-09-26
DE3882898D1 (en) 1993-09-09
US4999813A (en) 1991-03-12
JPH01113999A (en) 1989-05-02

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