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KR880010493A - 디램 쎌의 제조방법 - Google Patents

디램 쎌의 제조방법 Download PDF

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Publication number
KR880010493A
KR880010493A KR870001554A KR870001554A KR880010493A KR 880010493 A KR880010493 A KR 880010493A KR 870001554 A KR870001554 A KR 870001554A KR 870001554 A KR870001554 A KR 870001554A KR 880010493 A KR880010493 A KR 880010493A
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KR
South Korea
Prior art keywords
forming
region
transistor
storage capacitor
electrode
Prior art date
Application number
KR870001554A
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English (en)
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KR890003217B1 (ko
Inventor
강면구
곽병헌
장원희
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870001554A priority Critical patent/KR890003217B1/ko
Priority to JP63037681A priority patent/JPH0715947B2/ja
Priority to US07/159,177 priority patent/US4945066A/en
Publication of KR880010493A publication Critical patent/KR880010493A/ko
Application granted granted Critical
Publication of KR890003217B1 publication Critical patent/KR890003217B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

디램 쎌의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 1트랜지스터 디램셀 어레이의 회로도.
제2도는 1트랜지스터 디램셀 어레이의 레이아웃 평면도.
제3(A)-(J)도는 본 발명에 따른 1트랜지스터 디램셀의 제조 공정도.

Claims (1)

  1. 반도체 메모리셀의 제조 공정에 있어서, 실리콘기판(100) 전면에 실리콘 산화막층(10)과 질화실리콘층(12)을 형성하고 채널스톱영역(15) 형성을 위해 붕소를 이온 주입하는 제1공정과, 상기 채널스톱영역(15) 상부에 셀과 셀의 분리를 위한 필드산화막(16)을 형성하는 제2공정과, 스토리지 캐패시터의 하부 전극과 트랜지스터의 소오스 영역을 연결시키기 위한 인이온 주입을 하는 제3공정과, 고용량 캐패시터를 형성하기 위해 필드산화막층(16)의 가장자리 부분을 희석불산 용액으로 에칭하여 스토리지 패캐시터영역(54)을 넓히고 스토리지 캐패시터영역(54) 하부에 알파입자에 의해 발생되는 소수캐리어의 모임을 막는 장벽 형성을 위해 붕소(22)를 이온 주입하는 제4공정과, 상기 에칭되어 있는 스토리지 캐패시터 부위(21)에 산화막을 성장시키고 스토리지 캐패시터의 전극형성을 위해 비소이온 주입을 하는 제5공정과, 상기 절연막(23)위에 스트리지 캐패시터의 전극형성을 위해 제1폴리실리콘(25)을 형성하는 제6공정과, 상기 제1폴리실리콘전극(25) 상부에 제2폴리실리콘과의 절연을 목적으로 하는 두꺼운 산화실리콘층을 형성하고 남아 있는 질화실리콘을 모두 제거하고 나서 산화막의 전면에 드레쉬홀드 전압의 조정을 위해 전면에 불순물을 도핑시키는 제7공정과, 상기 산화실리콘의 상부에 워드라인과 트랜지스터의 게이트전극 형성을 위한 제2폴리실리콘을 형성하고 트랜지스터의 소오스(35)와 드레이(36) 영역을 형성하는 제8공정과, 보호막층(38)을 형성하고 나서 알루미늄 비트라인(42)과 트랜지스터의 드레인(36) 접촉을 위한 윈도우(39)를 형성하고 상기 윈도우(39)를 통하여붕소이온 주입을 하여 트랜지스터의 드레인영역(36) 하부에 소수캐리어에 대한 장벽(40)을 형성하는 제9공정과, 상기 보호막층(38) 상부에 비트라인(42)을 형성하는 제10공정으로 이루어짐을 특징으로 하는 반도체장치의 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870001554A 1987-02-24 1987-02-24 디램 쎌의 제조방법 KR890003217B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019870001554A KR890003217B1 (ko) 1987-02-24 1987-02-24 디램 쎌의 제조방법
JP63037681A JPH0715947B2 (ja) 1987-02-24 1988-02-22 Ｄｒａｍセルの製造方法
US07/159,177 US4945066A (en) 1987-02-24 1988-02-23 Process for manufacturing a dynamic random access memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870001554A KR890003217B1 (ko) 1987-02-24 1987-02-24 디램 쎌의 제조방법

Publications (2)

Publication Number Publication Date
KR880010493A true KR880010493A (ko) 1988-10-10
KR890003217B1 KR890003217B1 (ko) 1989-08-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870001554A KR890003217B1 (ko) 1987-02-24 1987-02-24 디램 쎌의 제조방법

Country Status (3)

Country Link
US (1) US4945066A (ko)
JP (1) JPH0715947B2 (ko)
KR (1) KR890003217B1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156990A (en) * 1986-07-23 1992-10-20 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
US5252504A (en) * 1988-05-02 1993-10-12 Micron Technology, Inc. Reverse polysilicon CMOS fabrication
US5026657A (en) * 1990-03-12 1991-06-25 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions
US5030585A (en) * 1990-03-22 1991-07-09 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation
US5332682A (en) * 1990-08-31 1994-07-26 Micron Semiconductor, Inc. Local encroachment reduction
KR0161885B1 (ko) * 1995-12-26 1999-02-01 문정환 반도체 소자와 그의 제조방법
GB2322042B (en) 1997-02-05 2002-02-06 Ericsson Telefon Ab L M Radio architecture
US6046606A (en) * 1998-01-21 2000-04-04 International Business Machines Corporation Soft error protected dynamic circuit
US6730569B2 (en) * 2000-12-19 2004-05-04 Texas Instruments Incorporated Field effect transistor with improved isolation structures
US6806541B2 (en) * 2001-10-25 2004-10-19 Texas Instruments Incorporated Field effect transistor with improved isolation structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
JPS58154256A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 半導体装置
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
JPS62145860A (ja) * 1985-12-20 1987-06-29 Mitsubishi Electric Corp 半導体記憶装置の製造方法
US4763181A (en) * 1986-12-08 1988-08-09 Motorola, Inc. High density non-charge-sensing DRAM cell

Also Published As

Publication number Publication date
US4945066A (en) 1990-07-31
JPH0715947B2 (ja) 1995-02-22
KR890003217B1 (ko) 1989-08-26
JPS63244672A (ja) 1988-10-12

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