KR880003426A - Plastic capsule semiconductor device and manufacturing method thereof - Google Patents
Plastic capsule semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- KR880003426A KR880003426A KR1019870009326A KR870009326A KR880003426A KR 880003426 A KR880003426 A KR 880003426A KR 1019870009326 A KR1019870009326 A KR 1019870009326A KR 870009326 A KR870009326 A KR 870009326A KR 880003426 A KR880003426 A KR 880003426A
- Authority
- KR
- South Korea
- Prior art keywords
- mold
- plate
- plastic
- encapsulation
- pins
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명의 제1의 양호한 실시예에 사용된 리드 프레임의 평면도.3 is a plan view of a lead frame used in the first preferred embodiment of the present invention.
제4도는 제3도에 도시한 바와 같은 프레임에 의해 형성된 플라스틱 캡슐형 반도체 장치의 단면도.4 is a cross-sectional view of a plastic encapsulated semiconductor device formed by a frame as shown in FIG.
제5도는 제4도에 도시한 바와 같은 반도체 장치의 입체도.5 is a three-dimensional view of the semiconductor device as shown in FIG.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT6611A/86 | 1986-08-27 | ||
IT8606611A IT1215023B (en) | 1986-08-27 | 1986-08-27 | RESIN AND ELECTRONICALLY ISOLATED ENCAPSULATED DEVICE AND SEMICONDUCTOR AND PROCESS FOR LASUA MANUFACTURE |
Publications (1)
Publication Number | Publication Date |
---|---|
KR880003426A true KR880003426A (en) | 1988-05-17 |
Family
ID=11121391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019870009326A KR880003426A (en) | 1986-08-27 | 1987-08-26 | Plastic capsule semiconductor device and manufacturing method thereof |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS6362239A (en) |
KR (1) | KR880003426A (en) |
IT (1) | IT1215023B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2596995B2 (en) * | 1988-12-21 | 1997-04-02 | シャープ株式会社 | Method for manufacturing semiconductor device |
JP2752677B2 (en) * | 1989-01-11 | 1998-05-18 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH02216838A (en) * | 1989-02-17 | 1990-08-29 | Fuji Electric Co Ltd | Manufacturing method for resin-sealed semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60130129A (en) * | 1983-12-16 | 1985-07-11 | Nec Corp | Method for sealing isolation-type semiconductor element with resin |
-
1986
- 1986-08-27 IT IT8606611A patent/IT1215023B/en active
-
1987
- 1987-08-25 JP JP62209401A patent/JPS6362239A/en active Pending
- 1987-08-26 KR KR1019870009326A patent/KR880003426A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JPS6362239A (en) | 1988-03-18 |
IT8606611A0 (en) | 1986-08-27 |
IT1215023B (en) | 1990-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19870826 |
|
PG1501 | Laying open of application | ||
PC1203 | Withdrawal of no request for examination | ||
WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |