KR880002502B1 - Dual premises electronic exchange device - Google Patents

Abstract

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Description

Dual premises electronic exchange device

1 is a system diagram of a redundant premises electron exchange device of the present invention.

2 is a detailed block diagram of a common memory.

3 is a detailed block diagram of the main diagnostic circuit of FIG.

4 is a detailed block diagram of the selector.

* Explanation of symbols for main parts of the drawings

1,2: subscriber processing module 3,4: subscriber circuit

10,20: central controller 11,21: main memory

12,22: clock generator 13,23: subscriber status monitoring circuit

14,24: subscriber call circuit 15,25: time slot control memory

16,26: switching memory 17,27: common memory

18,28: main diagnostic circuit 19,29: selector

172,272: Selector 171,271: Memory

173,273: Flag 1 174,274: Flag

2,181,281: Emergency process diagnosis circuit 185,285: Fault indication device

191,291 Subscriber control signal selector 192,292 Protection circuit

193,293: Selector fault diagnosis unit 194,294: Subscriber status signal selector

The present invention relates to a digital on-premises electronic exchange device, in particular, to configure the internal electronic exchange device in redundancy so that when one exchange device cannot control his subscriber phone due to a failure of power supply, etc. The present invention relates to a redundant premises electron exchange device that can be detected and controlled by the device.

The digital single electronic switching device is configured to control only the subscriber's telephone belonging to the electronic switching device. Therefore, when a failure of the power supply or the like in the subscriber processor or the subscriber circuit occurs, all the devices belonging to the electronic switching device belong to the electronic switching device. There was a flaw that the subscriber's telephone could not be controlled and could not make calls until it was repaired.

Accordingly, an object of the present invention is to control its own subscriber circuit section when two electronic switching devices are normal, and another electronic switch when one electronic switching device cannot control its subscriber circuit section due to a failure in power supply or the like. The present invention provides a redundant premises electronic exchange apparatus capable of simultaneously controlling the subscriber circuit portion and the magnetic side subscriber circuit portion of the failed electronic exchange apparatus.

The present invention having such an object will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a dual premises electronic switching device of the present invention, as shown in FIG. 1, the central controller 10, 20, and main memories 11, 21, clock generators 12, 22, and subscribers. State monitoring circuits 13, 23, subscriber call circuits 14, 24, time slot control memories 15, 25, switching memories 16, 26, shared memory 17, (27), the main diagnostic circuits 18, 28, and the selector 19, 29 constitute the subscriber processing modules 1, 2 symmetrically with each other, and then selector of the subscriber processing module ( 19) and (20) by connecting subscriber circuits (3) and (4), respectively, wherein the central controller 10 of the subscriber processing module 1 operates as the main clock of the clock generator 12 and the whole thereof. The operation is monitored, controlled and controlled by the contents of the main memory 11 through the address bus 51 and the data bus 52, and the fault selector 19 and the counterpart selector 29 receive the fault interrupt signals of the counterpart and the counterpart. To The main memory 11 is composed of a ROM and a RAM, and has a built-in processing program for processing the entire operation. The clock generator 12 controls the central controller 10. To generate the main clock and the frame sync, the various real-time clock, the clock required for each circuit operation and output through the clock line 53, the subscriber state monitoring circuit 13 is the subscriber circuit unit (3), ( Hang on, hang off, and dialing reported through transmission lines 64, 64 'and selectors 19, 29', and time division line 54 at all subscribers of 4). The subscriber status signal of the subscriber is monitored by the subscriber status memory and outputted to the central controller 10. The subscriber calling circuit 14 divides all subscribers subscribed to the subscriber circuits 3 and 4 into a quadrant line 55. ) And command signals such as rings and dials that can be called via selectors 19, 29, transmission lines 65, 65 ' The time slot memory comprises a time slot assignment memory for allocating time slots through time division lines 56 and selectors 19 and 29 in all subscribers subscribed to subscriber circuits 3 and 4. The switching memory 16 transmits the voice signals of all subscribers subscribed to the subscriber circuits 3 and 4 to the transmission lines 64, 65, 64 ', 65' and the selectors 19, 29. And, it is connected to each other through the voice transmission line 57, 58, 59, and the common memory 17 is a line (B) between the subscriber subscriber processing module 1 and the subscriber subscriber processing module 2 of the other party (2). 60, which is a kind of passage for obtaining necessary information through the track 61 or providing the necessary information through the track 61, the detailed diagram of which is shown in FIG. Check and diagnose the various circuits of 1) and the control signal of the subscriber circuit section 3 to interrupt the central controller 10 or the counterpart central controller 20. As shown in FIG. 3, the selector 19 has its own subscriber processing module in response to the selector selection command signals of the central controller 10 and the counterpart central controller 20. FIG. The various control signals of (1) or the various control signals of the other party's subscriber processing module 2 are transmitted to the subscriber path unit 3 through the transmission line 64, and at the same time, the subscriber status signal of the own subscriber circuit unit 3 or the magnetic signal is generated. The subscriber status signal of the subscriber circuit section 4 via the side subscriber status signal and the counterpart selector 29 is transmitted to the subscriber status monitoring circuit 14 via the time division line 54. As shown.

In addition, each part of the subscriber processing module 2 is also configured in the same way as that of the above-mentioned subscriber processing module 1, and the processing modules 1, 2 of each of the subscriber processing modules 1, 2 are processed. Power supply for supplying power to each part of the) is not shown. In the description of the drawings, reference numerals 30 and 40 of the subscriber circuits 3 and 4 denote shift buffers, 31 and 41 denote local diagnostics, and 32 and 42 denote respective subscriber circuits.

2 is a detailed block diagram of the common memory 17 and 27, which stores data transmitted to the data buses 52 and 52 ', respectively, and outputs the stored data, respectively. Selectors 172 and 272 which select one of the address signals transmitted to the memories 171 and 271 and the address buses 51 and 51 'and pass them to the memories 171 and 271; In addition, the selectors 172 and 272 control each other so as to select their own or relative address signals, and at the same time, the memory 171 and 271 may be in a write or read state. Flags 1 (173) and (273) for controlling the other side, and flags 2 (174) and (274) for applying an interrupt signal to each other to receive information data from the central controller (20) and (10). The operation process thereof is as follows.

로 트라이스테이트버퍼(TS₁₃)를 도통상태로 만들어버퍼(B₂₃),(B₁₄)를 통한 상대편 플래그 1(273)의 출력신호를 데이타버스(52)의 0비트 버스선(DB₁₀)으로 출력시키고, 이 0비트 버스선(DB₁₀)으로 출력된 플래그 1(273)의 출력신호를 중앙처리기(10)에서 읽어, 그 출력신호가 저전위 상태이면 정보데이타를 메모리(171)으 지정 어드레스에 기억시키게 되고, 그 출력신호가 고전위 상태이면 저전위 상태로 될때까지 기다린 후 상기 동작을 수행하게 되며, 이때 일정시간이 지나도 상기 플래그 1(273)의 출력신호가 저전위 상태로 되지 않으면 에러(error)로 보고하게 된다.In the case of transmitting information data from the subscriber processing module 1 to the subscriber processing module 2, first, the control signal from the central controller 10 of the subscriber processing module 1 is transmitted.

The low tri-state buffer TS ₁₃ is brought into a conductive state and the output signal of the opposite flag 1 (273) through the buffers B ₂₃ and B ₁₄ is transferred to the 0-bit bus line DB ₁₀ of the data bus 52. Outputs the output signal of flag 1 (273) output to the 0-bit bus line DB ₁₀ from the central processing unit 10, and if the output signal is in the low potential state, designates the information data in the memory 171 If the output signal is in the high potential state, wait until it reaches the low potential state and perform the above operation. In this case, if the output signal of the flag 1 (273) does not become the low potential state after a predetermined time, an error occurs. (error) will be reported.

That is, when the output signal of the flag 1 (273) through the buffer (B ₂₃ ), (B ₁₄ ) as described above is in the low potential state, the low potential signal is applied to the select terminal SL of the selector 172, so that the selector The input terminal A of 172 is connected to the output terminal Y thereof, whereby the address signal output from the central controller 10 to the address bus 51 is input terminal A and output of the selector 172. The terminal Y is applied to the address input terminal AB of the memory 171 to designate its address, and at this time, the low potential signal through the buffer B ₁₄ is inverted into a high potential signal and then the NAND gate ( N ₁₁ ) is applied to one input terminal of the input terminal, and the low potential signal applied to the read / write control signal terminal RD ₁ / WR ₁ is applied to the other input terminal thereof inverted to a high potential signal. The potential signal is output, and this low potential signal is input to the function control signal of the memory 171. It is applied to the party (E) make him a light state. Therefore, the information data output from the central controller 10 to the data bus 52 is recorded in the address of the memory 171 designated as described above.

In this manner, after the central controller 10 records the information data in the memory 171, the high potential signal, which is the flag 2WR signal, is recorded and output in the flag 2 174, and the high potential signal output from the flag 2 174 is output. Is applied to the 2-bit bus line DB ₁₂ of the data bus 52 through the tri-state buffer TS ₁₁ , so that the central control 10 recognizes that the high-potential signal is output from the flag 2 174. After finishing the operation, the next operation is performed.

In addition, since the high potential signal output from the flag 2 (174) is applied as an interrupt signal to the counterpart central controller 20 through the buffers B ₁₁ and B ₂₂ , the central controller 20 is shared with the counterpart. Information data stored in the memory 171 of the memory is read. That is, the central controller 20 records and outputs a high potential signal, which is a flag 1 WR signal, to a flag 1 (273), and the high potential signal output from the flag 1 (273) is buffered (B ₂₃ ), (B ₁₄ ). Is applied to the select terminal SL of the selector 172, and the input terminal B of the selector 172 is connected to its output terminal Y, and the high potential signal is inverted to a low potential signal. Since it is applied to one input terminal of the NAND gate N ₁₁ , a high potential signal is output to its output terminal regardless of the signal applied to the other input terminal thereof, thereby making the memory 171 read.

로 트라이 스테이트 버퍼(TS₂₅),를 도통시킴으로써 데이타버스(52')를 통해 읽게 된다. 이 후 중앙 제어기(20)는 플래그 1(273)에 저전위 신호를 기록시켜 다음 데이타 정보신호를 기록하게 된다.Therefore, the address signal output from the central controller 20 to the address bus 51 'is stored in the memory via the input terminals B and output terminals Y of the buffers B ₂₅ , B ₁₆ and the selector 172. Since an address of 171 is designated, a data information signal written to the address is outputted to its data output terminal DO, so that the control signal is transmitted from the central controller 20 at this time.

The low tri state buffer TS ₂₅ is turned on to read through the data bus 52 '. Thereafter, the central controller 20 records the low potential signal in the flag 1 273 to record the next data information signal.

In this way, it is possible to transmit the data information signal from the central controller 10 of the subscriber processing module 1 to the central controller 20 of the subscriber processing module 2 through the common memories 17 and 27, In addition, the central controller 20 of the subscriber processing module 2 transmits the data information signal to the central controller 10 of the subscriber processing module 1 in the same manner as described above.

3 is a detailed block diagram of a fraudulent main diagnosis circuit 18. As shown in FIG. 3, an abnormal failure interrupt signal is detected at the counterpart central controller 20 by detecting an abnormality of a main clock and a power supply controlling the central controller 10. As shown in FIG. After detecting various fault signals such as an emergency processing diagnostic circuit 181, a frame sink, various real time clocks, and a selector 19, the fault is caused to the central controller 10 through the tri-state buffer TS ₁₅ . Various main diagnostic circuits 182 to be applied as an interrupt signal, an interrupt blocking circuit 183 for blocking a fault interrupt signal by blocking the magnetic state buffer TS ₁₅ to a blocked state, and after the fault interrupt signal is blocked, It consists of a diagnostic circuit check circuit 184 for checking whether or not the various main diagnostic circuits 182 are faulty, and a fault display device 185 for displaying the fault state with a light emitting element. The main diagnostic circuit 28 of FIG. 2 is configured in the same manner as the main diagnostic circuit 18 of the subscriber subscriber module 1, and the description of the main diagnostic circuit 28 is described in the following description. The description given in the same manner as the reference numerals given to the respective parts of 18) will be given.

When the main diagnosis circuit 18 configured as described above has an abnormality in the main clock and power supply for controlling the central controller 10, the emergency diagnosis circuit 181 detects it and then emergency breakdown to the counterpart central controller 20. It is applied as an interrupt signal to take over control of the own subscriber circuit section 3 so that the other subscriber processing module 2 performs the control.

In addition, when a failure occurs in the frame sync, various real-time clocks, and the selector 19, the failure signal is detected by the various main diagnosis circuits 182, and then the main controller 10 through the tri-state buffer TS ₁₅ is used. When the fault interrupt signal is applied to the central controller 10, the interrupt blocky circuit 183 is interrupted through the address bus 51 and the data bus 52 to cover all of the fault signals. Drive the circuit board to block the fault interrupt signal by blocking the tri-state buffer TS ₁₅ with its output signal, and then check whether the various main diagnosis circuits 182 are broken by the diagnostic circuit check circuit 184. If the central controller 10 determines that a failure is made by the central controller 10 through the address bus 51 and the data bus 52, the failure is determined. Status is displayed on the fault display device 187 to request repair.

However, in this case, when the subscriber circuit module 3 cannot control the subscriber circuit unit 3 as described above, the central controller of the subscriber subscriber module 2 via the common memories 17 and 27 as described above. A data information signal is applied to 20 to perform the control of the subscriber circuit section 3 on the counterpart subscriber processing module 2. In addition, the main diagnosis circuit 28 of the subscriber processing module 2 also operates in the same manner as the main diagnosis circuit 18 of the subscriber processing module 1 described above.

4 is a detailed block diagram of the selector 19 of the subscriber processing module 1, and as shown therein, the subscriber subscriber control signal or the subscriber subscriber control signal and the subscriber subscriber control signal of the other party's central controller 20 are shown. Subscriber control signal selector 191 selects and outputs the selector selection command signal and stabilizes the output signal of the subscriber control signal selector 191 to control subscribers with transmission line 65 connected to the subscriber circuit section 3 of the subscriber side. The fault of the selector is diagnosed from the output signal of the protection circuit 192 which transmits a signal, and the subscriber control signal selector 191 and the protection circuit 192, and a fault diagnosis result signal is applied to the main diagnosis circuit 18 of its own side. Selector fault diagnosis unit 193, its own subscriber status signal or its own subscriber status signal and its counterpart subscriber status signal by means of the selector selection command signal of its own central controller 10; And a subscriber status signal selector 19 which outputs the subscriber status signal to its own subscriber status monitoring circuit 14 via the time division line 54. The subscriber control signal selector 191 has its select terminal SL. When the low potential signal, which is the selector selection command signal of the counterpart central controller 20, is applied, its input terminal A is connected to its output terminal Y to output its own subscriber control signal and the high potential signal is When it is applied, its input terminal (B) is connected to its output terminal (Y) to output the own subscriber control signal and the other subscriber control signal through the OR gate OR ₁₁ , and the subscriber relative signal selector 194. ) it is also a magnetic-side subscriber through the subscriber control signal selector 191 and the magnetic side or subscriber status signal Iowa gate (oR ₁₁₎ according to the command signal selector selecting the magnetic-side central controller 10 in the same manner A signal and the other party subscriber status signal is to be selected is outputted.

In addition, the selector 29 of the subscriber processing module 2 is also configured in the same manner as the selector 19 of the subscriber processing module 1, and the description of the selector 29 will be described below. The description will be made in the same manner as the reference numerals given to the respective parts of 19).

In addition, the selector selection command signal applied to the subscriber state signal selector 194 of the own side selector 19 and the subscriber control signal selector 291 of the opposing side selector 29 is normally controlled by the central controller 10 of the subscriber processing module. When the fixed interrupt signal is applied in the same manner as described above in the subscriber processing module 2, the high potential signal is outputted as a low potential signal. The selector selection command signal applied to the subscriber status signal selector 294 of the side selector 29 and the subscriber control signal selector 191 of the counterpart selector 19 is normally output as a low potential signal before the counterpart subscriber processing module 1 When the fault interrupt signal as described above is applied, the high potential signal is output.

According to the present invention configured as described above, when the subscriber processing modules 1 and 2 are all normal, the selector selection command signals output from the central controllers 10 and 20 as described above are all at low potential, and thus the selector 19 Subscriber control signal selectors 191, 291, and subscriber status signal selectors 194, 294 of (2) and (29) select and output their own subscriber control signals and their own subscriber status signals, respectively.

That is, the time division lines 55, 56 and voice are controlled by the subscriber calling circuit 14, the time slot control memory 15, and the switching memory 16 under the control of the central controller 10 of the subscriber processing module 1. Only signals output to the transmission / reception line 58 are output to the output terminal Y through the input terminal A of the subscriber control signal selector 191, and thus output from the subscriber control signal selector 191. The subscriber control signal is applied to the subscriber circuit unit 3 through the protection circuit 192 and the transmission line 65 to control each subscriber circuit 32.

In addition, at this time, only the subscriber station state signal output from the subscriber circuit unit 3 to the transmission line 64 is output to the output terminal Y through the input terminal A of the subscriber state signal selector 194, and then the time division line. Since it is applied to the subscriber state monitoring circuit 13 through 54, the central controller 10 performs the control accordingly. The voice signal transmitted from the subscriber circuit section 3 to the transmission line 64 is output to the voice transmission / reception line 58 through the selector 19 and the voice transmission / reception line 57 switching memory 16.

Similarly, only signals output from the subscriber calling circuit 24, the timeslot control memory 25, and the switching memory 26 of the subscriber processing module 2 are used to selector subscriber control signal selector 291 and protection circuit 292. The subscriber side subscriber circuit section 4 is controlled via the subscriber side signal circuit 4, and only the subscriber status signal of the subscriber circuit number 4 is applied to the subscriber status monitoring circuit 23 through the subscription status signal selector 294 of the selector 29. .

When the subscriber processing module 1, 2 is normal as described above, the subscriber processing module 1, 2 independently monitors and controls only its own subscriber circuits 3, 4, respectively. However, if one of the subscriber processing modules (1), (2) cannot control the own side subscriber circuit section (3) (4) due to a failure, the subscriber processing module (1), (2) is in a normal state. The subscriber processing module is in control of both the subscriber circuit section (3), (4).

For example, the subscriber processing module 2 generates an emergency failure interrupt signal from the emergency processing diagnosis circuit 181 of the main diagnosis circuit 28 due to an abnormality of the main clock and the power supply. After identifying the failure interrupt signal applied to the central controller 10 or generated in the various main diagnosis circuits 282 as described above, the central controller 20 and the common memory 27, 17 in the same manner as described above. When requesting the central controller 10 to control the own subscriber circuit unit 4 through the subscriber station, the subscriber processing module 2 becomes unable to control the own subscriber circuit unit 4 and at the same time the subscriber processor module 1 ) Is in a state capable of controlling the own subscriber circuit 3 and the other subscriber circuit section 4. In addition, at this time, the selector selection command signal is output from the central processing unit 10 of the subscriber processing module 1 as a high potential signal so that the select terminal SL and the counterpart selector of the subscriber state signal selector 194 of the own side selector 19 are output. The input terminal B of the subscriber control signal selector 194 of (29) is connected to its output terminal Y and is in a conducting state, and the input terminal B of the subscriber control signal selector 291 is also output terminal ( Y) is connected to the state of conduction.

Accordingly, under the control of the central controller 10, the subscriber call circuit 14, the time slot control memory 15, and the switching memory 16 are divided into the time division lines 55, 56 and the voice transmission / reception line 58, respectively. The output signal is applied to the magnetic subscriber circuit unit 3 via the magnetic subscriber control signal selector 191, the protection circuit 192, and the transmission line 65 as described above, and the time division lines 55, 56 ) and a signal output to the audio transmit and receive line 58 is applied to the other end Iowa gate (OR ₂₁₎ and a subscriber control signal selector 291, a protection circuit 292, the other party subscriber circuit (4) through the transmission line (65 ') Therefore, the subscriber module 1 can control both the own subscriber circuit 3 and the other subscriber circuit unit 4, and at this time, the voice signal transmitted from the subscriber circuit unit 3 to the transmission line 64 is selected by the selector 19. And the voice transmission / reception line 57 and the switching memory 16 to the voice transmission / reception line 58 and the subscriber circuit section 4. ) Is output to the voice transmission / reception line 58 through the selector 29, the voice transmission / reception line 59, and the switching memory 16.

At this time, the subscriber status signal outputted from the counterpart subscriber circuit section 4 to the transmission line 64 'is output to the time division line 54' through the temporary subscriber state signal selector 294, and to this time division line 54 '. The counterpart subscriber status signal outputted and the subscriber status signal outputted from the self subscriber circuit unit 3 to the transmission line 64 are output to the time division line 54 through the OR gate ₁₂ and the subscriber status signal selector 194. Since it is applied to the subscriber status monitoring circuit 54, the subscriber processing module 1 can monitor the states of the own subscriber circuit section 3 and the counterpart subscriber circuit 4, and perform control accordingly.

Similarly, if a failure occurs that the subscriber processing module 1 cannot control its own subscriber circuit section 3, the subscriber processing module 2 replaces the subscriber circuit sections 3 and 4 in the same manner as described above. All is in control. However, when the subscriber processing module (1) or subscriber processing module (2) controls both the subscriber circuit unit (3), (4), subscriber processing module (1), (2) is independently of their own subscriber circuit unit (3) When controlling only, (4), the traffic is halved.

As described above, in the present invention, when both of the subscriber processing modules are normal, each of the subscriber processing circuits independently controls its own subscriber circuit unit. If it is not possible to control the subscriber circuit part of both sides in the normal subscriber processing module, there is an advantage that can always make a call except the abnormality of the subscriber circuit part.

Claims (4)

Central controller 10, 20 and main diagnostic circuits 11, 21, clock generators 12, 22, subscriber status monitoring circuits 13, 23, subscriber call circuits 14, 124, a time slot control memory 15, 25, a switching memory 16, and 26, respectively, in the premises electronic switching apparatus which controls only its own subscriber circuit section 3, 4, Checking and diagnosing the control signals of the common memory (17) (18) and the magnetic side mounting circuit and the subscriber circuit (3) and (4), which are capable of giving or receiving the necessary information between the central controller (10), (20). Main diagnostic circuits (18) and (28) and the central controller (10), which are configured to apply a fault interrupt signal to the magnetic central controller 10, 20 or the counterpart central controller 20, 10. In accordance with the selector selection command signal of (20), the subscriber control signal outputted from the own side or the subscriber control signal outputted from the other side is passed through the subscriber circuit section (3), (4) and at the same time, the own subscriber status signal. Or a selector (19) or (29) configured to pass the subscriber side status signal and the counterpart subscriber relative signal to the subscriber status monitoring circuits (13) and (23). 2. The data transfer apparatus according to claim 1, wherein the data transferred from the central controllers 10 and 20 to the data buses 52 and 52 'are stored, respectively, and the stored data is stored in the counterpart data buses 52' and 52. Selector 172 which selects one of the memory signals 171 and 271 outputted to the memory 171 and the address signals transmitted to the address buses 51 and 51 'and passes them to the memory 171 and 271, respectively. 272 and the flag 1 (173) for controlling the other side so that the memory 171, 271 is in the write or read state at the same time as the selector 172, 272 selects the magnetic side or the relative side address signal. ), (273) and the common memory (17), (27) with flags 2 (174), (274) for applying an interrupt signal to the central controller (20), (10) of the other side to receive information data. Redundant premises electronic exchange device, characterized in that the configuration. 2. The emergency processing diagnostic circuits 181 and 281 according to claim 1, which detect an abnormality of a main clock, a power supply, and the like and apply an emergency failure interrupt signal to the counterpart central controllers 20 and 10. After detecting a fault of the circuit, various main diagnostic circuits 182 and 282 for applying a fault interrupt signal to the central memory 10 and 20 of the magnetic side, and a fault interrupt after the fault interrupt signal is output. Interrupt blocking circuits 183 and 284 for blocking a signal, various main diagnostic circuits 184 and 284 after the fault interrupt signal is blocked, and a fault display device for displaying the fault state ( 185) and 285, wherein the dual diagnostic electron exchange device comprises a main diagnostic circuit (18) and (28). The subscriber control signal selector according to claim 1, wherein various subscriber control signals outputted from the own side or various subscriber control signals outputted from the opposing side are selected and passed by the selector selection command signals of the counterpart central controllers 20 and 10. Stabilization circuits 192 and 292 for stabilizing the output signals of the selectors 191 and 291 and outputting them to the magnetic subscriber circuits 3 and 4; A selector for diagnosing a failure of the selector from the output signals of the selectors 191, 291 and the protection circuits 192, 292 and applying the resultant signal to the main side diagnosis circuits 18, 28 of the magnetic side. The fault diagnosis unit 193 and 293, the own subscriber status signal or the own subscriber status signal and the counterpart subscriber status signal are selected in accordance with the selector selection command signals of the own central controllers 10 and 20, and the own side is selected. Subscriber status signal selector 194 which passes to subscriber status monitoring circuits 14 and 24, And (294), selector (19) and (29).

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