KR880000905Y1 - Signal switching circuit - Google Patents
Signal switching circuit Download PDFInfo
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- KR880000905Y1 KR880000905Y1 KR2019850003092U KR850003092U KR880000905Y1 KR 880000905 Y1 KR880000905 Y1 KR 880000905Y1 KR 2019850003092 U KR2019850003092 U KR 2019850003092U KR 850003092 U KR850003092 U KR 850003092U KR 880000905 Y1 KR880000905 Y1 KR 880000905Y1
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Abstract
내용 없음.No content.
Description
본 고안의 회로도.Circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 층방전 회로 20 : 클램핑회로10: layer discharge circuit 20: clamping circuit
R1, R2, …, R9: 저항 D1, D2, D3: 다이오드R 1 , R 2 ,. , R 9 : resistor D 1 , D 2 , D 3 : diode
Q1, Q2, Q3: 트랜지스터 SW : 절환스위치Q 1 , Q 2 , Q 3 : Transistor SW: Switch
본 고안은 모니터에 인가되는 아날로그 신호 및 디지탈 신호의 영상신호(R, G, B)를 모드선택스위치로 절환시킬 수 있게한 시그널 절환회로에 관한 것이다.The present invention relates to a signal switching circuit that enables the mode selection switch to switch the video signals (R, G, B) of the analog and digital signals applied to the monitor.
현재 사용되고 있는 모니터는 입력되는 시그널(Signal)의 종류에 따라 아날로그 및 디지탈 모니터로 대별할 수 있는데 이는 각기 시그널의 레벨(LEVEL)과 진폭(Amplitudt)이 서로 상이하기 때문에 각기 인가되는 시그널에 따라 전용의 모니터가 필요하게 되는 것이다.Currently used monitors can be classified into analog and digital monitors according to the type of signal (Signal) that is input. You will need a monitor.
본 고안은 이와 같은 점을 감안하여 두가지의 인터페이스(Inter-face)회로가 필요없이 서로 다른 시그널을 한 입력단자에 공급하여 각 모드로 절환시킬 수 있는 시그널 절환회로를 제공하고자 하는 것으로 입력단자에서 인가되는 상태신호로서 서로 역구동하는 영상신호 버퍼용 트랜지스터를 통하여 충방전 회로에 인가되도록 구성한후 절환스위치에 의하여 클램핑 회로 및 아날로그신호 출력단자의 출력측 영상신호 버퍼용 트랜지스터의 바이어스 전압을 제어 하도록 구성시켜 된 것이다.The present invention is to provide a signal switching circuit that can be switched to each mode by supplying different signals to one input terminal without the need for two interface circuits in this regard. It is configured to be applied to the charge / discharge circuit through the video signal buffer transistor reversely driven as a state signal, and to control the bias voltage of the output signal buffer transistor of the clamping circuit and the analog signal output terminal by a switching switch. will be.
이를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to the accompanying drawings.
입력단자(1)에 인가되는 상태신호가 저항(R2)를 통하여 영상신호 버퍼용 트랜지스터(Q1)의 베이스측과 다이오드(D1)를 통하여 저항(R3)(R4)으로 분배되어 영상신호 버퍼용 트랜지스터(Q2)의 베이스측에 인가되게 구성하여 트랜지스터(Q1)(Q2)가 서로 역구동하도록 구성시킨후 저항(R5) 및 콘덴서(C1)로 구성시킨 충방전회로(10)에 인가되게 구성하고 디지탈신호 출력단자(2)및 아날로그 신호 출력단자(3)와 절환스위치(SW)의 각 단자 사이에 다이오드 (D2)와 저항(R7)으로 구성된 클램핑 회로(20)및 영상신호 버퍼용 트랜지스터(Q3)를 제어할 수 있는 저항(R6)(R8)(R9)과 다이오드(D6)를 구성시켜 된 것이다.Is distributed to the input terminal (1) resistance (R 3) (R 4), the status signal which is applied through a resistance (R 2) through the base side and the diode (D 1) of the video signal buffer transistor (Q 1) for the Charge and discharge configured to be applied to the base side of the image signal buffer transistor Q 2 so that the transistors Q 1 and Q 2 are driven back to each other and composed of a resistor R 5 and a capacitor C 1 . A clamping circuit configured to be applied to the circuit 10 and composed of a diode (D 2 ) and a resistor (R 7 ) between the digital signal output terminal (2) and the analog signal output terminal (3) and each terminal of the changeover switch (SW). (20) and a resistor (R 6 ) (R 8 ) (R 9 ) and a diode (D 6 ) capable of controlling the image signal buffer transistor (Q 3 ).
여기서 절환스위치(SW)가 각 단자와 상 방향으로 접속시키면 디지탈 신호 출력 시이며 절환스위치(SW)가 각 단자와 하방향으로 접속될때에는 아날로그 신호 출력시이다.In this case, when the switching switch SW is connected to each terminal in the up direction, the digital signal is output. When the switching switch SW is connected to each terminal in the down direction, it is an analog signal output.
이와 같이 구성된 본 고안에서 약 1-2VPP의 진폭을 갖은 아날로그 상태신호가 입력단자(1)에 인가될때에는 절환스위치(SW)를 아래쪽 단자에 접속시킨다. (도면과 반대위치)In the present invention configured as described above, when an analog state signal having an amplitude of about 1-2 VPP is applied to the input terminal 1, the switching switch SW is connected to the lower terminal. (Opposite to the drawing)
이때 전원(VCC)은 절환스위치(SW)에서 저항(R7)및 다이오드(D2)를 통하여 디지탈 시그널 출력단자(2)에 인가되고 입력단자(1)에서 인가되는 아날로그 신호는 저항(R1)을 통하여 전원(VCC)과 합성되므로 디지탈 시그널 출력단자(2)에는 아날로그 상태신호가 나타나지 않게 된다.At this time, the power supply VCC is applied to the digital signal output terminal 2 through the resistor R 7 and the diode D 2 in the switching switch SW, and the analog signal applied from the input terminal 1 is the resistor R 1. Since it is combined with the power supply (VCC), the analog status signal does not appear in the digital signal output terminal (2).
그리고 영상신호 버퍼용 트랜지스터(Q1)의 베이스측에 인가되는 아날로그 상태신호는 트랜지스터(Q1)(Q2)를 통하여 트랜지스터(Q2)의 에미터와 병렬로 연결된 저항(R5)및 콘덴서(C1)에 인가되게 된다.The analog state signal applied to the base side of the image signal buffer transistor Q 1 is connected to the emitter R 5 and the capacitor in parallel with the emitter of the transistor Q 2 through the transistors Q 1 and Q 2 . Is applied to (C 1 ).
즉, 다이오드(D1)는 트랜지스터(Q1)(Q2)가 서로 역구동을 행할때에 오동작을 방지하며 저항(R5)및 콘덴서(C1)로 구성된 충방전 회로(10)는 트랜지스터(Q2)가 차단시 방전된 전압으로 트랜지스터(Q3)를 구동시킬 수가 있는 것으로 저항(R8)과 다이오드(D3)를 통하여 연결된 절환스위치(SW)는 접지되어 있어 충방전 회로(10)를 통하여 출력되는 저전위 상태신호가 저항(R6)과 분배되어 다이오드(D3)를 통하여 흐르게 되고 영상신호 버퍼용 트랜지스터(Q3)는 베이스측에 인가되는 저전위 상태 신호에 의하여 도통하게 된다.That is, the diode D 1 prevents malfunction when the transistors Q 1 and Q 2 reversely drive each other, and the charge / discharge circuit 10 composed of the resistor R 5 and the capacitor C 1 includes a transistor. It is possible to drive the transistor Q 3 with the discharged voltage when Q 2 is interrupted. The switching switch SW connected through the resistor R 8 and the diode D 3 is grounded so that the charge / discharge circuit 10 The low potential state signal outputted through Nk is distributed with the resistor R 6 and flows through the diode D 3 , and the image signal buffer transistor Q 3 conducts by the low potential state signal applied to the base side. do.
따라서 트랜지스터(Q3)의 에미터측에 연결된 아날로그 신호 출력단자(3)에는 트랜지스터(Q3)의 도통여부에 따라 전원(VCC)을 출력시키게 되므로 입력단자(1)로 인가되는 아날로그 상태신호와 동위상의 출력이 나타나게 되는 것이다.Thus analog connected to the emitter teocheuk of the transistor (Q 3), the signal output terminal 3 is provided with an analog status signals and par because thereby output the power (VCC) according to the conduction if the transistor (Q 3) which is applied to the input terminal (1) The output of the award will appear.
그리고 디지탈 상태신호가 인가될때에는 절환스위치(SW)를 도면과 같이 상방향으로 접속시키면 디지탈 신호 출력단자(2)에는 디지탈 상태신호가 저항(R7)과 다이오드(D2)로 구성된 클램핑 회로(20)에서 클램핑된후 입력단자(1)에 인가되는 디지탈 상태의 시그널이 그대로 출력하게 되며 영상신호 버퍼용 트랜지스터(Q1)의 베이스에 입력된 디지탈 상태신호는 아날로그 신호 출력시와 동일하게 트랜지스터(Q2)의 에미터측으로 출력하게 되나 영상신호 버퍼용 트랜지스터(Q3)의 베이스측에 연결된 다이오드(D3)와 정항(R6)에는 전원(VCC)가 절환스위치(SW)의 단자를 통하여 공급되므로 트랜지스터(Q3)는 항상 차단상태를 유지할 수 가 있게 되어 아날로그 신호 출력단자(3)에는 아무런 출력이 나타나지 않게 되는 것이다.When the digital state signal is applied, the switching switch SW is connected upward as shown in the drawing, and the digital signal output terminal 2 has a clamping circuit composed of a resistor R 7 and a diode D 2 . The signal in the digital state applied to the input terminal 1 after being clamped at 20) is output as it is, and the digital state signal input to the base of the image signal buffer transistor Q 1 is the same as that of the analog signal output. Q 2 ) is output to the emitter side, but the power supply VCC is connected to the diode D 3 and positive terminal R 6 connected to the base side of the image signal buffer transistor Q 3 through the terminal of the switching switch SW. Since it is supplied, the transistor Q 3 can be kept in a blocked state at all times, so that no output appears at the analog signal output terminal 3.
이상에서와 같이 본 고안은 절환수위치(SW)로서 아날로그 및 디지탈 출력단자로 출력되는 상태를 제어할 수 있을뿐만 아니라 디지탈 상태 신호 인가시에 일정하게 클램핑한후 디지탈 출력신호를 출력시킬 수 가 있으며 아날로그 상태신호 인가시에는 서로 상반되는 트랜지스터를 통하여 충방전회로에서 출력되는 상태신호로서 영상신호 버퍼용 트랜지스터(Q3)를 제어하여 아날로그상태신호를 출력시킬 수 가 있는 것으로 서로 다른 시그널이 한 입력단자에 인가되어도 절환스위치로서 절환시킬 수 가 있는 시그널 절환회로를 제공할 수 가 있는 것이다.As described above, the present invention not only can control the state output to the analog and digital output terminals as the switch position (SW), but also can output the digital output signal after constant clamping when the digital state signal is applied. analog status signals is when there with each other through the opposite transistor to control the video signal buffer transistor (Q 3) for a status signal output from the charge-discharge circuit that is able to output an analog status signals of different signal is one input terminal It is possible to provide a signal switching circuit that can be switched as a switching switch even if it is applied to.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850003092U KR880000905Y1 (en) | 1985-03-23 | 1985-03-23 | Signal switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850003092U KR880000905Y1 (en) | 1985-03-23 | 1985-03-23 | Signal switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR860012500U KR860012500U (en) | 1986-10-10 |
| KR880000905Y1 true KR880000905Y1 (en) | 1988-03-16 |
Family
ID=19240812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850003092U Expired KR880000905Y1 (en) | 1985-03-23 | 1985-03-23 | Signal switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR880000905Y1 (en) |
-
1985
- 1985-03-23 KR KR2019850003092U patent/KR880000905Y1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| KR860012500U (en) | 1986-10-10 |
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