KR880000408Y1 - Monitor synchronization and blanking circuit - Google Patents
Monitor synchronization and blanking circuit Download PDFInfo
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- KR880000408Y1 KR880000408Y1 KR2019840014245U KR840014245U KR880000408Y1 KR 880000408 Y1 KR880000408 Y1 KR 880000408Y1 KR 2019840014245 U KR2019840014245 U KR 2019840014245U KR 840014245 U KR840014245 U KR 840014245U KR 880000408 Y1 KR880000408 Y1 KR 880000408Y1
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- blanking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/24—Blanking circuits
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
본고안의 회로도Circuit diagram
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 비데오 앰프 20 : 동기분리 및 귀선소거부10: Video Amplifier 20: Sync Separation and Rejection Rejection
30 : 영상 처리회로 40 : 음극선관30: image processing circuit 40: cathode ray tube
Q1,Q2: 트랜지스터 R1-R8: 저항Q 1 , Q 2 : transistor R 1 -R 8 : resistance
C1-C5: 콘덴서 N1,N2: 인버터C 1 -C 5 : Condenser N 1 , N 2 : Inverter
본 고안은 모니터의 동기분리 및 귀선소 거회로에 관한 것이다.The present invention relates to a synchronous separation and blanking circuit of the monitor.
종래의 텔레비젼에 있어서 수평동기 신호 및 수직동기 신호를 분리시키는 동기분리부와 화상을 흑레벨 이하로 하여 화면을 지우는 귀선소거 신호를 인출시키는 귀선소 거부는 다수개의 트랜지스터 및 수동 소자로서 구성시켰으나 그 회로 구성이 복잡할뿐 아니라 외부에서 유기되는 전파가 농동 소자에 유기되어 트러블이 생기는 원인이 되므로 화상이 뿌연해져서 문자 신호나 화상 정보를 처리하는 모니터용으로 적합하지 못한 것이었다.In conventional televisions, a synchronization separator for separating a horizontal synchronization signal and a vertical synchronization signal and a rejection signal for drawing a blanking signal for erasing a screen with an image below a black level are configured as a plurality of transistors and passive elements. Not only is the configuration complicated, but the radio waves from the outside are induced in the farming device, causing trouble, and the images are cloudy, which makes them unsuitable for monitors that process text signals or image information.
본 고안은 이와 같은 점을 감안하여 인버터로 구성된 집적회로를 사용하여 회로의 단순화를 기하는 동시에 외부 전파에 방해를 받지 않고 안정된 동기분리 및 귀선소거 신호를 인출시킬 수 있는 회로를 제공하고자 하는 것으로 영상 처리회로의 전단과 비데와 앰프 사이에 인버터로 구성된 오픈 콜렉터용 집적소자로서 동기분리 및 귀선 소거부가 구성되게 한 것이다.In view of the above, the present invention aims to provide a circuit which can simplify the circuit using an integrated circuit composed of inverters and at the same time can draw out a stable synchronous separation and blanking signal without being disturbed by external radio waves. An open collector integrated device composed of an inverter between the front end of the processing circuit and the bidet and the amplifier is configured to have a synchronous separation and a blanking unit.
이를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to the accompanying drawings.
복합 영상신호(VS)가 인가되는 비데오 앰프(10)의 출력단자(P2)에는 콘덴서(C2)를 통하여 트랜지스터(Q2)의 베이스측과 접속되게 구성하고 트랜지스터(Q2)의 에미터측에는 저항(R5)과 방렬로 직류 차단용 콘덴서(C5)가 연결되게 구성시킨다.The output terminal P 2 of the video amplifier 10 to which the composite video signal VS is applied is configured to be connected to the base side of the transistor Q 2 through a capacitor C 2 and to emitter of the transistor Q 2 . On the side, the resistor R 5 and the direct current blocking capacitor C 5 are configured to be connected in a row.
그리고 트랜지스터(Q1)의 콜렉터측에 인덕턴스 코일(L1) 및 저항(R7)(R8)을 통하여 음극선관(40)과 연결되는 동시에 트랜지스터(Q1)의 콜렉터측과 연결되게 구성시킨후 전원(Vcc)이 콘덴서(C3) 및 저항(R6)을 통하여 베이스측에 인가되는 트랜지스터(Q1)의 여미터측과 트랜지스터(Q2)의 콜렉터측이 공접되게 통상의 영상 처리회로(30)가 구성된 것을 일반적인 모니터 회로와 동일하다.And the inductance to the collector side of the transistor (Q 1), a coil (L 1) and a resistor (R 7) (R 8) in which a cathode ray tube (40) configured to be connected simultaneously with the collector side of the transistor (Q 1) connected to and through the after power supply (Vcc) is a capacitor (C 3) and a resistor (R 6) to be a collector side of the open meter-side of the transistor (Q 1) to be applied to the base side and the transistor (Q 2) is gongjeop conventional video processing circuit via The configuration of 30 is the same as that of a general monitor circuit.
본 고안은 이와 같이 구성된 통상의 영상 처리회로(30)와 비데오 앰프(10)의 출력단자(P1) 사이에 직류차단용 콘덴서(C1)를 통하여 각각 바이어스 분배용 저항(R1-R4)과 연결된 인버터(N1)(N2)에 접속되게 동기분리 및 귀선소거부(20)가 구성되게 하여 인버터(N1)로 수직 및 수평동기신호(VH)가 출력되게 구성하고 인버터(N2)로 출력되는 귀선소거신호(M)는 트랜지스터(Q1)의 베이스측에 인가되게 구성시켜 된 것이다.The present invention is a bias distribution resistor (R 1- R 4 ) through the DC blocking capacitor (C 1 ) between the conventional image processing circuit 30 and the output terminal (P 1 ) of the video amplifier 10 configured as described above ) Is configured to be connected to the inverter (N 1 ) (N 2 ) connected to the synchronous separation and retracement unit 20 is configured to output the vertical and horizontal synchronous signal (VH) to the inverter (N 1 ) and inverter (N The retrace clear signal M output to 2 ) is configured to be applied to the base side of the transistor Q 1 .
여기서 인버터(N1)(N2)로 구성되는 동기분리 및 귀선소거부(20)는 일반적으로 널리 사용되고 있는 집적 소자(7416형)로서 저항(R1)(R3)와 연결되어 오픈 콜렉터가 되게 구성시킨 것이다.Here, the synchronous separation and blanking unit 20 composed of an inverter N 1 (N 2 ) is an integrated element 7416 that is widely used, and is connected to a resistor R 1 (R 3 ) so that an open collector is connected. It is configured.
이와 같이 구성된 본 고안에서 복합 영상신혼(VS)가 비데오 앰프(10)에 인가되면 비데오 앰프에서 신호 처리하여 비데오 신호는 출력단자(P2)로 출력시키며 수직 및 수평 동기 신호로 출력단자(P1)로 출력하게 되는 것으로 모니터 회로에서 널리 사용되고 있는 영상 처리회로(30)는 다음과 같은 동작을 수행하게 된다.When thus combined image honeymoon (VS) is applied to the video amplifier 10 in the present design is configured to signal processing in the video amplifier video signal output terminal (P 2) sikimyeo output to the output terminal in the vertical and horizontal synchronization signals (P 1 The image processing circuit 30 widely used in the monitor circuit performs the following operation.
트랜지스터(Q1)의 베이스측에는 콘덴서(C3) 및 저항(R6)을 통하여 전원(Vcc)이 인가되어 있고(대략 5V-2V) 트랜지스터(Q1)의 콜렉터측에는 인덕턴스 코일(L1) 및 저항(R7)(R8)으로 분배된 비교적 높은 중압(VBB)이 인가되어 있어 트랜지스터(Q2)가 비데오 신호에 의하여 "턴온" 시트랜지스터(Q1)의 에미터측이 저전위 상태가 되어 트랜지스터(Q1)도 턴온하게 되는 것으로 비데오 앰프(10)의 비데오 신호는 트랜지스터(Q2)(Q1)의 콜렉터측으로 반전 증폭되어 음극선관(40)에 영상 신호를 공급하게 된다.The power supply Vcc is applied to the base side of the transistor Q 1 through the capacitor C 3 and the resistor R 6 (approximately 5V-2V), and the inductance coil L 1 and to the collector side of the transistor Q 1 . A relatively high medium voltage (VBB) distributed by resistors (R 7 ) (R 8 ) is applied so that the transistor (Q 2 ) is turned on by the video signal and the emitter side of the sheet transistor (Q 1 ) becomes low potential. The transistor Q 1 is also turned on, and the video signal of the video amplifier 10 is inverted and amplified to the collector side of the transistors Q 2 and Q 1 to supply an image signal to the cathode ray tube 40.
또한 귀선소거 시간에도 트랜지스터(Q2)의 베이스측에는 턴온 될수 있는 일정한 레벨의 신호가 비데오 앰프(10)로 출력되고 이때에 트랜지스터(Q1)의 베이스측에는 전원(Vcc)과 귀선 소거 신호가 합성되어 공급되므로 베이스 바이어스 전압이 크게 되어 트랜지스터(Q1)는 증폭용이 아니라 스위칭 트랜지스터(Q1)도 구동하기 때문에 콜렉터측에 공급되는 중압(VBB)이 모두 트랜지스터(Q1)(Q2)로 흐르게 되어 귀선 소거 기간에는 음극 선관에 공급되는 전원을 차단시키게 되는 것이다.In addition, a signal of a constant level, which can be turned on at the base side of the transistor Q 2 , is output to the video amplifier 10 even during the blanking time. At this time, a power supply Vcc and a blanking signal are synthesized at the base side of the transistor Q 1 . Since the base bias voltage is increased, the transistor Q 1 drives the switching transistor Q 1 instead of the amplification, so that all of the medium voltage VBB supplied to the collector side flows to the transistor Q 1 Q 2 . In the blanking period, the power supplied to the cathode ray tube is cut off.
따라서 비데오 앰프(10)의 출력단자(P1)에서 콘덴서(C1)를 통하여 인가되는 수직 및 수평 동기 신호는 인버터(N1)를 통하여 반전되어 출력하게 되며 동기 신호 출력시 발생되어야 하는 귀선 소거신호(M)는 인버터(N2)에서 재반전되어 트랜지스터(Q1)의 베이스측에 인가되어 상기와 같은 귀선 소거 동작을 행할 수가 있는 것으로 논리 회로를 사용하기 때문에 신뢰성이 증가되며 동기분리 및 귀선 소거부(20)가 바이어스 분배되는 저항(R1)(R3)에 의하여 콜렉터 오픈용 증폭기로 동작될 수 있어 입력 저항이 높고 출력 저항이 낮은 특성을 그대로 이용할 수 있어 비데오 앰프와 연결시키기 편리한 동시에 동작이 안정되어 찌그러짐 없는 안정된귀선 소거 신호를 출력시킬 수 있는 효과가 있는 것이다.Therefore, the vertical and horizontal synchronizing signals applied through the condenser C 1 at the output terminal P 1 of the video amplifier 10 are inverted and outputted through the inverter N 1 , and the blanking that should be generated when the synchronizing signal is output. The signal M is inverted by the inverter N 2 and applied to the base side of the transistor Q 1 to perform the blanking operation as described above. Since the logic circuit is used, reliability is increased and synchronization is separated and returned. Since the eraser 20 can be operated as a collector open amplifier by the bias-distributing resistors R 1 and R 3 , the input resistance is high and the output resistance is low. The operation is stabilized, so that a stable retrace cancellation signal without distortion is output.
또한 수평, 수직동기 신호를 인버터(N1)(N2) 사이에서 인출시켜 플라이백트랜스에 인가시킬 때에 역시 오픈 콜렉터 저항(R1)(R2)을 통하여 공급되기 때문에 안정된 출력을 공급할 수가 있는 것이다.In addition, when the horizontal and vertical synchronous signals are drawn between the inverters N 1 and N 2 and applied to the flyback transformer, they are also supplied through the open collector resistor R 1 and R 2 . will be.
이상에서와 같이 본 고안은 발진 회로를 집적 회로의 논리 소자로서 구성하여 회로의 단순화를 기할 수있는 동시에 콜렉터오 픈용 증폭기로서 동작되게 하여 안정된 출력을 얻을 수가 있는 것으로 문자나 화상의 정보를 나타내는 모니터에 본고안의 회로를 적용할 때에 인가되는 동기신호에 따라 정확하게 구동하여 선명한 화상 신호를 나타낼 수 있는 모니터의 동기분리 및 귀선 소거회로를 제공할 수가 있는 것이다.As described above, the present invention can be configured as a logic element of an integrated circuit to simplify the circuit and to operate as a collector-open amplifier to obtain a stable output. It is possible to provide a synchronous separation and blanking circuit of a monitor which can be driven precisely in accordance with the synchronization signal applied when the circuit of the present invention is applied to display a clear image signal.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019840014245U KR880000408Y1 (en) | 1984-12-26 | 1984-12-26 | Monitor synchronization and blanking circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019840014245U KR880000408Y1 (en) | 1984-12-26 | 1984-12-26 | Monitor synchronization and blanking circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR860009018U KR860009018U (en) | 1986-07-31 |
| KR880000408Y1 true KR880000408Y1 (en) | 1988-03-10 |
Family
ID=19239070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019840014245U Expired KR880000408Y1 (en) | 1984-12-26 | 1984-12-26 | Monitor synchronization and blanking circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR880000408Y1 (en) |
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1984
- 1984-12-26 KR KR2019840014245U patent/KR880000408Y1/en not_active Expired
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| Publication number | Publication date |
|---|---|
| KR860009018U (en) | 1986-07-31 |
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