KR870003381Y1 - RAM Synchronization Signal Correction Circuit for Digital Audio Playback - Google Patents
RAM Synchronization Signal Correction Circuit for Digital Audio Playback Download PDFInfo
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- KR870003381Y1 KR870003381Y1 KR2019850007488U KR850007488U KR870003381Y1 KR 870003381 Y1 KR870003381 Y1 KR 870003381Y1 KR 2019850007488 U KR2019850007488 U KR 2019850007488U KR 850007488 U KR850007488 U KR 850007488U KR 870003381 Y1 KR870003381 Y1 KR 870003381Y1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
- G11B5/09—Digital recording
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
- G11B2020/10537—Audio or video recording
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Abstract
내용 없음.No content.
Description
제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.
제2도는 본 고안 회로도의 각부파형도.2 is an angle waveform diagram of the present invention circuit diagram.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기록/재생회로 20 : 동기신호 보정회로10: recording / reproducing circuit 20: synchronizing signal correction circuit
A1, A2: 앤드게이트 OR1, OR2, OR3, OR4, OR5: 오아게이드A 1 , A 2 : ANDGATE OR 1 , OR 2 , OR 3 , OR 4 , OR 5 : Ogade
M1, M2: 멀티플렉서 1 : 패리티생성 및 에러정정회로M 1 , M 2 : Multiplexer 1: Parity Generation and Error Correction Circuit
2 : 기록장치2: recording device
본 고안은 디지탈 오디오 재생시 램의 동기신호 보정회로에 관한 것이다. 디지탈 오디오기기는 아날로그 상태신호를 디지탈신호로 박환시켜 신호처리함으로써 원음을 재생처리하기 편리한 이점이 있으며 테이프에 녹음된 신호를 재생신호 처리시에 다수개의 헤드를 사용하여 램덤하게 기록된 상태신호(데이타의 보합를 위하여)를 다중처리 행하도록 하고 있으며 테이프에 기록된 것을 재생할 경우에 연집에러(Burst error)가 생기는 것을 방지하기 위하여 데이타 및 데이타를 보호할 목적으로 생성시키는 패리티를 분산시켜 기록하고 재생시에는 데이타 및 패리티램에 인가되는 데이타 및 패리티를 합성하도록 하여 에러정정회로를 통하여 원래의 데이타신호로 재생하도록 하였으나 데이타 및 패리티램이 각기 별도로 구성된 카운터에 의하여 동작하기 때문에 동기신호가 어긋나는 경우에는 올바른 데이타신호를 읽어낼 수가 없는 것이었다.The present invention relates to a synchronization signal correction circuit of a RAM in digital audio reproduction. Digital audio equipment has the advantage of reproducing the original sound by converting the analog state signal into a digital signal and processing the signal.The signal recorded on the tape is randomly recorded by using a plurality of heads during the reproduction signal processing. In order to prevent burst errors when playing back the recorded data on the tape, the parity generated for the purpose of protecting the data and data is distributed and recorded. And the data and parity applied to the parity RAM are synthesized to reproduce the original data signal through an error correction circuit. However, since the data and parity RAM are operated by separate counters, the correct data signal is output when the synchronization signal is out of order. Can read Was that.
본 고안의 목적은 디지탈 오디오기기에 있어서 테이프에 기록된 데이타신호를 재생시키고자 할때에 데이타 및 패리티가 인가되는 램을 구동시키는 카운터 1, 2에 일정시간마다 동기신호를 일치시켜 줄 수 있게한 디지탈 오디오 재생시 램의 동기신호 보정회로를 제공하고자 하는 것으로 별개로 구동하는 카운터 1, 2에 동기신호 보정회로의 카운터 3, 4 및 카운터 5의 출력에 의하여 일정시간 후 동기신호가 일치되게 구성한 것이다.An object of the present invention is to enable synchronization of a synchronization signal every predetermined time to counters 1 and 2 which drive a RAM to which data and parity are applied when a data signal recorded on a tape is to be reproduced in a digital audio device. It is to provide the synchronization signal correction circuit of RAM when digital audio is reproduced, and the synchronization signal is matched after a certain time by the outputs of the counters 3 and 4 and the counter 5 of the synchronization signal correction circuit, which are separately driven. .
이를 첨부도면에 의하여 상세히 설명하면 다음과 같다.When described in detail by the accompanying drawings as follows.
제1도는 본 고안의 회로도로서 기록/재생회로(10)와 동기신호 보정회로(20)로 구성되어 있으며 기록/재생회로(10)는 패리티 생성 및 에러정정회로(1)가 양방향성 멀티플렉서(M1)와 연결되어 카운터 1, 2와 연결된 램 1, 2에서 양방향성 멀티플렉서(M2)를 통하여 기록장치(2)와 연결되게 구성한 것으로 패리티 생성 및 에러정정회로(1)에서 패리티 생성회로는 기록장치(2)의 테이프에 데이타 상태신호를 기록하고자 할때에 패리티를 생성시켜 에러위치에 대한 정보가 기록되게 하고 에러정정회로는 기록장치에 기록된 데이타를 재생시키고자 할때에 재생된 데이타 상태신호를 에러정정 회로에서 정정시켜 올바른 데이타를 얻고자 구성시킨 것이다.1 is a circuit diagram of the present invention, which comprises a recording / reproducing circuit 10 and a synchronization signal correction circuit 20. The recording / reproducing circuit 10 has a parity generation and error correction circuit 1 having a bidirectional multiplexer (M 1). ) Is connected to the recording device 2 through the bidirectional multiplexer (M 2 ) in RAM 1 and 2 connected to the counters 1 and 2, and the parity generating circuit in the parity generating and error correction circuit (1) is a recording device ( Parity is generated when recording the data status signal on the tape of 2) so that information about the error position is recorded, and the error correction circuit records the reproduced data status signal when the data recorded on the recording device is to be reproduced. It is configured to get correct data by correcting in error correction circuit.
그리고 동기신호 보정회로(20)는 주시스템에서 인가되는 블럭싱크(BS)가 카운터리셋트용 오아게이트(OR3)(OR4)(OR5)와 연결된 카운터 3, 4, 5에 인가되게 구성시키며 앤드게이트(A1)(A2)에 의하여 일정시간마다 카운터된 리셋트 상태신호가 오아게이트(OR1)(OR2)를 통하여 각각의 카운터 1, 2에 인가되게 구성시킨 것으로 마스터 리셋트신호(MS)는 디지탈 오디오기기의 플레이 보턴구동시 발생되는 상태신호이다.In addition, the synchronization signal correction circuit 20 is configured such that the block sink BS applied from the main system is applied to the counters 3, 4, and 5 connected to the counter reset OR gates OR 3 (OR 4 ) and OR 5 . It is configured to apply the reset status signal countered by the AND gate A 1 (A 2 ) every predetermined time to the respective counters 1 and 2 through the ora gate OR 1 (OR 2 ). The signal MS is a state signal generated when driving the play button of the digital audio device.
여기서 각 카운터 4, 5에 앤드게이트(A1)(A2)를 구성시킨 것은 계수되는 카운터(28진 및 244진)의 카운터수에 따라 원하는 출력펄스(S2)(S3)를 얻기위한 것이다.Herein, the AND gates A 1 (A 2 ) are configured in each of the counters 4 and 5 to obtain a desired output pulse S 2 (S 3 ) according to the number of counters of the counters (28 and 244 numbers) to be counted. will be.
이와 같이 구성된 본 고안에서 에러정정용 코드를 사용하여 기록된 것을 재생한 경우에 연집에러(Burst error)를 방지하기 위하여 데이타의 에러를 정정할 수 있는 코드(parity)를 사용하여 인접한 데이타를 서로 분산시켜 기록장치(2)에 기록되게 된다.In the present invention configured as described above, when the recorded data is reproduced using the error correction code, the adjacent data are distributed to each other using a parity that can correct an error of the data in order to prevent burst errors. The recording device 2 is to be recorded.
즉 기록장치(2)의 테이프에 기록하고자 할때에는 양방향성 멀트플렉서(M2)를 통하여 램 1에 기록된 데이타 상태신호와 램 2에 기록된 패리티를 분산시켜 기록하게 되므로 이와 같이 분산된 데이타 및 패리티를 재생시켜 원래의 데이타를 생성시키기 위하여서는 기록시 분산시켰던 역순으로 데이타와 패리티가 합성되어 멀티플렉서(M1)를 통하여 패리티생성 및 에러정정회로(1)에 인가되어 에러정정회로에서 에러를 정정시켜 정상적인 데이타신호가 재생될 수 있도록 디지탈 신호처리를 행하고 있는 것이다.That is, when recording on the tape of the recording device 2, the data status signal recorded in the RAM 1 and the parity recorded in the RAM 2 are dispersed and recorded through the bidirectional multiplexer (M 2 ). In order to reproduce the parity and generate the original data, the data and parity are synthesized in the reverse order of the distribution, and applied to the parity generation and error correction circuit 1 through the multiplexer M 1 to correct the error in the error correction circuit. Digital signal processing is performed so that normal data signals can be reproduced.
(여기서 패리티 생성회로는 데이타를 테이프에 기록하고자 할때에 데이타에 의하여 생성된 패리티를 출력시키게 된다)(In this case, the parity generating circuit outputs the parity generated by the data when the data is to be written to the tape.)
그러나 재생시에 분산되었던 데이타와 패리티를 합성시키는 과정에서 데이타 램 1에 공급되는 카운터 1의 어드레서 카운터신호와 패리티 램 2에 공급되는 카운터 2의 어드레스 카운터신호가 서로 독립적으로 동작하게 됨으로 어느 시점에서 동기신호가 상호 어긋날 경우에는 두 동기신호가 상이하여 데이타 및 패리티를 정상적으로 합성시킬 수가 없어 에러정정회로에 정상적인 상태신호를 공급할 수 없게 되는 것이었다.However, in the process of synthesizing the data and parity distributed at the time of reproduction, the address counter signal of the counter 1 supplied to the data RAM 1 and the address counter signal of the counter 2 supplied to the parity RAM 2 operate independently of each other. When the signals are different from each other, the two synchronization signals are different so that data and parity cannot be synthesized normally, so that a normal state signal cannot be supplied to the error correction circuit.
본 고안은 이와 같이 카운터 1, 2가 별개로 동작할때에 서로 동기신호가 어긋나는 것을 동기신호 보정회로(20)에서 일정시간 후 항상 일치되는 동기신호를 카운터 1, 2에 인가시켜 램 1, 2가 오동작을 행하는 것을 방지할 수 있게 되는 것이다.In the present invention, when the counters 1 and 2 operate separately, the synchronization signals are shifted from each other so that the synchronization signal correction circuit 20 always applies the same synchronization signal to the counters 1 and 2 after a predetermined time. It is possible to prevent the malfunction from occurring.
즉, 재생초기에는 도시되지 아니한 플레이 보턴에 의하여 마스터리 셋트신호(MS)가 오아게이트(OR1)(OR3)(OR4)(OR5)를 통하여 카운터 1, 2, 3, 4, 5에 전부 인가되어 정상적인 카운터동작을 행할 수 있게되는 것으로 주시스템회로에서 인가되는 블럭싱크(BS)에 의하여 카운터 3, 4, 5는 정상적인 카운터 동작을 수행하게 된다.That is, in the initial stage of reproduction, the master set signal MS is transmitted to the counters 1, 2, 3, 4, 5 through the oragate OR 1 (OR 3 ) (OR 4 ) (OR 5 ) by a play button (not shown ). The counters 3, 4 and 5 perform the normal counter operation by the block sink BS applied from the main system circuit.
따라서 제2도와 같이 마스터 리셋트신호(MS) 인가후 블럭싱크(BS)에 의하여 카운터 3, 4, 5가 행하게 되면 카운터 3은 32진 카운터로 구동하여 32번째의 펄스(S1)발생시 오아게이트(OR3)를 통하여 카운터 3를 리셋트시키는 동시에 오아게이트(OR1)를 통하여 카운터 1를 리셋트시키므로 카운터 1은 카운터 3의 리셋트 출력에 동기되어 램 1에 기록되는 데이타에 어드레스신호를 인가시키게 된다. 그리고 카운터 4는 앤드게이트(A1)와 연설되어 28진 카운터로서 구동하게 되는 것으로 28번째의 펄스(S2)발생시 오아게이트(OR2)(OR4)를 통하여 카운터 2, 4가 동시에 리셋트되어 동기신호가 일치하게 되므로 램 2에 패리티 어드레스신호를 인가시키게 된다.Therefore, if the counters 3, 4, and 5 are performed by the block sync BS after the master reset signal MS is applied as shown in FIG. 2, the counter 3 is driven as a 32-degree counter to generate an oragate when the 32nd pulse S 1 is generated. Counter 1 is reset via (OR 3 ) and counter 1 is reset through OR gate (OR 1 ), so that counter 1 applies an address signal to data written to RAM 1 in synchronization with the reset output of counter 3. Let's go. The counter 4 is driven to the end gate A 1 and is driven as a 28-degree counter. When the 28th pulse S 2 occurs, the counters 2 and 4 are simultaneously reset through the ora gate OR 2 (OR 4 ). Therefore, the synchronization signal is matched, thereby applying the parity address signal to the RAM 2.
이와 같이 카운터 3에 동기되는 카운터 1의 출력과 카운터 4에 동기되는 카운터 2의 출력신호가 일치되는 경우에는 정상적인 재생동작을 수행할 수가 있으나 카운터 3, 4의 오동작에 의하여 정확하게 동기신호가 일치되지 않는 경우를 대비하여 앤드게이트(A2)와 연설된 카운터 5는 카운터 3, 4의 최소공배수(28, 32)=224이므로 224진 카운터로 동작하게 하여 제2도와 같이 카운터 3, 4의 출력펄스(S1)(S2)가 일치되지 않더라도 강제적으로 224진 카운터펄스(S3)가 오아게이트(OR1)(OR2)를 통하여 카운터 1, 2를 리셋트시킬 수가 있으므로 카운터 1, 2가 오동작을 행하더라도 일정시간 후 카운터 1, 2의 동기신호를 일치시켜 에러정정회로에 재생된 데이타신호를 인가시켜 줄 수 있는 효과가 있는 것이다.As described above, when the output of the counter 1 synchronized with the counter 3 and the output signal of the counter 2 synchronized with the counter 4 coincide with each other, the normal reproducing operation can be performed. For the case, counter 5 spoken with AND gate (A 2 ) is the least common multiple (28, 32) = 224 of counters 3 and 4, so that it operates as a 224 binary counter so that the output pulses of counters 3 and 4 (Fig. Even if S 1 ) (S 2 ) does not match, counters 1 and 2 malfunction because the 224-definition counter pulse S 3 can force the reset of counters 1 and 2 through the OR gate OR 1 and OR 2 . Even if the operation is performed, the synchronization signal of the counters 1 and 2 can be matched to apply the reproduced data signal to the error correction circuit after a certain time.
이상에서와 같이 본 고안은 기록된 데이타의 재생시에 램 1, 2에 기록되는 데이타 및 패리티 상태신호가 카운터 1, 2에 의하여 저장될때 동기신호 보정회로(20)의 카운터 3, 4에 동기되어 카운터 1, 2가 동작되게 하며 카운터 5에서 일정시간 후 재동기되게 함으로써 일치되는 동기신호를 공제할 수 있어 디지탈 상태신호의 재생시에 올바른 데이타신호를 전송시킬 수 있는 효과가 있는 것이다.As described above, the present invention is synchronized with the counters 3 and 4 of the synchronization signal correction circuit 20 when the data and the parity status signals recorded in the RAMs 1 and 2 are stored by the counters 1 and 2 when the recorded data is reproduced. By activating 1 and 2 and resynchronizing after a certain time at counter 5, the same synchronization signal can be subtracted, which is effective in transmitting the correct data signal when the digital state signal is reproduced.
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| Application Number | Priority Date | Filing Date | Title |
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| KR2019850007488U KR870003381Y1 (en) | 1985-06-20 | 1985-06-20 | RAM Synchronization Signal Correction Circuit for Digital Audio Playback |
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| Application Number | Priority Date | Filing Date | Title |
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| KR2019850007488U KR870003381Y1 (en) | 1985-06-20 | 1985-06-20 | RAM Synchronization Signal Correction Circuit for Digital Audio Playback |
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| Publication Number | Publication Date |
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| KR870001163U KR870001163U (en) | 1987-02-20 |
| KR870003381Y1 true KR870003381Y1 (en) | 1987-10-15 |
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| KR20010099486A (en) * | 2001-10-08 | 2001-11-09 | 윤규석 | Auto Folding Umbrella |
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| KR20010099486A (en) * | 2001-10-08 | 2001-11-09 | 윤규석 | Auto Folding Umbrella |
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| KR870001163U (en) | 1987-02-20 |
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