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KR860006870A - Current mirror circuit - Google Patents

Current mirror circuit Download PDF

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Publication number
KR860006870A
KR860006870A KR1019860000360A KR860000360A KR860006870A KR 860006870 A KR860006870 A KR 860006870A KR 1019860000360 A KR1019860000360 A KR 1019860000360A KR 860000360 A KR860000360 A KR 860000360A KR 860006870 A KR860006870 A KR 860006870A
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KR
South Korea
Prior art keywords
transistor
collector
power supply
current
vcc
Prior art date
Application number
KR1019860000360A
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Korean (ko)
Other versions
KR900001169B1 (en
Inventor
사또시 히야마
Original Assignee
가부시끼가이샤 도오시바
사바쇼오이찌(외 1)
도오시바 오디오.비디오 엔지니어링 가부시끼가이샤
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Application filed by 가부시끼가이샤 도오시바, 사바쇼오이찌(외 1), 도오시바 오디오.비디오 엔지니어링 가부시끼가이샤 filed Critical 가부시끼가이샤 도오시바
Publication of KR860006870A publication Critical patent/KR860006870A/en
Application granted granted Critical
Publication of KR900001169B1 publication Critical patent/KR900001169B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/907—Temperature compensation of semiconductor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

내용 없음No content

Description

전류미러회로Current mirror circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예를 나타낸 회로구성도. 제2도는 본 발명의 다른 실시예를 나타낸 회로구성도. 제3도는 종래회로의 구성도.1 is a circuit diagram showing an embodiment of the present invention. 2 is a circuit diagram showing another embodiment of the present invention. 3 is a block diagram of a conventional circuit.

Q1, Q2-트랜지스터, Q3, Q4-다이오드, I1, I3-정전류원, I2-입력전류원.Q 1 , Q 2 -transistor, Q 3 , Q 4 -diode, I 1 , I 3 -constant current source, I 2 -input current source.

Claims (5)

전원공급단자(Vcc)와, 기준전위단(G), 에미터가 상기 기준 전위단(G)에 연결됨과 아울러 콜렉터가 상기 전원공급단자(Vcc)측에 연결되어 있는 제1의 트랜지스터(Q1), 상기 트랜지스터(Q1)와 동일도전형으로 되어 있으면서 그 에미터가 상기 기준전위단(G)에 연결되어 있는 제2의 트랜지스터(Q2), 상기 트랜지스터(Q1)(Q2)의 베이스를 접속시키기 위한 제1의 수단(B), 상기 제1트랜지스터(Q1)의 콜렉터를 전류 입력 노우드(A)에 접속시키기 위한 제2의 수단(C), 상기 전원공급단자(Vcc)와 제1의 수단(B)간에 설치된 전류원 수단(I1) 및 상기 전원공급단자(Vcc)와 제2트랜지스터(Q2)의 콜렉터간에 설치된 부하회로수단(L)등으로 이루어진 전류미러회로에 있어서, 상기 제1트랜지스터(Q1)의 베이스-에미터 접합면적 보다도 큰 접합면적으로 되어 있으면서 제1트랜지스터(Q1)의 베이스와 콜렉터간에 접속되어 상기 전류원수단(I1)으로부터 전류입력 노우드(A)로 전류를 인가하도록 되어 있는 다이오드형의 제3수단(Q3)을 구비하고 있음을 특징으로 하는 전류미러회로.The first transistor Q 1 having a power supply terminal Vcc, a reference potential terminal G, and an emitter connected to the reference potential terminal G, and a collector connected to the power supply terminal Vcc side. ), the transistor (Q 1) and the same is also supposed to type the emitter is the reference potential terminal (G) a second transistor (Q 2 in) which is connected to the transistor (Q 1) (Q 2) of the First means (B) for connecting a base, second means (C) for connecting the collector of the first transistor (Q 1 ) to the current input norm (A), and the power supply terminal (Vcc) And a current source means (I 1 ) provided between the first means (B) and a load circuit means (L) provided between the power supply terminal (Vcc) and the collector of the second transistor (Q 2 ). , the base of the first transistor (Q 1) - while the large contact area than the emitter junction area of the first transistor Characterized by the connection between the base and the collector of the (Q 1) that comprises a third means (Q 3) of the diode type which is arranged to apply a current with a current input Norwood (A) from said current source means (I 1) Current mirror circuit. 제1항에 있어서, 부하회로수단(L)이 전원공급단자(Vcc)와 제2트랜지스터(Q2)의 콜렉터간에 접속되는 제2의 전류원(I3)을 포함하고 있는 전류미러회로.The current mirror circuit according to claim 1, wherein the load circuit means (L) comprises a second current source (I 3 ) connected between the power supply terminal (Vcc) and the collector of the second transistor (Q 2 ). 제1항에 있어서, 부하회로수단(L)이 전원공급단자(Vcc)와 제2트랜지스터(Q2)간에 접속되는 저항(R)을 포함하고 있는 전류미러회로.The current mirror circuit according to claim 1, wherein the load circuit means (L) comprises a resistor (R) connected between the power supply terminal (Vcc) and the second transistor (Q 2 ). 제1항에 있어서, 제1, 제2 트랜지스터(Q1)(Q2)가 NPN형인 전류미러회로.The current mirror circuit according to claim 1, wherein the first and second transistors (Q 1 ) (Q 2 ) are of NPN type. 전원공급단자(Vcc)와, 기준전위단(G), 에미터가 상기 기준전위단(G)에 연결되고 콜렉터가 상기 전원공급단자(Vcc)측에 연결되어 있는 제1의 트랜지스터(Q1), 상기 트랜지스터(Q1)와 동일 도전형으로 되어 있으면서 그 에미터가 상기 기준전위단(G)에 연결되어 있는 제2의 트랜지스터(Q2), 상기 트랜지스터(Q1)(Q2)의 베이스를 접속시키기 위한 제1의 수단(B), 상기 트랜지스터(Q1)의 콜렉터를 전류입력 노우드(A)에 접속시키기 위한 제2의 수단(C), 상기 전원공급단자(Vcc)와 제1수단(B)에 설치된 전류원수단(I1), 상기 전원공급단자(Vcc)와 제2트랜지스터(Q2)의 콜렉터간에 설치된 부하회로수단(L)등으로 이루어진 전류미러회로에 있어서, 상기 제1트랜지스터(Q1)의 베이스-에미터 접합면적보다 큰 접합면적으로 되어 있으면서 제1트랜지스터(Q1)의 베이스와 콜렉터간에 접속되어 상기 전류원(I1)으로부터 전류입력 노우드(A)로 전류를 인가하도록 되어있는 제1 다이오드 접합수단(Q3)과, 상기 제2 트랜지스터(Q2)의 베이스-에미터 접합면적보다 큰 접합면적으로 되어 있으면서 상기 제2 트랜지스터(Q2)의 베이스와 콜렉터간에 접속되어 상기 전류원(I1)으로부터 제2 트랜지스터(Q2)의 콜렉터로 전류를 인가하도록 되어있는 제2 다이오드 접합수단(Q4)을 구비하여 이루어진 것을 특징으로 하는 전류미러회로.A first transistor Q 1 having a power supply terminal Vcc, a reference potential terminal G, and an emitter connected to the reference potential terminal G, and a collector connected to the power supply terminal Vcc side. A second transistor Q 2 and a base of the transistor Q 1 and Q 2 having the same conductivity type as the transistor Q 1 , and whose emitters are connected to the reference potential terminal G; First means (B) for connecting a second means, second means (C) for connecting the collector of the transistor (Q 1 ) to the current input norm (A), and the power supply terminal (Vcc) and the first A current mirror circuit comprising a current source means I 1 provided in a means B, a load circuit means L provided between the power supply terminal Vcc and a collector of a second transistor Q 2 , and the like. transistor (Q 1) of the base-emitter junction area than the supposed large joining area of the first transistor, the base and the call (Q 1) Is connected between the emitter base of a first diode junction means (Q 3) and said second transistor (Q 2) which is arranged to apply a current with a current input Norwood (A) from said current source (I 1) - emitter junction while in area than it is the large junction area claim adapted to be connected between the base and the collector of the second transistor (Q 2) applying a current to the collector of the second transistor (Q 2) from said current source (I 1) 2 diode junction A current mirror circuit comprising a means (Q 4 ). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860000360A 1985-02-14 1986-01-21 Current mirror circuit KR900001169B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27383 1985-02-14
JP60-27383 1985-02-14
JP60027383A JPS61187406A (en) 1985-02-14 1985-02-14 Low voltage current mirror circuit

Publications (2)

Publication Number Publication Date
KR860006870A true KR860006870A (en) 1986-09-15
KR900001169B1 KR900001169B1 (en) 1990-02-27

Family

ID=12219524

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000360A KR900001169B1 (en) 1985-02-14 1986-01-21 Current mirror circuit

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US (1) US4647840A (en)
JP (1) JPS61187406A (en)
KR (1) KR900001169B1 (en)
DE (1) DE3604530A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3545039A1 (en) * 1985-12-19 1987-07-02 Sgs Halbleiterbauelemente Gmbh VOLTAGE LIMIT CIRCUIT
JPH065493B2 (en) * 1986-02-25 1994-01-19 株式会社東芝 Constant current supply circuit
US4975632A (en) * 1989-03-29 1990-12-04 Texas Instruments Incorporated Stable bias current source
US5502406A (en) * 1995-03-06 1996-03-26 Motorola, Inc. Low power level shift circuit and method therefor
US6885239B2 (en) * 2001-10-31 2005-04-26 Kabushiki Kaisha Toshiba Mobility proportion current generator, and bias generator and amplifier using the same
DE10219003B4 (en) * 2002-04-27 2004-07-08 Xignal Technologies Ag Current mirror for an integrated circuit
US20050263021A1 (en) 2004-05-31 2005-12-01 Fuji Photo Film Co., Ltd. Platemaking method for lithographic printing plate precursor and planographic printing method
US7522002B2 (en) * 2007-01-04 2009-04-21 Atmel Corporation Biasing current to speed up current mirror settling time

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139163A (en) * 1977-05-12 1978-12-05 Toshiba Corp Constant voltage generator circuit
JPS5639608A (en) * 1979-09-07 1981-04-15 Hitachi Ltd Current miller circuit
US4297646A (en) * 1980-01-25 1981-10-27 Motorola Inc. Current mirror circuit
US4329639A (en) * 1980-02-25 1982-05-11 Motorola, Inc. Low voltage current mirror
JPS5767447A (en) * 1980-10-08 1982-04-24 Kazufumi Kachi Cutting and winding device in toilet paper winder
US4414502A (en) * 1981-07-20 1983-11-08 Advanced Micro Devices, Inc. Current source circuit
JPS6033717A (en) * 1983-08-04 1985-02-21 Toshiba Corp Current mirror circuit

Also Published As

Publication number Publication date
DE3604530A1 (en) 1986-08-21
DE3604530C2 (en) 1988-07-28
US4647840A (en) 1987-03-03
KR900001169B1 (en) 1990-02-27
JPS61187406A (en) 1986-08-21
JPH0367366B2 (en) 1991-10-22

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