KR20250122849A - Semiconductor substrate inspection method of wide bandgap material - Google Patents
Semiconductor substrate inspection method of wide bandgap materialInfo
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Abstract
본 발명은 와이드 밴드갭 소재의 반도체 기판 검사 방법에 관한 것으로서, 반도체 기판 검사면을 Optical Microscopy(OM)로 검사하여 표면 삼각결함을 탐색하는 단계; 탐색된 표면 삼각결함의 성장방향에 대하여 우측면에 위치하는 영역을 내부결함 예상영역으로 설정하는 단계;를 포함하여 이루어지는 것을 특징으로 한다.
본 발명에 의하여, 표면 삼각결함이 발생되면 내부결함 발생확률이 높은 부분을 표시하여 결함탐지 신뢰도를 향상시키는 와이드 밴드갭 소재의 반도체 기판 검사 방법을 제공하는 이점이 있다.The present invention relates to a method for inspecting a semiconductor substrate of a wide bandgap material, and is characterized by comprising the steps of: inspecting a semiconductor substrate inspection surface using an optical microscope (OM) to detect surface triangular defects; and setting an area located on the right side with respect to the growth direction of the detected surface triangular defects as an expected area of internal defects.
According to the present invention, there is an advantage in providing a method for inspecting a semiconductor substrate of a wide bandgap material, which improves the reliability of defect detection by indicating a part where an internal defect occurrence probability is high when a surface triangular defect occurs.
Description
본 발명은 와이드 밴드갭 소재의 반도체 기판 검사 방법에 관한 것으로서, 표면 삼각결함이 탐색되면, 표면에는 결함이 없지만 내부결함이 확산되었을 가능성이 있는 영역을 내부결함 예상영역으로 표시하여 결함 탐색 신뢰도를 향상시키는 기술에 관한 것이다. The present invention relates to a method for inspecting a semiconductor substrate of a wide bandgap material, and relates to a technique for improving the reliability of defect detection by indicating an area where there is no defect on the surface but an internal defect may have spread as an area expected to have an internal defect when a surface triangular defect is detected.
일반적으로 실리콘 카바이드(SiC)와 같은 와이드밴드 갭 소재는 실리콘(Si)에 비하여 절연 파괴 전계가 약 10배 크고, 밴드 갭도 약 3배 크다는 등의 우수한 특성을 가지므로, 파워 디바이스, 고온 동작 디바이스 등에의 응용이 기대되고 있다.In general, wide band gap materials such as silicon carbide (SiC) have excellent characteristics such as an insulation breakdown field that is about 10 times larger than that of silicon (Si) and a band gap that is about 3 times larger, so their application to power devices and high-temperature operating devices is expected.
이러한 SiC 디바이스는, 승화 재결정법 등으로 성장시킨 SiC의 벌크 단결정으로부터 가공하여 얻어진 SiC 단결정 기판 상에, 화학적 기상 성장법(Chemical Vapor Deposition: CVD) 등에 의하여 디바이스의 활성 영역으로 되는 SiC 에피택셜층을 성장시킨 SiC 에피택셜 웨이퍼를 사용하여 제작되는 것이 일반적이다.These SiC devices are generally manufactured using a SiC epitaxial wafer in which a SiC epitaxial layer, which becomes the active region of the device, is grown by a chemical vapor deposition (CVD) method or the like on a SiC single crystal substrate obtained by processing from a bulk single crystal of SiC grown by a sublimation recrystallization method or the like.
SiC 단결정 기판에는 많은 결정 결함이 존재하고, 그 결정 결함이 에피택셜층에 전파되는 것이 알려져 있다. 그 때문에, 그 전파를 고려한 에피택셜층의 품질 향상을 위한 기술 개발이 진행되고 있다.SiC single-crystal substrates are known to contain numerous crystal defects, and these defects are known to propagate into the epitaxial layer. Therefore, technology development is underway to improve the quality of the epitaxial layer by taking these defects into account.
SiC 단결정 기판이나 그 위에 에피택셜층이 형성된 SiC 에피택셜 웨이퍼 내에 포함되는 전위나 적층 결함 등의 결정 결함을 비파괴로 검출하는 방법으로서는, X선 토포그래피법이나, 포토 루미네센스법이 알려져 있다.Known methods for non-destructively detecting crystal defects such as dislocations or stacking faults contained in a SiC single crystal substrate or a SiC epitaxial wafer on which an epitaxial layer is formed include X-ray topography and photoluminescence.
도 6은 SiC 에피택셜 웨이퍼의 결함을 광학현미경(Optical Microscopy(OM)), XRT(X-ray topography), PL(Photoluminescence) 및 EBIC(Electron Beam Induced Current)로 검사한 사진이다.Figure 6 is a photograph of a SiC epitaxial wafer inspected for defects using optical microscopy (OM), X-ray topography (XRT), photoluminescence (PL), and electron beam induced current (EBIC).
도 6a에서 보여지는 바와 같이 광학현미경으로 보여지는 에피택셜층 표면에는 아무런 결함이 탐색되지 않지만, XRT, PL 및 EBIC에서는 내부 결함이 탐색되고 있으므로, 내부 결함에 대한 조사는 필수적임을 알 수 있다.As shown in Fig. 6a, no defects are detected on the surface of the epitaxial layer as seen by an optical microscope, but internal defects are detected by XRT, PL, and EBIC, so it can be seen that investigation of internal defects is essential.
도 6b는 도 6a의 사진에서 결함부분을 강조하여 표시한 사진이다.Figure 6b is a photograph that highlights the defective portion in the photograph of Figure 6a.
SiC 에피택셜층에서 발생되는 삼각결함은 품질을 열화시키는 원인으로 알려져 있다. Triangular defects occurring in SiC epitaxial layers are known to cause quality deterioration.
SiC 에피택셜층의 삼각결함은 웨이퍼 표면에 남아있는 연마 흠집, 스텝 플로우 성장 중에 테라스에 형성되는 2차원 핵, 성장 초기의 과포화 상태일 때 기판과 에피택셜층의 계면에 형성되는 이종의 폴리타입의 결정핵, SiC막의 미소 파편 등 다양한 원인에 의하여 발생되는 것으로 연구되고 있다.Triangular defects in SiC epitaxial layers are being studied to be caused by various factors, including polishing scratches remaining on the wafer surface, two-dimensional nuclei formed on terraces during step flow growth, heterogeneous polytype crystal nuclei formed at the interface between the substrate and the epitaxial layer during supersaturation in the early stage of growth, and micro-fragments in the SiC film.
SiC 에피택셜층은, SiC 단결정 기판을 10° 이내의 오프 각으로 경사지게 하여 스텝 밀도를 고의로 높게 한 면을 성장면으로 하여, 스텝의 가로 방향으로의 결정 성장(스텝 플로우 성장)하여 형성하는 것이 일반적이다.The SiC epitaxial layer is generally formed by growing crystals in the transverse direction of the steps (step flow growth) by tilting the SiC single crystal substrate at an off-angle of less than 10° and using the surface with an intentionally high step density as the growth surface.
상기 삼각 결함(1)은 도 2(비특허문헌 [0001]의 인용 그림)에서 보여지는 바와 같이 스텝 플로우 성장 방향을 따라 삼각형의 정점(10)과 그 대변(20)이 순서대로 배열되는 방향을 향하여 형성되므로, SiC 에피택셜층의 성장과 함께 성장해 간다. The above triangular defect (1) is formed in a direction in which the vertex (10) and its opposite side (20) of the triangle are sequentially arranged along the step flow growth direction as shown in FIG. 2 (a drawing cited in non-patent literature [0001]), and thus grows together with the growth of the SiC epitaxial layer.
따라서, 삼각결함(1)에는 도 2와 같이 성장방향(30)을 정의할 수 있다.Therefore, the growth direction (30) can be defined for the triangular defect (1) as shown in Fig. 2.
삼각결함(1)은 스텝 플로우 성장과 함께, 상기 기점을 삼각형의 정점(10)으로 하여, 대략 삼각형의 상사형을 유지하면서 그 면적을 크게 하도록 성장해 간다.The triangle defect (1) grows with step flow growth, with the starting point being the vertex of the triangle (10), and grows to increase its area while maintaining a roughly triangular shape.
따라서, 일반적으로 결함 기점이 SiC 에피택셜층의 성장 초기에 발생한 삼각 결함일수록 크기가 크므로, 삼각 결함(1)의 크기로부터 내면 기점의 깊이를 추측할 수 있다.Therefore, since the defect origin is generally a triangular defect that occurs in the early stage of growth of the SiC epitaxial layer, the size of the defect origin is larger, so the depth of the inner origin can be estimated from the size of the triangular defect (1).
그런데, 이와 같은 삼각결함은 높은 확률로 내부에 결함이 확산 전파되어 있으며, 이는 광학현미경으로 탐색되지 않는 부분이어서 탐색다이의 설정 등을 위하여 내부결함 발생확률이 높은 부분의 표기가 요구되고 있다.However, such triangular defects have a high probability of internally spreading defects, and since these are areas that cannot be detected by an optical microscope, marking of areas with a high probability of internal defect occurrence is required for purposes such as setting up a search die.
본 발명은 상기한 문제점을 해결하기 위한 것으로서, 표면 삼각결함이 발생되면 높은 확률로 내부에 결함이 확산 전파되어 있으므로 내부결함의 탐색 신뢰도를 향상시키기 위하여 내부결함 발생확률이 높은 부분을 표시하는 와이드 밴드갭 소재의 반도체 기판 검사 방법을 제공하는 것을 목적으로 한다.The present invention is intended to solve the above-mentioned problem, and since there is a high probability that a defect will diffuse and propagate internally when a surface triangular defect occurs, the purpose of the present invention is to provide a method for inspecting a semiconductor substrate made of a wide bandgap material, which indicates a part with a high probability of occurrence of an internal defect, in order to improve the reliability of detection of an internal defect.
상기한 목적을 달성하기 위하여 본 발명은 와이드 밴드갭 소재의 반도체 기판 검사 방법에 있어서, 반도체 기판 검사면을 Optical Microscopy(OM)로 검사하여 표면 삼각결함을 탐색하는 단계; 탐색된 표면 삼각결함의 성장방향에 대하여 우측면에 위치하는 영역을 내부결함 예상영역으로 설정하는 단계;를 포함하여 이루어지는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법을 기술적 요지로 한다. In order to achieve the above-mentioned purpose, the present invention provides a method for inspecting a semiconductor substrate of a wide bandgap material, comprising: a step of inspecting a semiconductor substrate inspection surface using an optical microscope (OM) to detect surface triangular defects; and a step of setting an area located on the right side with respect to the growth direction of the detected surface triangular defects as an expected area of internal defects.
본 발명에서 상기 반도체 기판 검사면을 복수 개의 단위 검사영역으로 구획시키는 단계;를 더 포함하여 표면 삼각결함의 성장방향에서 우측면에 위치하는 단위 검사영역들을 내부결함 예상영역으로 설정하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In the present invention, it is preferable to provide a method for inspecting a semiconductor substrate of a wide bandgap material, characterized in that it further comprises a step of dividing the semiconductor substrate inspection surface into a plurality of unit inspection areas, and setting the unit inspection areas located on the right side in the growth direction of surface triangular defects as expected internal defect areas.
또한, 상기 반도체 기판은 갈륨나이트라이드(GaN) 또는 실리콘 카바이드(SiC) 에피택셜 웨이퍼인 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In addition, it is preferable that the semiconductor substrate be a method for inspecting a wide band gap material semiconductor substrate characterized in that the semiconductor substrate is a gallium nitride (GaN) or silicon carbide (SiC) epitaxial wafer.
또한, 상기 내부결함 예상영역은 삼각결함에 인접할수록 결함발생 확률이 높은 것으로 평가하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In addition, it is preferable that the above internal defect prediction area be a method for inspecting a semiconductor substrate of a wide band gap material, characterized in that the closer it is to a triangular defect, the higher the probability of defect occurrence.
또한, 상기 삼각결함의 성장방향은 삼각결함 정점에서 대변으로 내린 제1 수선과 방향으로 정의하며, 상기 내부결함 예상영역은 상기 제1 수선의 중심에서 상기 성장방향의 우측면 방향으로 상기 제1 수선에 수직하게 연장한 제2 수선에 가까울 수록 결함발생 확률이 높은 것으로 평가하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In addition, the growth direction of the above-mentioned triangular defect is defined as the direction of the first perpendicular line extending from the vertex of the triangular defect to the opposite side, and the internal defect prediction area is preferably a method for inspecting a semiconductor substrate of a wide band gap material, characterized in that the closer it is to the second perpendicular line extending perpendicularly to the first perpendicular line in the direction of the right side of the growth direction from the center of the first perpendicular line, the higher the probability of defect occurrence.
또한, 반도체 기판 검사면에 결함예상 영역을 표시한 결함예상 맵을 출력시키는 단계를 더 포함하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In addition, it is preferable to provide a method for inspecting a semiconductor substrate of a wide bandgap material, characterized by further including a step of outputting a defect prediction map indicating a defect prediction area on a semiconductor substrate inspection surface.
또한, 본 발명은 상기 결함예상 영역을 XRT(X-ray topography), PL(Photoluminescence) 및/또는 EBIC(Electron Beam Induced Current)의 타겟 검사영역으로 설정하여 내부결함 검사가 수행되게 하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법으로 되는 것이 바람직하다. In addition, the present invention is preferably a method for inspecting a semiconductor substrate of a wide band gap material, characterized in that the defect prediction area is set as a target inspection area of XRT (X-ray topography), PL (Photoluminescence) and/or EBIC (Electron Beam Induced Current) to perform an internal defect inspection.
상기한 본 발명에 의하여, 표면 삼각결함이 발생되면 내부결함 발생확률이 높은 부분을 표시하여 결함탐지 신뢰도를 향상시키는 와이드 밴드갭 소재의 반도체 기판 검사 방법을 제공하는 이점이 있다.According to the present invention described above, there is an advantage in providing a method for inspecting a semiconductor substrate of a wide bandgap material, which improves the reliability of defect detection by indicating a part where the probability of occurrence of an internal defect is high when a surface triangular defect occurs.
도 1은 본 발명의 순서도
도 2는 비특허문헌 [0001]의 인용 그림으로서, 와이드 밴드갭(WBG) 반도체의 에피택셜층 삼각결함 형성과정 설명도
도 3은 결함검사 장치별 와이드 밴드갭(WBG) 반도체의 에피택셜층 삼각결함 사진
도 4는 본 발명의 설명도
도 5는 본 발명의 일 실시예에 대한 출력도
도 6은 와이드 밴드갭(WBG) 반도체의 에피택셜층 내부결함 사진 Figure 1 is a flow chart of the present invention.
Figure 2 is a drawing cited from non-patent literature [0001], and is an explanatory diagram of the formation process of triangular defects in the epitaxial layer of a wide band gap (WBG) semiconductor.
Figure 3 is a photograph of a triangular defect in the epitaxial layer of a wide bandgap (WBG) semiconductor by defect inspection device.
Figure 4 is an explanatory diagram of the present invention.
Figure 5 is an output diagram for one embodiment of the present invention.
Figure 6 is a photograph of internal defects in the epitaxial layer of a wide bandgap (WBG) semiconductor.
이하 도면을 참조하여 본 발명에 관하여 살펴보기로 하며, 본 발명을 설명함에 있어서 관련된 공지기술 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략할 것이다. The present invention will be described with reference to the drawings below. In explaining the present invention, if it is determined that a detailed description of a related known technology or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.
그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있으므로 그 정의는 본 발명을 설명하는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. And the terms described below are terms defined in consideration of their functions in the present invention, and may vary depending on the intention or custom of the user or operator, so their definitions should be made based on the contents throughout this specification explaining the present invention.
이하의 도 1은 본 발명의 순서도이며, 도 2는 와이드 밴드갭(WBG) 반도체의 에피택셜층 삼각결함 형성과정 설명도이며, 도 3은 결함검사 장치별 와이드 밴드갭(WBG) 반도체의 에피택셜층 삼각결함 사진이고, 도 4는 본 발명의 설명도이며, 도 5는 본 발명의 일 실시예에 대한 출력도이며, 도 6은 와이드 밴드갭(WBG) 반도체의 에피택셜층 내부결함 사진이다.The following Figure 1 is a flowchart of the present invention, Figure 2 is a diagram explaining a process of forming a triangular defect in an epitaxial layer of a wide bandgap (WBG) semiconductor, Figure 3 is a photograph of a triangular defect in an epitaxial layer of a wide bandgap (WBG) semiconductor according to a defect inspection device, Figure 4 is a diagram explaining the present invention, Figure 5 is an output diagram for one embodiment of the present invention, and Figure 6 is a photograph of an internal defect in an epitaxial layer of a wide bandgap (WBG) semiconductor.
도면에 도시된 바와 같이 본 발명은 와이드 밴드갭 소재의 반도체 기판 검사 방법에 관한 것이다.As illustrated in the drawing, the present invention relates to a method for inspecting a semiconductor substrate of a wide bandgap material.
본 발명이 적용되는 상기 와이드 밴드갭 소재의 반도체 기판의 일 실시예는 갈륨나이트라이드(GaN) 또는 실리콘 카바이드(SiC) 에피택셜 웨이퍼가 있다.One example of a semiconductor substrate of the wide bandgap material to which the present invention is applied is a gallium nitride (GaN) or silicon carbide (SiC) epitaxial wafer.
와이드 밴드갭(WBG) 반도체는 기존 소재보다 밴드갭이 더 넓어 반도체로서, 밴드갭이란 가전자대(valence band) 맨 위와 전도대(conduction band) 맨 아래 사이의 에너지 차이를 의미한다.Wide bandgap (WBG) semiconductors are semiconductors with a wider bandgap than conventional materials. The bandgap refers to the energy difference between the top of the valence band and the bottom of the conduction band.
이하, 본 발명의 설명에서는 실리콘 카바이드(SiC) 에피택셜 웨이퍼를 일 실시예로 하여 도 1과 함께 설명하기로 한다.Hereinafter, the present invention will be described using a silicon carbide (SiC) epitaxial wafer as an example, together with FIG. 1.
본 발명의 단계(S100)는 반도체 기판 검사면을 광학 현미경(Optical Microscopy(OM))으로 검사하여 표면 삼각결함을 탐색하는 단계이다.Step (S100) of the present invention is a step of examining a semiconductor substrate inspection surface using an optical microscope (Optical Microscopy (OM)) to search for surface triangular defects.
광학 현미경은 물체의 미세한 부분을 확대하여 관찰하는 광학 장치로, 반도체 기판 표면에 노출된 결함을 대면적으로 빠르게 검사하여 탐색할 수 있는 이점이 있다.An optical microscope is an optical device that magnifies and observes minute parts of an object, and has the advantage of being able to quickly inspect and explore defects exposed on the surface of a semiconductor substrate over a large area.
광학 현미경을 사용하여 SiC 에피택셜 웨이퍼를 관찰하는 경우, 일반적으로 에피택셜층의 표면에 초점을 맞추어 표면에 있는 결함을 관찰한다.When observing a SiC epitaxial wafer using an optical microscope, the focus is usually on the surface of the epitaxial layer to observe defects on the surface.
SiC 에피택셜 웨이퍼를 검사하는 방법은 상기 광학 현미경을 통한 표면 결함검사 이외에 XRT(X-ray topography), PL(Photoluminescence), 및 EBIC(Electron Beam Induced Current)를 통한 내부결함 검사를 하는 방법이 있다.In addition to surface defect inspection using the optical microscope described above, there are methods for inspecting SiC epitaxial wafers, including internal defect inspection using XRT (X-ray topography), PL (Photoluminescence), and EBIC (Electron Beam Induced Current).
도 6은 상기 각 방법에 의하여 SiC 에피택셜 웨이퍼를 검사한 사진으로서, 도 6a는 각 장비의 출력사진이고, 도 6b는 결함 부분을 표시한 사진이다.Fig. 6 is a photograph showing an SiC epitaxial wafer inspected using each of the above methods. Fig. 6a is an output photograph of each device, and Fig. 6b is a photograph showing a defective portion.
도 6에서 보여지는 바와 같이 광학 현미경에서 표면결함이 보여지지 않아도 내부결함이 존재함을 알 수 있다. As shown in Fig. 6, it can be seen that internal defects exist even though no surface defects are visible under an optical microscope.
이하, 삼각결함에 대하여 살펴보기로 한다.Below, we will look at the triangle defect.
SiC 에피택셜층의 삼각결함은 품질을 열화시키는 원인으로 알려져 있다. Triangular defects in SiC epitaxial layers are known to cause quality degradation.
SiC 에피택셜층의 삼각결함은 웨이퍼 표면에 남아있는 연마 흠집, 스텝 플로우 성장 중에 테라스에 형성되는 2차원 핵, 성장 초기의 과포화 상태일 때 기판과 에피택셜층의 계면에 형성되는 이종의 폴리타입의 결정핵, SiC막의 미소 파편 등 다양한 원인에 의하여 발생되는 것으로 연구되고 있다.Triangular defects in SiC epitaxial layers are being studied to be caused by various factors, including polishing scratches remaining on the wafer surface, two-dimensional nuclei formed on terraces during step flow growth, heterogeneous polytype crystal nuclei formed at the interface between the substrate and the epitaxial layer during supersaturation in the early stage of growth, and micro-fragments in the SiC film.
상기 삼각 결함(1)은 도 2에서 보여지는 바와 같이 스텝 플로우 성장 방향을 따라 삼각형의 정점(10)과 그 대변(20)이 순서대로 배열되는 방향을 향하여 형성되므로, SiC 에피택셜층의 성장과 함께 성장해 간다. The above triangle defect (1) is formed in the direction in which the vertex (10) and its opposite side (20) of the triangle are sequentially arranged along the step flow growth direction as shown in Fig. 2, and thus grows together with the growth of the SiC epitaxial layer.
따라서, 삼각결함(1)에는 도 2와 같이 성장방향(30)을 정의할 수 있다.Therefore, the growth direction (30) can be defined for the triangular defect (1) as shown in Fig. 2.
삼각결함(1)은 스텝 플로우 성장과 함께, 상기 기점을 삼각형의 정점(10)으로 하여, 대략 삼각형의 상사형을 유지하면서 그 면적을 크게 하도록 성장해 간다.The triangle defect (1) grows with step flow growth, with the starting point being the vertex of the triangle (10), and grows to increase its area while maintaining a roughly triangular shape.
따라서, 일반적으로 결함 기점이 SiC 에피택셜층의 성장 초기에 발생한 삼각 결함일수록 크기가 크므로, 삼각 결함(1)의 크기로부터 내면 기점의 깊이를 추측할 수 있다.Therefore, since the defect origin is generally a triangular defect that occurs in the early stage of growth of the SiC epitaxial layer, the size of the defect origin is larger, so the depth of the inner origin can be estimated from the size of the triangular defect (1).
본 발명의 단계(S100)는 광학 현미경(Optical Microscopy(OM))으로 삼각결함을 탐색하는 단계이므로 표면에 노출된 삼각결함을 찾는 단계가 된다.Step (S100) of the present invention is a step for searching for triangular defects using an optical microscope (Optical Microscopy (OM)), and thus becomes a step for finding triangular defects exposed on the surface.
본 발명의 단계(S300)는 도 3에서 보여지는 바와 같이 탐색된 표면 삼각결함의 성장방향(30)에 대하여 우측면에 위치하는 영역을 내부결함 예상영역(50)으로 설정하는 단계이다.Step (S300) of the present invention is a step of setting an area located on the right side with respect to the growth direction (30) of the surface triangular defects detected as shown in FIG. 3 as an internal defect prediction area (50).
이하 이에 대하여 도 3과 함께 상세히 살펴보기로 한다.Below, we will examine this in detail together with Fig. 3.
도 3a는 에피택셜층의 표면에 초점을 맞추어 삼각결함을 관찰한 광학 현미경사진이며, 도 3b는 PL, 도 3c은 XRT, 도 3b는 EBIC의 사진이다.Fig. 3a is an optical microscope photograph focusing on the surface of the epitaxial layer to observe triangular defects, Fig. 3b is a PL photograph, Fig. 3c is an XRT photograph, and Fig. 3b is an EBIC photograph.
도 3의 사진을 살펴보면, 도 6과 달리 표면 삼각결함(1)의 아래쪽에서 내부결함이 확산되는 것을 알 수 있다.Looking at the photo in Fig. 3, unlike Fig. 6, it can be seen that the internal defect spreads from below the surface triangular defect (1).
본 발명에서는 도 4의 삼각결함 아래쪽을 삼각결함의 성장방향(30) 우측면으로 정의한다.In the present invention, the lower part of the triangular defect in FIG. 4 is defined as the right side of the growth direction (30) of the triangular defect.
상기 삼각결함(1)의 성장방향(30)을 도 4와 함께 다시 한번 살펴보면 삼각결함 정점(10)에서 대변(20)으로 내린 제1 수선(30a)과 방향으로 정의할 수 있다.If we look at the growth direction (30) of the above triangle defect (1) again together with Fig. 4, it can be defined as the direction of the first perpendicular line (30a) drawn from the triangle defect vertex (10) to the opposite side (20).
즉, 삼각결함(1)의 성장방향은 마치 크기와 방향을 가지는 벡터로 해석할 수 있다.That is, the growth direction of the triangular defect (1) can be interpreted as a vector having a size and direction.
다시 도 3을 살펴보면 도 3a에서 광학 현미경으로 에피택셜 층 표면에 삼각결함이 발견되면, 도 3b, 도 3c, 도 3d에서 보여지는 바와 같이 에피택셜 층 내면에는 결함이 편방향으로 확산되어 있음을 알 수 있다.Looking at Figure 3 again, when a triangular defect is found on the surface of the epitaxial layer with an optical microscope in Figure 3a, it can be seen that the defect is spread in one direction inside the epitaxial layer as shown in Figures 3b, 3c, and 3d.
본 발명은 에피택셜 층 내면의 결함 확산이 발생되는 경우, 그 방향이 항상 편방향으로 형성되고, 그 편방향은 항상 상기 성장방향의 우측면인 것을 발견하고 이를 구체화시킨 것이다.The present invention has discovered and embodied that when defect diffusion occurs within an epitaxial layer, the direction is always formed in one direction, and that the one direction is always the right side of the growth direction.
따라서, 본 발명은 삼각결함 성장방향(30)의 우측면을 상기 내부결함 예상영역(50)으로 정의한다.Therefore, the present invention defines the right side of the triangular defect growth direction (30) as the internal defect expected area (50).
본 발명에서 상기 내부결함 예상영역(50)은 결함발생 확률로 표시할 수 있는데, 상기 삼각결함(1)에 인접할수록 결함발생 확률이 높은 것으로 평가하여 표시하고, 상기 제1 수선(30a) 중심에서 우측면 방향으로 수직하게 연장한 제2 수선(40)에 가까울 수록 결함발생 확률이 높은 것으로 평가하여 표시할 수 있다.In the present invention, the internal defect prediction area (50) can be expressed as a defect occurrence probability. The closer it is to the triangle defect (1), the higher the defect occurrence probability is evaluated and displayed, and the closer it is to the second perpendicular line (40) extending vertically from the center of the first perpendicular line (30a) toward the right side, the higher the defect occurrence probability is evaluated and displayed.
본 발명에서 상기 반도체 기판 검사면을 복수 개의 단위 검사영역으로 구획시키는 단계(S200);를 더 포함할 수 있는데, 이와 같은 경우 도 5에서 보여지는 바와 같이 표면에 결함이 없는 단위 검사영역(50a)이 형성된다.The present invention may further include a step (S200) of dividing the semiconductor substrate inspection surface into a plurality of unit inspection areas; in this case, as shown in FIG. 5, a unit inspection area (50a) having no defects on the surface is formed.
도 5는 내부결함 예상영역(50) 단위 검사영역 별로 결함발생 확률을 색상으로 표시한 일 실시예이다.Figure 5 is an example of displaying the probability of defect occurrence by color for each unit inspection area of the internal defect expected area (50).
이와 같은 결함발생확률은 일반적으로 숫자로 표기할 것이지만, 본 발명의 설명을 위하여 색상 표기한 것으로 본 발명의 기술적 취지에 이에 한정되는 것은 아니다.The probability of occurrence of a defect like this is generally expressed in numbers, but is expressed in color for the purpose of explaining the present invention and is not limited to this in the technical intent of the present invention.
도 5에서 보여지는 바와 같이 본 발명은 각 단위 검사영역에 도 5와 같이 결함발생 확률이 표시되어지므로, 단순 단위 검사영역만을 보았을 때 표면 결함이 없는 검사영역이더라도 내부결함 확률이 표기되어 내부결함에 대한 추가 조사를 안내하는 효과가 있다.As shown in Fig. 5, the present invention displays the probability of defect occurrence in each unit inspection area as shown in Fig. 5, so that even if there is no surface defect in an inspection area when only a simple unit inspection area is viewed, the probability of internal defects is displayed, thereby providing an effect of guiding further investigation into internal defects.
즉, 본 발명은 상기 결함예상 영역을 XRT(X-ray topography), PL(Photoluminescence) 및/또는 EBIC(Electron Beam Induced Current)의 타겟 검사영역으로 설정하여 내부결함 검사가 수행되게 하는 단계(S500)을 포함할 수 있다.That is, the present invention may include a step (S500) of performing an internal defect inspection by setting the above-mentioned defect prediction area as a target inspection area of XRT (X-ray topography), PL (Photoluminescence) and/or EBIC (Electron Beam Induced Current).
또한, 본 발명은 반도체 기판 검사면 전체에 결함예상 영역을 표시하여 결함예상 맵을 출력시키는 단계(S400)를 포함할 수 있는데, 이 경우, 도 5에서 보여지는 바와 같이 각 단위 검사영역에 결함발생 확률을 표시하고 이를 웨이퍼 전체 수준으로 확장하면 전체 결함예상 맵이 형성되게 된다.In addition, the present invention may include a step (S400) of displaying a defect prediction area on the entire inspection surface of a semiconductor substrate to output a defect prediction map. In this case, as shown in FIG. 5, when a defect occurrence probability is displayed in each unit inspection area and expanded to the entire wafer level, an entire defect prediction map is formed.
이상 본 발명의 설명을 위하여 도시된 도면은 본 발명이 구체화되는 하나의 실시예로서 도면에 도시된 바와 같이 본 발명의 요지가 실현되기 위하여 다양한 형태의 조합이 가능함을 알 수 있다.The drawings shown for the purpose of explaining the present invention are one embodiment in which the present invention is embodied, and it can be seen that various combinations of forms are possible in order to realize the gist of the present invention as shown in the drawings.
따라서 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와 같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다. Accordingly, the present invention is not limited to the above-described embodiments, and as claimed in the following claims, it is possible for anyone with ordinary skill in the art to make various modifications without departing from the spirit of the present invention, and it is said that the technical spirit of the present invention exists to the extent that it is possible to make various modifications without departing from the spirit of the present invention.
1 : 삼각결함
10 : 삼각결함 정점
20 : 삼각결함 대변
30 : 삼각결함 성장방향
30a : 제1 수선
40 : 제2 수선
50 : 내부결함 예상영역
50a : 단위 검사영역1: Triangular defect
10: Triangular defect vertex
20: Triangular defect
30: Triangular defect growth direction
30a: First waterline
40: Second repair
50: Expected internal defect area
50a: Unit inspection area
Claims (7)
반도체 기판 검사면을 Optical Microscopy(OM)로 검사하여 표면 삼각결함을 탐색하는 단계;
탐색된 표면 삼각결함의 성장방향에 대하여 우측면에 위치하는 영역을 내부결함 예상영역으로 설정하는 단계;
를 포함하여 이루어지는 것을 특징으로 하는
와이드 밴드갭 소재의 반도체 기판 검사 방법.
In a method for inspecting a semiconductor substrate of a wide bandgap material,
A step of detecting surface triangular defects by inspecting the semiconductor substrate inspection surface using Optical Microscopy (OM);
A step of setting an area located on the right side of the growth direction of the explored surface triangular defect as an expected internal defect area;
characterized by including
A method for inspecting semiconductor substrates made of wide bandgap materials.
상기 반도체 기판 검사면을 복수 개의 단위 검사영역으로 구획시키는 단계;
를 더 포함하여
표면 삼각결함의 성장방향에서 우측면에 위치하는 단위 검사영역들을 내부결함 예상영역으로 설정하는 것을 특징으로 하는
와이드 밴드갭 소재의 반도체 기판 검사 방법.
In paragraph 1
A step of dividing the semiconductor substrate inspection surface into a plurality of unit inspection areas;
Including more
It is characterized by setting the unit inspection areas located on the right side in the growth direction of the surface triangular defect as the expected internal defect area.
A method for inspecting semiconductor substrates made of wide bandgap materials.
갈륨나이트라이드(GaN) 또는 실리콘 카바이드(SiC) 에피택셜 웨이퍼인 것을 특징으로 하는
와이드 밴드갭 소재의 반도체 기판 검사 방법.
In the first paragraph, the semiconductor substrate
characterized by being a gallium nitride (GaN) or silicon carbide (SiC) epitaxial wafer.
A method for inspecting semiconductor substrates made of wide bandgap materials.
삼각결함에 인접할수록 결함발생 확률이 높은 것으로 평가하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법.
In the first paragraph, the internal defect expected area is
A method for inspecting a semiconductor substrate using a wide bandgap material, characterized in that the closer the material is to a triangular defect, the higher the probability of defect occurrence.
삼각결함 정점에서 대변으로 내린 제1 수선과 방향으로 정의하며,
상기 내부결함 예상영역은
상기 제1 수선의 중심에서 상기 성장방향의 우측면 방향으로 상기 제1 수선에 수직하게 연장한 제2 수선에 가까울 수록
결함발생 확률이 높은 것으로 평가하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법.
In the first paragraph, the growth direction of the triangular defect is
It is defined as the first perpendicular and direction from the vertex of the triangle to the opposite side,
The above internal defect expected area is
The closer it is to the second perpendicular line extending perpendicularly to the first perpendicular line in the right-hand direction of the growth direction from the center of the first perpendicular line,
A method for inspecting a semiconductor substrate made of a wide bandgap material characterized by being evaluated as having a high probability of defect occurrence.
반도체 기판 검사면에
결함예상 영역을 표시한 결함예상 맵을 출력시키는 단계를
더 포함하는 것을
특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법.
In paragraph 1
On the semiconductor substrate inspection surface
A step for outputting a defect prediction map that indicates the defect prediction area.
Including more
A method for inspecting a semiconductor substrate made of a wide bandgap material.
상기 결함예상 영역을
XRT(X-ray topography), PL(Photoluminescence) 및/또는 EBIC(Electron Beam Induced Current)의 타겟 검사영역으로 설정하여
내부결함 검사가 수행되게 하는 것을 특징으로 하는 와이드 밴드갭 소재의 반도체 기판 검사 방법.
In paragraph 1
The above defect prediction area
By setting the target inspection area for XRT (X-ray topography), PL (Photoluminescence) and/or EBIC (Electron Beam Induced Current)
A method for inspecting a semiconductor substrate made of a wide bandgap material, characterized in that an internal defect inspection is performed.
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| KR102268931B1 (en) | 2016-07-20 | 2021-06-23 | 토레이 엔지니어링 컴퍼니, 리미티드 | Defect Inspection Apparatus for Wide Gap Semiconductor Substrates |
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| KR102381348B1 (en) | 2020-10-29 | 2022-03-30 | 한국전기연구원 | Non-destructive analysis for TSD and TED defect of silicon carbide wafers |
| KR102567624B1 (en) | 2021-09-09 | 2023-08-16 | 한국전기연구원 | Silicon carbide crystal defect location analysis method using non-destructive analysis method and analysis device and computer program including the same |
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