KR20250078489A - Package-on-package (PoP) interconnect area with reduced capacitance to reduce impedance discontinuities. - Google Patents

Abstract

This paper describes devices and techniques for providing interconnections between packages to limit impedance discontinuities in the package-on-package (PoP) interconnect regions to reduce signal losses between the packages. The devices and techniques configure the PoP electrical and physical interconnect regions to reduce capacitance and impedance discontinuities in the interconnect.

Description

Package-on-package (PoP) interconnect area with reduced capacitance to reduce impedance discontinuities.

Signal transmission within and/or between semiconductor packages and other electronic devices can be impaired by impedance discontinuities caused by insertion loss, return loss, and/or cross-talk. Impedance discontinuities can occur either within the packages or at the interfaces between the packages. Within a package, signal line geometry and spacing can be adjusted to reduce impedance discontinuities within the package. However, impedance discontinuities at interconnections between packages may not be reduced in the same manner. Forming trace inductance coils in the signal lines adjacent to interconnection points can be used to reduce impedance discontinuities between packages. However, forming inductance coils consumes package space and may therefore increase cost or be impractical.

This paper describes devices and techniques for providing interconnections between packages to limit impedance discontinuities in the package-on-package (PoP) interconnection region to reduce signal losses between packages. The devices and techniques configure the PoP electrical and physical interconnection regions to reduce capacitance at these interconnections to reduce impedance discontinuities at the interconnection.

In various implementations, the PoP electrical and physical interconnection region on the package includes a conductive region and a non-conductive region. When the packages are joined by an interconnection structure (e.g., a solder ball having a non-conductive core), the interconnection structure physically and electrically interconnects the packages. At the same time, including the non-conductive region in the PoP interconnection region reduces the capacitance in the electrical connection between the PoP interconnection region and the interconnection structure, thereby reducing impedance discontinuities.

For example, a PoP device may include a top package, a bottom package, and an interconnection structure. The top package includes a first PoP electrical and physical interconnection region configured to enable top physical connection and top electrical connection between the top package and the bottom package through the interconnection structure. The first PoP interconnection region has a top conductive region and a top non-conductive region. The top conductive region is configured to enable signal transmission between the top package and the bottom package. The top non-conductive region is configured to provide a first reduced capacitance at the top electrical connection. The bottom package includes a second PoP electrical and physical interconnection region configured to enable bottom physical connection and bottom electrical connection between the bottom package and the top package through the interconnection structure. The second PoP interconnection region has a bottom conductive region and a bottom non-conductive region. The bottom conductive region is configured to enable signal transmission between the bottom package and the top package. The bottom non-conductive region is configured to provide a second reduced capacitance at the bottom electrical connection. The interconnect structure is configured to support physical and electrical connections between the first PoP interconnect region and the second PoP interconnect region. The first reduced capacitance and the second reduced capacitance limit impedance discontinuities of signals passing therebetween.

As another example, a method of interconnecting an upper package and a lower package includes forming a first PoP electrical and physical interconnection region on the upper package to enable upper physical connection and upper electrical connection. An upper conductive region is formed configured to enable signal transmission between the upper package and the lower package and to provide a first reduced capacitance at the upper electrical connection. A second PoP electrical and physical interconnection region is formed on the lower package to enable lower physical connection and lower electrical connection. The lower conductive region is formed to enable signal transmission between the lower package and the upper package, and a lower non-conductive region is formed to provide a second reduced capacitance at the lower electrical connection. The first PoP interconnection region is coupled to the second PoP interconnection region by an interconnection structure including a non-conductive portion and a conductive portion. An interconnection structure is disposed between the first PoP interconnection region and the second PoP interconnection region, and heat is applied to cause at least a conductive portion of the interconnection structure to fluidly couple with both the first PoP interconnection region and the second PoP interconnection region. Coupling of the PoP interconnection regions through the interconnection structure reduces impedance discontinuities of signal transmission with the first reduced capacitance and the second reduced capacitance, thereby enabling signal transmission between the upper package and the lower package.

This summary is provided to introduce PoP interconnect regions having conductive and non-conductive regions as further described below in the detailed description and drawings. This summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

Details of one or more aspects of devices and techniques for providing package-on-package (PoP) interconnect regions having conductive and non-conductive regions are described herein with reference to the drawings. Like numbers are used throughout the drawings to refer to similar features and components.
FIG. 1 is a cross-sectional view of PoP interconnect regions formed on upper and lower packages to be joined via an interconnect structure;
FIG. 2 is a cross-sectional view of the PoP interconnection regions of FIG. 1 joined by an interconnection structure;
FIG. 3 is a partial cutaway perspective view of the PoP interconnection regions and interconnection structures of FIG. 1;
FIG. 4 is a partial cutaway perspective view of the upper and lower packages having a plurality of PoP interconnect regions to be joined with a plurality of interconnect structures;
FIG. 5 is a perspective view of the upper and lower packages of FIG. 4 joined together via PoP interconnect regions and interconnect structures;
FIGS. 6A through 6C, FIGS. 7A through 7D, FIGS. 8A through 8C, and FIGS. 9A through 9C are schematic illustrations of different configurations of PoP interconnect regions having conductive and/or non-conductive regions;
FIGS. 10A to 10C, FIGS. 11A and 11B, and FIGS. 12A to 12C are cross-sectional views of examples of implementations of PoP interconnect regions joined by examples of interconnect structures;
FIG. 13 is a flow diagram of an exemplary method of joining upper and lower packages using PoP interconnect regions and interconnect structures as described with reference to FIGS. 1 to 12c; and
FIG. 14 is a flow diagram of an exemplary method for forming a PoP interconnection region as described with reference to FIGS. 1 to 12c.

outline

Computing devices and other electronic devices are continually becoming more powerful and smaller. The ever-increasing performance and ever-decreasing size of semiconductor devices and other packages help provide improved device power and reduced size. However, the ability to improve device power and reduce size also relies on both the ability to fit more packages into a compact volume and the ability to efficiently interconnect devices.

As previously described, it can be important to limit impedance discontinuities within and between packages to prevent signal loss. Also, as previously described, one technique used to reduce impedance discontinuities in connections between devices is to use inductance coils. These inductance coils can include multiple turns around the signal line and thus can consume a significant amount of space on the surface of the package. Thus, while inductance coils are useful, in increasingly compact and densely packed devices, it is not always practical to allocate package space to include inductance coils.

Meanwhile, the impedance discontinuity in the interconnection between the packages can be reduced by reducing the capacitance in the interconnection regions between the packages. According to the implementation examples described herein, the capacitance in the interconnection between the packages can be reduced by selectively configuring the electrical and physical interconnection regions on the packages.

In one exemplary implementation, package-on-package electrical and physical interconnect regions (PoP interconnect regions) of the package are configured to enable physical connection and electrical connection with another package via interconnect structures. The PoP interconnect regions each include a conductive region and a non-conductive region. The conductive region is configured to enable signal transmission between the package and another package. The interconnect structure, which may also include conductive structures and non-conductive structures, is coupled to the PoP interconnect regions to result in reduced capacitance in the PoP interconnect regions to reduce impedance discontinuities.

This document describes devices including PoP interconnect regions that reduce capacitance to reduce impedance discontinuities and techniques for forming and/or joining PoP interconnect regions having reduced capacitance. The devices and techniques may be useful for interconnecting packages within system-on-chip (SoC) devices with memory devices, for joining multiple memory and/or logic devices together, and for facilitating efficient signal transmission between these devices in other applications.

Exemplary devices

FIG. 1 illustrates a system (100) including PoP interconnect regions (120 and 140) that can be joined by interconnect structures (150). In the example of FIG. 1, the PoP interconnect regions (120 and 140) include conductive regions (122 and 142) and non-conductive regions (124 and 144), respectively. The PoP interconnect regions (120 and 140) can be joined by an interconnect structure (150) that includes a conductive structure (152) and a non-conductive structure (154). When interconnected as described below with reference to FIG. 2, the interconnect structure (150) electrically and physically connects the PoP interconnect regions (120 and 140).

More specifically, the upper package (110), which may include a semiconductor device, such as a memory device or a logic device, includes a bottom-facing surface (112) on which a first PoP interconnection region (120) is formed. The first PoP interconnection region (120) includes an upper conductive region (122) on a side of an upper conductive material (126) that is formed as part of the creation of the upper package (110). The first PoP interconnection region (120) also includes an upper non-conductive region (124) on the bottom-facing surface (112). The non-conductive region (124) may be on a side of an upper non-conductive material (128), which may include a body or substrate of the upper package (110). The upper conductive material (126) can be electrically and physically coupled to a first signal conductor (125) within the upper package (110) through which signals received by or transmitted from the upper conductive region (122) are conducted.

A lower package (130), which may also include a semiconductor device, such as a memory device or a logic device, includes a top-facing surface (132) having a second package-on-package interconnection region (140) (second PoP interconnection region (140)) formed thereon. The second PoP interconnection region (140) includes a lower conductive region (142) on a side of a lower conductive material (146) that is formed as part of the formation of the lower package (130). The second PoP interconnection region (140) also includes a lower non-conductive region (144) on a side of a upper non-conductive material (148), which may include a substrate or body of the lower package (130). The lower conductive material (146) may be electrically and physically coupled to a second conductor (145) within the lower package (130) through which signals received by or transmitted from the lower conductive region (142) are conducted.

As will be appreciated by those skilled in the art of package fabrication, conductive regions, such as conductive regions (122 and 142), may be formed by depositing a conductive material on a non-conductive substrate. Similarly, non-conductive regions, such as non-conductive regions (124 and 144), may be formed by removing a portion of conductive material previously deposited on a substrate.

The interconnect structure (150) connecting the PoP interconnect regions (120, 140) may have the properties of a solder ball. In the example of FIG. 1, the conductive structure (152) includes a conductive layer disposed over or around a non-conductive structure (154). The non-conductive structure (154) may include a core of the interconnect structure (150). In various implementations, the non-conductive structure (154) may be formed of an elastomer, such as a plastic. The use of such an elastomer and a plastic core provides a physical structure that supports the conductive structure (152) and facilitates physical connection of the upper package (110) and the lower package (130), as described further below.

FIG. 2 illustrates a system (200) in which PoP interconnect regions (120 and 140) are joined in their assembled form by an interconnect structure (250). In the assembled form of the interconnect structure (250), the conductive structure (252) and the non-conductive structure (254) have been deformed as part of the assembly process compared to the forms of the conductive structure (152) and the non-conductive structure (154) of the interconnect structure (150) of FIG. 1. As part of the assembly process, heat (not shown in FIG. 1 or FIG. 2) may be applied to the upper package (110), the lower package (130), and the interconnect structure (150) to induce flow of the conductive structure (152) and the non-conductive structure (154) of the interconnect structure (150). As heat is applied, the upper package (110) is moved relative to the lower package (130) (e.g., the upper package (110) is moved toward the lower package (130)), and the interconnect structure (150) is positioned between the first PoP interconnect region (120) and the second PoP interconnect region (140). Moving the upper package (110) and the lower package (130) together causes the interconnect structure (150) of FIG. 1 to be pressed therebetween, deforming the conductive structure (152) and the non-conductive structure (154) of the interconnect structure (150) into the form of the assembled form of the conductive structure (252) and the non-conductive structure (254) of the interconnect structure (250) as shown in FIG. 2. As a result, the conductive structure (252) and the non-conductive structure (254) of the interconnection structure (250) connect the first PoP interconnection region (120) and the second PoP interconnection region (140).

More specifically, the conductive structure (252) of the interconnection structure (250) forms electrical and physical connections between the upper conductive region (122) of the first PoP interconnection region (120) of the upper package (110) and the lower conductive region (142) of the second PoP interconnection region (140). The non-conductive structure (254) of the interconnection structure (150) also forms physical connections between the upper non-conductive region (124) of the first PoP interconnection region (120) of the upper package (110) and the lower non-conductive region (144) of the second PoP interconnection region (140). Including an upper non-conductive region (124), a lower non-conductive region (144), and a non-conductive structure (254) reduces the size of the electrical contact region between the upper non-conductive region (124) and the lower non-conductive region (144), thereby reducing the capacitance of this region. Reducing the capacitance can, among other effects, reduce reflection loss when signals are transmitted across these regions, thereby reducing impedance discontinuities and improving signal transmission.

FIG. 3 illustrates a perspective view and a partial cut-away view of a system (300) to illustrate first surfaces (315) and second surfaces (335) of a first PoP interconnection region (320) and a second PoP interconnection region (340) of an upper package (310) and a lower package (330), respectively. Similar to the example of FIG. 1, the PoP interconnection regions (320 and 340) include conductive regions (322 and 342) and non-conductive regions (324 and 344), respectively. In the example of FIG. 3, the first surface (315) of the first PoP interconnection region (320) is located on the bottom-facing surface (312) of the upper package (310). The upper conductive region (322) of the first PoP interconnection region (320) is a surface of the upper conductive material (326) disposed in the upper package (310). In the example of FIG. 3, the upper conductive region (322) surrounds the upper non-conductive region (324) included in the upper package (310). Correspondingly, the second surface (335) of the second PoP interconnection region (340) is located on the upper-facing surface (332) of the lower package (330). The lower conductive region (342) of the second PoP interconnection region (340) is a surface of the lower conductive material (346) disposed in the lower package (330). In the example of FIG. 3, the lower conductive region (342) surrounds the lower non-conductive region (344) included in the lower package (330).

In the example of FIG. 3, the upper conductive region (322) and the lower conductive region (342) are shaped like rings that surround the upper non-conductive region (324) and the lower non-conductive region (344), respectively. In this manner, when the packages (310 and 330) are assembled together, the conductive outer structure (352) of the interconnect structure (350) electrically and physically couples the rings of the upper conductive region (322) and the lower conductive region (342). The non-conductive structure (354) of the interconnect structure (350) physically couples the upper non-conductive region (324) and the lower non-conductive region (344) approximately at the center of the ring.

It should be understood that the depths of the upper conductive material (326), the upper non-conductive material (328), the lower conductive material (346), and the lower non-conductive material (348) as illustrated in FIG. 3 are for illustrative purposes and may not be to scale. Each of the upper conductive material (326), the upper non-conductive material (328), the lower conductive material (346), and the lower non-conductive material (348) have non-zero depths to facilitate their function, but need not extend to any particular depth within their respective packages (310 and 330).

FIG. 4 illustrates a system (400) including an upper package (410) having sets of first PoP interconnection regions (420 and 421) on a bottom-facing surface (412) of the upper package (410) and a lower package (430) having sets of second PoP interconnection regions (440 and 441) on a top-facing surface (432) of the lower package (430). A plurality of interconnect structures (450) are positioned between each of the sets of first PoP interconnection regions (420 and 421) and the sets of second PoP interconnection regions (440 and 441). To assemble the system (400), the upper package (410) and the lower package (430) are moved toward each other in relative directions (405 and 415), respectively, while heat (490) is introduced to induce flow within the interconnect structure (450).

FIG. 5 now illustrates an assembled system (500) having an upper package (410) coupled to a lower package (430) by deformed interconnect structures (550). The deformed interconnect structures (550) are at least partially deformed as a result of pressurizing the upper package (410) and the lower package (430) together to compress the interconnect structures (550) between the lower-facing surface (412) and the upper-facing surface (432) while heat (490) (FIG. 4) is applied, as previously described with reference to FIG. 2. The extent to which the interconnect structure (550) is deformed may depend on the deformability of the non-conductive structure (254) (FIG. 2), as further described below with reference to FIGS. 10A and 10B. Accordingly, the upper package (410) and the lower package (430) are electrically and physically coupled by interconnect structures (550) between the sets of first PoP interconnect regions (420 and 421) and the sets of second PoP interconnect regions (440 and 441), each of the interconnect structures within the sets (420, 421, 440, and 441) being coupled as described with reference to FIG. 3. The interconnect structures within the sets (420, 421, 440, and 441) are coupled in a manner that reduces capacitance at the interface to reduce impedance discontinuities for each of the electrical connections formed between the PoP interconnect structures within the groups (420, 421, 440, and 441).

FIGS. 6A-6C illustrate alternative PoP interconnection regions (600, 610, and 620) having different sized conductive regions (602, 612, and 622) and non-conductive regions (604, 614, and 624), respectively. Each of the alternative PoP interconnection regions (600, 610, and 620) may represent a first PoP interconnection region (120) of the upper package (110) or a second PoP interconnection region (140) of the lower package (130) of FIGS. 1-3 . Each of the PoP interconnection regions (600, 610, and 620) may include a conductive ring (605, 615, or 625). In each conductive ring (605, 615, and 625), the ring consists of a conductive region (602, 612, and 622) surrounding a non-conductive region (604, 614, and 624).

In particular, referring to FIG. 6A, since the conductive ring (605) is generally circular in shape, the relative sizes of the radii (606, 608) of the conductive region (602) and the non-conductive region (604), respectively, determine the relative sizes of the conductive region (602) and the non-conductive region (604), respectively. The relative sizes of the conductive region (602) and the non-conductive region (604), respectively, can be adjusted to change the capacitance of the PoP interconnection area (600).

For example, referring to FIG. 6b, the conductive region (612) of the PoP interconnection region (610) can have the same radius (606) as the conductive region (602) of the PoP interconnection region (600) of FIG. 6a. In contrast, the non-conductive region (614) of the PoP interconnection region (610) can have a larger radius (618) than the radius (608) of the non-conductive region (604) of the PoP interconnection region (600). As a result, the conductive ring (615) of the PoP interconnection region (610) is narrower than the conductive ring (605) of the PoP interconnection region (600) of FIG. 6a. A smaller area of the narrower conductive ring (615) will result in a PoP interconnect region (610) having a smaller capacitance than the conductive ring (605) of the PoP interconnect region (600) of FIG. 6a.

For another example, referring to FIG. 6c, the conductive region (622) of the PoP interconnection region (620) can have a larger radius (626) than the radius (606) of the conductive region (602) of the PoP interconnection region (600) of FIG. 6a. In contrast, the non-conductive region (624) of the PoP interconnection region (620) can have a smaller radius (628) than the radius (608) of the non-conductive region (604) of the PoP interconnection region (600) of FIG. 6a. As a result, the conductive ring (625) of the PoP interconnection region (620) is wider than the conductive ring (605) of the PoP interconnection region (600) of FIG. 6a. The larger area presented by the wider conductive ring (625) can reduce the resistance at the connection of the interconnect structure (not shown in FIG. 6c) and the PoP interconnect region (620). However, the wider conductive ring (625) of the PoP interconnect region (620) can also result in a larger capacitance than the PoP interconnect region (600) of FIG. 6a. Accordingly, the relative sizes of the conductive regions (602, 612, and 622) and the non-conductive regions (604, 614, and 624) of the PoP interconnect regions (600, 610, and 620), respectively, can be adjusted to provide desired electrical characteristics in the interconnect packages (not shown in FIGS. 6a-6c).

The PoP interconnect regions as described herein may not only have different ratios between their conductive and non-conductive areas, but may also be presented in different shapes. As described with reference to FIGS. 6A-6C , the PoP interconnect regions (600, 610, and 620) may be circular in shape. Further, referring to FIGS. 7A-7D , the PoP interconnect regions may include various multi-faceted shapes. Referring to FIG. 7A , the PoP interconnect region (700) may be rectangular or square in shape, and both the conductive region (702) and the non-conductive region (704) have four sides. Referring to FIG. 7B , the PoP interconnect region (710) may be triangular in shape, and both the conductive region (712) and the non-conductive region (714) have three sides. Referring to FIG. 7c, the PoP interconnect region (720) may have a hexagonal shape, and both the conductive region (722) and the non-conductive region (724) have six sides. It should be understood that there is no limitation to the number of sides that the conductive regions (702, 712, 722) and/or the non-conductive regions (704, 714, 724) may include.

Also, referring to FIG. 7d , it should be appreciated that the conductive region (732) and the non-conductive region (734) of the PoP interconnection region (730) may have different shapes. For example, the conductive region (732) may be rectangular or square in shape, while the non-conductive region (734) may be circular in shape (as shown in FIG. 7d ) or may include different multi-faceted shapes. The capacitance and other physical and electrical properties of the PoP interconnection region (730) may correlate with the relative areas of the conductive region (732) and the non-conductive region (734), even if the shapes of the conductive region (732) and the non-conductive region (734) are not identical.

Referring to FIGS. 8A-8C , in contrast to the PoP interconnection regions (600, 610, and 620) of FIGS. 6A-6C and the PoP interconnection regions (700, 710, 720, and 730) of FIGS. 7A-7D , the PoP interconnection regions (800, 810, and 820) may include conductive regions (802, 812, and 822) surrounded by non-conductive regions (804, 814, and 824). Considering examples of PoP interconnect regions (800, 810, and 820) as illustrated in FIGS. 8A-8C , the capacitance of the PoP interconnect regions (800, 810, and 820) may be correlated to the size of the conductive regions (802, 812, and 822) determined by their respective radii (806, 816, and 826), as described with reference to FIGS. 6A-6C .

The PoP interconnect regions having conductive regions surrounded by non-conductive regions need not include only circular conductive regions as described with reference to the examples of FIGS. 8A-8C . Referring to FIGS. 9A-9C , the PoP interconnect regions (900, 910, and 920) can include multi-sided conductive regions (902, 912, and 922), respectively. For example, the PoP interconnect region (900) includes a rectangular or square conductive region (902) having four sides. Referring to FIG. 9B , the PoP interconnect region (910) includes a triangular conductive region (912) having three sides. Referring to FIG. 9C , the PoP interconnect region (920) includes a hexagonal conductive region (922). It should be understood that there is no limitation on the number of sides that the conductive regions (902, 912, and 922) may include.

Various configurations of PoP interconnect regions and interconnect structures can be selected to determine desirable levels of capacitance and other electrical characteristics in the interconnect packages, as described with reference to FIGS. 10a through 12b.

Referring to FIGS. 10A-10C , systems (1000, 1002, and 1004) include PoP interconnect regions (1020 and 1040) having conductive regions (1022 and 1042) around non-conductive regions (1024 and 1044) as previously described with reference to FIGS. 1-4 and 6A-7C . In particular, referring to FIG. 10A, as described above, the capacitance of the PoP interconnect regions (1020 and 1040) in the electrical connection formed between the PoP interconnect regions (1020 and 1040) and the interconnect structure (1050) respectively is correlated to the relative sizes of the individual conductive regions (1022 and 1042) and the non-conductive regions (1024 and 1044) on the upper package (1010) and the lower package (1030). When the interconnect structure (1050) includes a conductive body (e.g., without a non-conductive core), the relative sizes of the non-conductive regions (1024 and 1044) are correlated to the capacitance in the electrical connection with the interconnect structure (1050). Similarly, and particularly with reference to FIG. 10b, where the interconnect structure (1051) includes both a conductive layer (1052) and a non-conductive core (1054), the non-conductive core (1054) may be constructed and/or sized from a rigid material so as not to block or interfere with contact between the conductive regions (1022, 1042) of the interconnect structure (1051) and the conductive layer (1052).

Referring to FIG. 10c, on the other hand, the interconnect structure (1053) may include a non-conductive core (1055) having a size and/or deformability such that the non-conductive core (1055) may partially block the electrical interconnection region between the conductive regions (1022 and 1042) of the interconnect structure (1053) and the conductive layer (1052). The non-conductive core (1055) may include a semi-rigid material configured to partially deform when pressed between the upper package (1010) and the lower package (1030). By partially blocking the electrical interconnection area between the conductive regions (1022 and 1042) of the interconnection structure (1053) and the conductive layer (1052), the non-conductive core (1055) can reduce the contact area between the conductive regions (1022 and 1042) of the interconnection structure (1053) and the conductive layer (1052), and thus change the capacitance or other electrical characteristics at the connection between the PoP interconnection regions (1020 and 1040).

The relative configuration of the interconnect structures can also affect electrical characteristics of the PoP interconnect regions that do not include conductive regions surrounding non-conductive regions. Referring to FIGS. 11A and 11B , the systems (1100 and 1102) of the upper and lower packages (1110 and 1130) include PoP interconnect regions (1120 and 1140) that include conductive regions (1122 and 1142) that do not surround non-conductive regions, as described with reference to FIGS. 8A-9C . The configuration of the interconnect structures (1150 and 1151) of FIGS. 11A and 11B can be varied to affect capacitance or other electrical characteristics. Referring to FIG. 11A , the interconnect structure (1150) includes a conductive body (e.g., without a non-conductive core); Therefore, the capacitance at the interconnection between the conductive regions (1122 and 1142) and the interconnection structure (1150) may be correlated with the sizes of the conductive regions (1122 and 1142) and the interconnection structure (1150).

In contrast, referring to FIG. 11B, the interconnect structure (1151) includes a conductive layer (1152) and a non-conductive core (1154). The non-conductive core (1154) may be composed and/or sized of a semi-rigid, deformable material such that the non-conductive core (1154) partially blocks the electrical interconnection region between the conductive regions (1122, 1142) of the interconnect structure (1151) and the conductive layer (1152). By partially blocking the electrical interconnection area between the conductive regions (1122 and 1142) of the interconnection structure (1151) and the conductive layer (1152), the non-conductive core (1154) can reduce the contact area between the conductive regions (1122 and 1142) and the conductive layer (1152) of the interconnection structure (1151), thereby changing the capacitance or other electrical characteristics at the connection between the PoP interconnection regions (1120 and 1140).

With reference to FIGS. 12A-12C , it should be emphasized that implementations of the PoP interconnection regions and interconnection structures described herein are not limited to symmetrical configurations. For example, in the system (1200) of FIG. 12A , the upper package (1210) may include a first PoP interconnection region (1220) that includes a conductive region (1222) that is different in size from a conductive region (1242) of a second PoP interconnection region (1240) of the lower package (1230) (potentially as a result of different sizes of the central non-conductive regions (1224 and 1244) within the conductive regions (1222 and 1242) of the PoP interconnection regions (1220 and 1240), respectively). As a result, the area of electrical contact between the PoP interconnect regions (1220 and 1240) across the interconnect structure (1250) may be different, resulting in different capacitances and/or different electrical characteristics in the connection with each of the PoP interconnect regions (1220 and 1240). Furthermore, when the interconnect structure (1250) includes a conductive layer (1252) and a non-conductive core (1254), the non-conductive core (1254) may affect the electrical connection area between the conductive layer (1252) and the conductive regions (1222 and 1242) differently.

Referring to FIG. 12b, in a system (1202) where the PoP interconnect regions (1221 and 1241) do not include non-conductive regions within their conductive regions (1223 and 1243), the conductive regions (1223 and 1243) may also be of different sizes to vary the capacitance or other electrical characteristics within each of the PoP interconnect regions (1221 and 1241). For example, the conductive region (1223) of the upper package (1212) may be smaller than the conductive region (1243) of the lower package (1232).

Referring to FIG. 12C, the system (1204) may include different types of PoP interconnection regions. For example, the first PoP interconnection region (1225) of the upper package (1214) may include a conductive region (1227) around a non-conductive region (1229), as described with reference to FIGS. 1-4 and 6A-7D. In contrast, the second PoP interconnection region (1245) of the lower package (1234) may not include a non-conductive region within the conductive region (1247), as described with reference to FIGS. 8A-9C. The differently configured PoP interconnection regions (1225 and 1245) may result in different capacitances and/or other electrical characteristics in the respective PoP interconnection regions (1225 and 1245).

Example method

Exemplary methods (1300 and 1400) are described with reference to FIGS. 13 and 14 , respectively, in accordance with one or more aspects of providing PoP interconnect regions having conductive and nonconductive regions that are bondable to each other as an interconnect structure to reduce capacitance in the PoP interconnect region to reduce impedance discontinuities. In general, methods (1300 and 1400) illustrate sets of operations (or actions) that may be performed in the order or combinations shown herein, but are not necessarily limited thereto. Furthermore, any one or more of the operations may be repeated, combined, reconfigured, omitted, or connected to provide a wide range of additional and/or alternative methods. In some of the following discussion, reference may be made to the devices or configurations of FIGS. 1-12C , by way of example only. The techniques and devices described in this disclosure are not limited to implementation or performance by one entity or multiple entities operating on one device or by those described with reference to the drawings.

FIG. 13 illustrates an exemplary method (1300) of interconnecting a top package and a bottom package using PoP interconnection regions on the packages as previously described with reference to FIGS. 1-12c. At block (1302), a first package-on-package electrical and physical interconnection region (a first PoP interconnection region) is formed on the top package to enable a top physical connection and a top electrical connection. Forming the top electrical connection includes forming a top conductive region configured to enable signal transmission between the top package and the bottom package. Forming the top physical connection includes forming a top non-conductive region configured to enable a first reduced capacitance in the top electrical connection. For example, the top package may include the top package (110) of FIG. 1 having a first PoP interconnection region (120) formed therein having a top conductive region (122) for forming the top electrical connection and a top non-conductive region (124) for forming a portion of the top physical connection.

At block (1304), a second package-on-package electrical and physical interconnection region (a first PoP interconnection region) is formed on the lower package to enable a lower physical connection and a lower electrical connection. The step of forming the lower electrical connection includes the step of forming a lower conductive region configured to enable signal transmission between the lower package and the upper package. The step of forming the lower physical connection includes the step of forming a lower non-conductive region configured to enable a second reduced capacitance in the lower electrical connection. For example, the lower package may include the lower package (130) of FIG. 1, and a second PoP interconnection region (140) is formed thereon, including a lower conductive region (142) for forming a lower electrical connection, a lower non-conductive region (144) for forming a portion of the lower physical connection, and a portion of the lower physical connection.

In block (1306), the first PoP interconnection region is coupled to the second PoP interconnection region by an interconnection structure including a non-conductive portion and a conductive portion. The step of coupling the first and second PoP interconnection regions includes the steps of disposing the interconnection structure between the first PoP interconnection region and the second PoP interconnection region, and applying heat to fluidize at least the conductive portion of the interconnection structure to couple with both the first PoP interconnection region and the second PoP interconnection region. The coupling of the PoP interconnection regions via the interconnection structure enables signal transmission between the upper package and the lower package having a first reduced capacitance at the upper electrical connection and a second reduced capacitance at the lower electrical connection, thereby reducing impedance discontinuities in the signal transmission. For example, FIGS. 4 and 5 illustrate joining the upper package (310) and the lower package (330) by electrically and physically interconnecting the PoP interconnect regions (420 and 421) on the upper package with the PoP interconnect regions (440 and 441) on the lower package via a plurality of interconnect structures (450). Moving the upper package (410) and the lower package (430) toward each other while applying heat (490) to induce flow within the interconnect structures (450) combines the packages (410 and 430) to form the combined system (500) of FIG. 5.

FIG. 14 illustrates an exemplary method (1400) for forming a package-on-package electrical and physical interconnect region (PoP interconnect region) on a first package for interconnection with a second package. At block (1402), in the PoP interconnect region, a non-conductive region is included on the first package and configured to support a physical connection between the first package and the second package via an interconnect structure between the first package and the second package. For example, FIG. 3 illustrates including an upper non-conductive region (324) on a first package in the form of an upper package (310) to couple and support an interconnect structure (350) to connect the upper package (310) to a second package in the form of a lower package (330).

In block (1404), a conductive region is formed on the first package around the non-conductive region. The conductive region is configured to provide an electrical connection to enable signal transmission between the first signal conductor of the first package and the second signal conductor of the second package, as illustrated by the first signal conductor (125) and the second signal conductor (145) being in electrical contact with the conductive regions (122 and 142) of the PoP interconnect regions (120 and 140), respectively. The reduced capacitance between the first package and the interconnect structure is correlated with the configuration of the conductive region and the non-conductive region when the interconnect structure is coupled with the PoP interconnect region, as previously described.

The preceding discussion describes devices and techniques for providing interconnections between packages to reduce capacitance in package-on-package (PoP) interconnections, thereby reducing impedance discontinuities and resulting signal losses between packages. These devices and techniques may be realized using one or more of the entities or components illustrated in FIGS. 1 through 14, which may be further segmented, combined, or otherwise. Thus, these drawings illustrate some of the many possible systems or devices that may employ the described techniques.

Unless the context dictates otherwise, the use of the word "or" herein may be construed as an "inclusive or," or the use of the term permitting the inclusion or application of more than one item joined by the word "or" (e.g., the phrase "A or B" could be interpreted to allow for just "A," just "B," or both "A" and "B"). Additionally, as used herein, the phrase referring to "at least one of" a list of items refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” can include a, b, c, a-, a-c, b-c, and a-b-c, as well as any combination of multiple of the same elements (e.g., a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Additionally, items depicted in the accompanying drawings and terminology discussed herein may represent one or more of the items or terms, and thus may be referenced interchangeably in the description herein with single or multiple forms of the items and terms.

Additional examples

Additional examples are provided in the following sections.

Example 1: A package-on-package device, comprising: an upper package; a lower package; and an interconnection structure, wherein the upper package comprises a first package-on-package electrical and physical interconnection region (a first PoP interconnection region), the first PoP interconnection region configured to enable upper physical connection and upper electrical connection between the upper package and the lower package through the interconnection structure, the first PoP interconnection region having an upper conductive region and an upper non-conductive region, the upper conductive region configured to enable signal transmission between the upper package and the lower package, and the upper non-conductive region configured to enable a first reduced capacitance in the upper electrical connection; The lower package includes a second package-on-package electrical and physical interconnection region (the second PoP interconnection region), the second PoP interconnection region is configured to enable a lower physical connection and a lower electrical connection between the lower package and the upper package via an interconnection structure, the second PoP interconnection region has a lower conductive region and a lower non-conductive region, the lower conductive region is configured to enable signal transmission between the lower package and the upper package, and the lower non-conductive region is configured to enable a second reduced capacitance in the lower electrical connection; and the interconnection structure is configured to support a physical connection and an electrical connection between the first PoP interconnection region and the second PoP interconnection region, the first reduced capacitance and the second reduced capacitance limiting impedance discontinuities of signals passing therebetween.

Example 2: The device of Example 1, wherein the upper conductive region surrounds the upper non-conductive region and the lower conductive region surrounds the lower non-conductive region.

Example 3: The device of Example 2, wherein the upper conductive region defines an upper ring surrounding the upper non-conductive region, and the lower conductive region defines a lower ring surrounding the lower non-conductive region.

Example 4: The device of Example 2, wherein the upper conductive region defines a first polyhedral shape surrounding the upper non-conductive region, and the lower conductive region defines a second polyhedral lower shape surrounding the lower non-conductive region.

Example 5: The device of Example 1, wherein the upper non-conductive region surrounds the upper conductive region and the lower non-conductive region surrounds the lower conductive region.

Example 6: The device of Example 5, wherein the upper non-conductive region defines an upper ring surrounding the upper conductive region, and the lower non-conductive region defines a lower ring surrounding the lower conductive region.

Example 7: The device of Example 5, wherein the upper non-conductive region defines a first polyhedral shape surrounding the upper conductive region, and the lower non-conductive region defines a second polyhedral lower shape surrounding the lower conductive region.

Example 8: A device according to any one of Examples 1 to 7, wherein the first reduced capacitance at the upper electrical connection is correlated to the relative sizes of the upper conductive region and the upper non-conductive region.

Example 9: A device according to any one of Examples 1 to 7, wherein the second reduced capacitance at the lower electrical connection is correlated to the relative sizes of the lower conductive region and the lower non-conductive region.

Example 10: The device of Example 1, wherein the interconnect structure includes a non-conductive structure and a conductive structure.

Example 11: The device of Example 10, wherein the non-conductive structure is configured to limit a first electrical interconnection region between the conductive structure and the upper electrical connection and a second electrical interconnection region between the conductive structure and the lower electrical connection.

Example 12: A device according to any one of Examples 10 and 11, wherein the non-conductive structure comprises a non-conductive core and the conductive structure comprises a conductive outer layer.

Example 13: The device of Example 12, wherein the non-conductive core comprises a rigid material.

Example 14: The device of Example 12, wherein the non-conductive core comprises an elastomer.

Example 15: The device of Example 14, wherein the elastomer comprises a plastic.

Example 16: The device of Example 10, wherein the interconnect structure includes solder balls.

Example 17: A package-on-package electrical and physical interconnection area (PoP interconnection area) device, comprising: a non-conductive region formed on a first package and configured to support a physical connection between the first package and the second package via an interconnection structure acceptable between the first package and the second package; and a conductive region formed on the first package adjacent the non-conductive region and configured to provide an electrical connection to enable signal transmission between a first conductor of the first package and a second conductor of the second package, wherein when the interconnection structure is coupled with the PoP interconnection area, reduced capacitance between the first package and the interconnection structure is correlated to the configurations of the conductive region and the non-conductive region.

Example 18: The device of Example 17, wherein the conductive region surrounds the non-conductive region.

Example 19: The device of Example 18, wherein the conductive region defines a ring surrounding the non-conductive region.

Example 20: The device of Example 18, wherein the conductive region defines a polyhedral shape surrounding the non-conductive region.

Example 21: A device according to any one of Examples 17 to 20, wherein the conductive region is configured to mate with a solder ball comprising a non-conductive core supporting the conductive layer, and the conductive region is configured to be electrically interlocked with the conductive layer.

Example 22: A method of interconnecting an upper package and a lower package, the method comprising: forming a first package-on-package electrical and physical interconnection region (first PoP interconnection region) on the upper package to enable upper physical connection and upper electrical connection; forming an upper conductive region configured to enable signal transmission between the upper package and the lower package and an upper non-conductive region configured to enable a first reduced capacitance in the upper electrical connection; forming a second package-on-package electrical and physical interconnection region (second PoP interconnection region) on the lower package to enable lower physical connection and lower electrical connection; forming a lower conductive region configured to enable signal transmission between the lower package and the upper package and a lower non-conductive region configured to enable a second reduced capacitance in the lower electrical connection; and a step of joining a first PoP interconnection region and a second PoP interconnection region using an interconnection structure including a non-conductive portion and a conductive portion; - a step of disposing the interconnection structure between the first PoP interconnection region and the second PoP interconnection region; and a step of applying heat to fluidize at least the conductive portion of the interconnection structure to join both the first PoP interconnection region and the second PoP interconnection region, thereby enabling signal transmission between the upper package and the lower package having a first reduced capacitance at the upper electrical connection and a second reduced capacitance at the lower electrical connection, thereby reducing impedance discontinuities in the signal transmission.

Example 23: The method of Example 22, further comprising the steps of forming an upper conductive region in a first region on the upper package around the upper non-conductive region, and forming a lower conductive region in a second region on the lower package around the lower non-conductive region.

Example 24: The method of Example 23, further comprising the steps of forming an upper conductive region in a first ring shape surrounding an upper non-conductive region, and forming a lower conductive region in a second ring shape surrounding a lower non-conductive region.

Example 25: The method of Example 23, further comprising the steps of forming an upper conductive region with a first polyhedral shape surrounding an upper non-conductive region, and forming a lower conductive region with a second polyhedral shape surrounding a lower non-conductive region.

Example 26: A method according to any one of Examples 22 to 25, further comprising the step of providing an interconnection structure as a solder ball including a conductive structure and a non-conductive structure.

Example 27: The method of Example 26, further comprising the step of providing a solder ball having a conductive structure including a layer formed around a non-conductive structure.

Example 28: The method of Example 27, further comprising the step of providing the non-conductive structure as an elastomeric core of the solder ball.

Example 29: The method of Example 28, further comprising the step of providing the elastomeric core as a plastic core.

Example 30: A method of forming a package-on-package electrical and physical interconnection region (PoP interconnection region) on a first package for interconnection with a second package, the method comprising: including a non-conductive region within the PoP interconnection region on the first package to support a physical connection between the first package and the second package via an interconnection structure between the first package and the second package; and forming a conductive region on the first package around the non-conductive region, the conductive region configured to provide an electrical connection enabling signal transmission between a first signal conductor of the first package and a second signal conductor of the second package, wherein a reduced capacitance between the first package and the interconnection structure when the interconnection structure is coupled with the PoP interconnection region is correlated with the configuration of the conductive region and the non-conductive region when the interconnection structure is coupled with the PoP interconnection region.

conclusion

Although embodiments of interconnections between packages to reduce capacitance in a package-on-package (PoP) interconnection and thereby reduce impedance discontinuities and resulting signal losses between packages have been described in specific language with respect to specific features and/or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary embodiments of implementing interconnections between packages to reduce capacitance in a PoP interconnection.

Claims (15)

As a package-on-package device,
upper package;
subpackages; and
Contains an interconnection structure,
The above upper package,
A first package-on-package electrical and physical interconnection region (a first PoP interconnection region), wherein the first PoP interconnection region is configured to enable a top physical connection and a top electrical connection between the upper package and the lower package through the interconnection structure, the first PoP interconnection region having a top conductive region and a top non-conductive region, the top conductive region being configured to enable signal transmission between the upper package and the lower package, and the top non-conductive region being configured to enable a first reduced capacitance in the top electrical connection;
The above sub-packages are,
A second package-on-package electrical and physical interconnection region (second PoP interconnection region), wherein the second PoP interconnection region is configured to enable a bottom physical connection and a bottom electrical connection between the lower package and the upper package through the interconnection structure, the second PoP interconnection region having a bottom conductive region and a bottom non-conductive region, the bottom conductive region being configured to enable signal transmission between the lower package and the upper package, and the bottom non-conductive region being configured to enable a second reduced capacitance in the bottom electrical connection; and
A package-on-package device, wherein the interconnect structure is configured to support physical connection and electrical connection between the first PoP interconnection region and the second PoP interconnection region, wherein the first reduced capacitance and the second reduced capacitance limit impedance discontinuities of signals passing therebetween. A package-on-package device in claim 1, wherein the upper conductive region surrounds the upper non-conductive region, and the lower conductive region surrounds the lower non-conductive region. A package-on-package device in the second aspect, wherein the upper conductive region defines an upper ring surrounding the upper non-conductive region, and the lower conductive region defines a lower ring surrounding the lower non-conductive region. A package-on-package device in the second aspect, wherein the upper conductive region defines a first polyhedral shape surrounding the upper non-conductive region, and the lower conductive region defines a second polyhedral lower shape surrounding the lower non-conductive region. A package-on-package device in claim 1, wherein the upper non-conductive region surrounds the upper conductive region, and the lower non-conductive region surrounds the lower conductive region. A package-on-package device in claim 5, wherein the upper non-conductive region defines an upper ring surrounding the upper conductive region, and the lower non-conductive region defines a lower ring surrounding the lower conductive region. A package-on-package device in claim 5, wherein the upper non-conductive region defines a first polyhedral shape surrounding the upper conductive region, and the lower non-conductive region defines a second polyhedral lower shape surrounding the lower conductive region. A package-on-package device according to any one of claims 1 to 7, wherein the first reduced capacitance at the upper electrical connection is correlated to the relative sizes of the upper conductive region and the upper non-conductive region. A package-on-package device according to any one of claims 1 to 7, wherein the second reduced capacitance at the lower electrical connection is correlated to the relative sizes of the lower conductive region and the lower non-conductive region. A package-on-package device in claim 1, wherein the interconnection structure includes a non-conductive structure and a conductive structure. A package-on-package device in claim 10, wherein the non-conductive structure is configured to limit a first electrical interconnection area between the conductive structure and the upper electrical connection and a second electrical interconnection area between the conductive structure and the lower electrical connection. A package-on-package device according to any one of claims 10 and 11, wherein the non-conductive structure comprises a non-conductive core, and the conductive structure comprises a conductive outer layer. A package-on-package device in claim 12, wherein the non-conductive core comprises a rigid material. A package-on-package device in claim 12, wherein the non-conductive core comprises an elastomer. A package-on-package device in claim 10, wherein the interconnection structure includes a solder ball.

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