KR20250044608A - Semiconductor memory device and the fabricating method including the same - Google Patents

Abstract

A method for manufacturing a semiconductor memory device with improved reliability is provided. The method for manufacturing a semiconductor memory device includes forming a stacked structure in which a plurality of semiconductor films and a plurality of sacrificial films are alternately stacked on a substrate including a cell region and a pad region, forming a plurality of buried insulating films penetrating the stacked structure, extending in a first direction, and spaced apart from each other in a second direction intersecting the first direction, forming a pre-active pattern separation structure penetrating the stacked structure and extending in the second direction on the cell region to separate each semiconductor film into a plurality of active patterns, wherein the pre-active pattern separation structure includes a pre-separation filling film including a metal material, and a separation liner disposed between the stacked structure and the pre-separation filling film, forming a first trench exposing a sidewall of the stacked structure by removing a portion of the buried insulating film, removing the sacrificial layer to expose an upper surface and a bottom surface of the active pattern, and performing a trimming process on the active pattern to reduce a thickness of the active pattern.

Description

SEMICONDUCTOR MEMORY DEVICE AND THE FABRICATING METHOD INCLUDING THE SAME

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor memory device with improved electrical characteristics and a method for manufacturing the same.

In order to meet the superior performance and low price demands of consumers, the integration of semiconductor devices is required to increase. In the case of semiconductor devices, the integration is an important factor in determining the price of the product, so increased integration is particularly required.

In the case of conventional two-dimensional or planar semiconductor devices, the integration is mainly determined by the area occupied by the unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required to miniaturize the pattern, the integration of two-dimensional semiconductor devices is still limited, although increasing. Accordingly, three-dimensional semiconductor memory devices having memory cells arranged three-dimensionally are being proposed.

The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor memory device with improved reliability.

Another problem that the present invention seeks to solve is to provide a semiconductor memory device with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to some embodiments of the technical idea of the present invention for solving the above problems, a method for manufacturing a semiconductor memory device includes forming a stacked structure in which a plurality of semiconductor films and a plurality of sacrificial films are alternately stacked on a substrate including a cell region and a pad region, forming a plurality of buried insulating films penetrating the stacked structure, extending in a first direction, and spaced apart from each other in a second direction intersecting the first direction, forming a pre-active pattern separation structure penetrating the stacked structure and extending in the second direction on the cell region to separate each semiconductor film into a plurality of active patterns, wherein the pre-active pattern separation structure includes a pre-separation filling film including a metal material, and a separation liner disposed between the stacked structure and the pre-separation filling film, forming a first trench exposing a sidewall of the stacked structure by removing a portion of the buried insulating film, exposing a top surface and a bottom surface of the active pattern by removing the sacrificial layer, and performing a trimming process on the active pattern to reduce a thickness of the active pattern.

According to some embodiments of the technical idea of the present invention for solving the above other problems, a semiconductor memory device comprises: a substrate including a cell region and a pad region, a plurality of first active patterns arranged on the cell region, arranged in a first direction, and including first sidewalls and second sidewalls opposite to a second direction intersecting with the first direction, a plurality of second active patterns arranged on the first active patterns and arranged in the first direction, a bit line arranged on the first sidewalls of the first active patterns, connected to the first active patterns, and extending in a third direction intersecting the first and second directions, a data storage pattern arranged on the second sidewalls of the first active patterns and connected to the first active patterns, a first word line arranged on the cell region, intersecting the first active pattern, and extending in the first direction, a second word line arranged on the first word line, intersecting the second active pattern, and extending in the first direction, a first word line pad arranged on the pad region, connected to the first word line, and extending in the first direction, a second word line and A second word line pad is connected and extends in a first direction, and a pad supporter penetrating the first word line pad and the second word line pad, wherein the pad supporter includes a supporter filling film including a metal material, and a supporter liner disposed between the first word line pad and the supporter filling film and between the second word line pad and the supporter filling film.

Other specific details of the present invention according to some embodiments of the technical idea of the present invention for solving the above problems are included in the detailed description and drawings.

FIG. 1 is a block diagram illustrating a semiconductor memory device according to some embodiments.
FIG. 2 is a circuit diagram for explaining the semiconductor memory device of FIG. 1.
FIG. 3 is a perspective view illustrating a semiconductor memory device according to some embodiments.
FIG. 4 is a perspective view for explaining the cell structure of the semiconductor memory device of FIG. 3.
FIG. 5 is a layout diagram for explaining the semiconductor memory device of FIG. 3.
Figure 6 is a cross-sectional view taken along line AA of Figure 5.
Figure 7 is a cross-sectional view taken along line BB of Figure 5.
Fig. 8 is a cross-sectional view taken along line CC of Fig. 5.
Fig. 9 is a cross-sectional view taken along DD of Fig. 5.
FIGS. 10 to 53 are intermediate step drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments.

In this specification, although the terms first, second, etc. are used to describe various elements or components, it is to be understood that these elements or components are not limited by these terms. These terms are merely used to distinguish one element or component from another element or component. Accordingly, it is to be understood that a first element or component mentioned below may also be a second element or component within the technical concept of the present invention.

FIG. 1 is a block diagram illustrating a semiconductor memory device according to some embodiments. FIG. 2 is a circuit diagram illustrating the semiconductor memory device of FIG. 1.

Referring to FIGS. 1 and 2, a semiconductor memory device according to some embodiments may include a memory cell array (1), a row decoder (2), a sense amplifier (3), a column decoder (4), and control logic (5).

A memory cell array (1) may include a plurality of memory cells (MC), a plurality of word lines (WL), and a plurality of bit lines (BL).

A plurality of memory cells (MC) can be arranged three-dimensionally along first to third directions (D1, D2, D3) intersecting each other. Memory cells (MC) adjacent to each other in the first direction (D1) can have a structure symmetrical to each other. Word lines (WL) and bit lines (BL) can intersect each other. One memory cell (MC) can be arranged between one word line (WL) and one bit line (BL). One memory cell (MC) can be connected to one word line (WL) and one bit line (BL), respectively.

Each memory cell (MC) may include a cell transistor (CTR) and a data storage element (DS). The cell transistor (CTR) and the data storage element (DS) may be electrically connected in series. The memory cell (MC) may be, for example, a dynamic random access memory (DRAM).

A cell transistor (CTR) may include a gate electrode, a channel, and source/drain terminals. The gate electrode of the cell transistor (CTR) may be connected to a word line (WL). The source/drain terminals of the cell transistor (CTR) may be connected to a bit line (BL) and a data storage element (DS), respectively. In some embodiments, the cell transistor (CTR) may have a gate-all-around transistor structure in which the gate electrode surrounds the channel.

The data storage element (DS) may be a capacitor or a variable resistor. When the data storage element (DS) is a capacitor, the data storage elements (DS) of memory cells (MC) adjacent to each other in the first direction (D1) may share a plate electrode (PE). When the data storage element (DS) is a variable resistor, the data storage element (DS) may include a variable resistance pattern that can be switched between two resistance states by an electrical pulse.

The plurality of word lines (WL) may be conductive patterns (e.g., metallic conductive lines) that are stacked in a third direction (D3). Each word line (WL) may extend in the second direction (D2). Adjacent word lines (WL) may be spaced apart from each other in the third direction (D3).

The plurality of bit lines (BL) may be conductive patterns (e.g., metallic conductive lines) extending in a third direction (D3). The plurality of bit lines (BL) may be arranged in a second direction (D2). Adjacent bit lines (BL) may be spaced apart from each other in the second direction (D2).

The row decoder (2) decodes an address input from the outside and can select one of the word lines (WL) of the memory cell array (1). The address decoded by the row decoder (2) can be provided to a row driver (not shown), and the row driver can provide a predetermined voltage to the selected word line (WL) and the unselected word lines (WL) in response to the control of the control circuits.

The sense amplifier (3) can detect and amplify the voltage difference between the selected bit line (BL) and the reference bit line according to the address decoded from the column decoder (4) and output it.

The column decoder (4) can provide a data transmission path between the sense amplifier (3) and an external device (e.g., a memory controller). The column decoder (4) can decode an address input from the outside and select one of the bit lines (BL). The control logic (5) can generate control signals that control operations of writing or reading data into the memory cell array (1).

FIG. 3 is a perspective view for explaining a semiconductor memory device according to some embodiments. FIG. 4 is a perspective view for explaining a cell structure of the semiconductor memory device of FIG. 3. FIG. 5 is a layout diagram for explaining the semiconductor memory device of FIG. 3. FIG. 6 is a cross-sectional view taken along line A-A of FIG. 5. FIG. 7 is a cross-sectional view taken along line B-B of FIG. 5. FIG. 8 is a cross-sectional view taken along line C-C of FIG. 9 is a cross-sectional view taken along line D-D of FIG. 5.

Referring to FIGS. 3 to 9, a semiconductor memory device according to some embodiments may include a first substrate (100), a cell structure (CS), and a peripheral circuit structure (PS).

The first substrate (100) may be bulk silicon or a silicon-on-insulator (SOI). Alternatively, the first substrate (100) may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the first substrate (100) is described as a substrate including silicon.

The first direction (D1) and the second direction (D2) may be directions parallel to the upper surface of the first substrate (100). The third direction (D3) may be a direction perpendicular to the upper surface of the first substrate (100).

The first substrate (100) may include a cell area (CA) and a pad area (EA). The cell area (CA) may be an area where a word line (WL) and a channel separation structure (APS) are arranged. The pad area (EA) may be an area where a word line pad (WP) and a pad supporter (WPS) are arranged.

The cell area (CA) and the pad area (EA) can be arranged alternately along the second direction (D2). The cell area (CA) can be arranged between adjacent pad areas (EA). The pad area (EA) can extend from the cell area (CA) in the second direction (D2).

The cell structure (CS) may include a memory cell array (1 in FIG. 1) described using FIGS. 1 and 2. The cell structure (CS) may include a plurality of active patterns (ACTs), a plurality of active pattern separation structures (APSs), a plurality of word lines (WLs), a plurality of bit lines (BLs), a data storage pattern (CAP), a plurality of word line pads (WPs), a plurality of pad supports (WPSs), a plurality of word line contacts (WCs), a first wiring structure (135), and a first bonding pad (139).

A plurality of active patterns (ACTs) can be arranged on a first substrate (100). A plurality of active patterns (ACTs) can be arranged on a cell area (CA).

A plurality of active patterns (ACTs) can be arranged in a grid shape along the first to third directions (D1, D2, D3). Active patterns (ACTs) located at the same level can be arranged in a grid shape along the first and second directions (D1, D2).

For example, the plurality of active patterns (ACT) may include a plurality of first active patterns (ACT1) and a plurality of second active patterns (ACT2) located at different levels. The first active patterns (ACT1) and the second active patterns (ACT2) may be spaced apart from each other in a third direction (D3). The first active patterns (ACT1) and the second active patterns (ACT2) may overlap each other in the third direction (D3). The plurality of first active patterns (ACT1) may be arranged in a grid shape along the first and second directions (D1, D2). The plurality of second active patterns (ACT2) may be arranged in a grid shape along the first and second directions (D1, D2).

Each active pattern (ACT) may have a line shape or a bar shape extending in a first direction (D1). Each active pattern (ACT) may include a first end, a second end, and a center. The first end of the active pattern (ACT) and the second end of the active pattern (ACT) may be opposite each other in the first direction (D1). The center of the active pattern (ACT) may be positioned between the first end of the active pattern (ACT) and the second end of the active pattern (ACT).

The first end and the second end of the active pattern (ACT) may include a first impurity region and a second impurity region, respectively. The first and second impurity regions may be regions in the active pattern (ACT) doped with impurities. The first and second impurity regions may have an n-type or p-type conductivity. The first and second impurity regions may be source/drain terminals of a cell transistor (CTR of FIG. 1) described using FIG. 1 and FIG. 2, respectively.

The center of the active pattern (ACT) may include a channel region. The channel region may be a channel of a cell transistor (CTR of FIG. 1) described using FIGS. 1 and 2.

Each active pattern (ACT) can include a first sidewall (ACT_SW1) and a second sidewall (ACT_SW2) that are opposite to each other in the first direction (D1). A first end of the active pattern (ACT) can include the first sidewall (ACT_SW1) of the active pattern (ACT). A second end of the active pattern (ACT) can include the second sidewall (ACT_SW2) of the active pattern (ACT).

The active pattern (ACT) can include at least one of silicon, germanium, silicon-germanium, an oxide semiconductor, and a two-dimensional material. The oxide semiconductor can be, for example, indium gallium zinc oxide (IGZO). The two-dimensional material can be, for example, MoS2, WS2, MoSe2, or WSe2.

A plurality of active pattern separation structures (APS) may be arranged on a first substrate (100). The plurality of active pattern separation structures (APS) may be arranged on a cell area (CA). The plurality of active pattern separation structures (APS) may be arranged in a lattice shape along the first and second directions (D1, D2).

An active pattern separation structure (APS) can be arranged between adjacent active patterns (ACT) in a second direction (D2). The active pattern separation structure (APS) can be arranged between adjacent first active patterns (ACT1) in the second direction (D2) and between adjacent second active patterns (ACT2) in the second direction (D2).

The active pattern separation structure (APS) can extend in a third direction (D3). The active pattern separation structure (APS) can overlap the active patterns (ACT) stacked in the third direction (D3) in a second direction (D2). For example, the active pattern separation structure (APS) can overlap the first active pattern (ACT1) and the second active pattern (ACT2) in the second direction (D2).

Each active pattern separation structure (APS) may include a separation liner (151), a separation filling film (152), and a separation capping film (153). The separation liner (151) may be disposed on the first substrate (100). The separation filling film (152) may be disposed on the separation liner (151). The separation capping film (153) may be disposed on the separation filling film (152). Although not shown, the separation liner (151) may be disposed between the active pattern (ACT) and the separation filling film (152).

The separation liner (151), the separation filling film (152), and the separation capping film (153) may each include an insulating material. The separation liner (151), the separation filling film (152), and the separation capping film (153) may each include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN).

The separation liner (151) may include an insulating material different from that of the separation peeling film (152). For example, the separation liner (151) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN), and the separation peeling film (152) may include silicon oxide (SiO ₂ ).

The separation liner (151) may include the same insulating material as the separation capping film (153). For example, both the separation liner (151) and the separation capping film (153) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN).

An interlayer insulating film (ILD) may be disposed between adjacent active patterns (ACT) in a third direction (D3). The interlayer insulating film (ILD) may be disposed between adjacent active pattern separation structures (APS) in a second direction (D2). The interlayer insulating film (ILD) may include an insulating material. The interlayer insulating film (ILD) may include, for example, silicon oxide.

A plurality of word lines (WL) may be arranged on a first substrate (100). The plurality of word lines (WL) may be arranged on a cell area (CA). The plurality of word lines (WL) may be arranged in a grid shape along the first and third directions (D1, D3).

The word lines (WL) may be stacked in a third direction (D3). For example, the plurality of word lines (WL) may include a first word line (WL1) and a second word line (WL2) located at different levels. The first word line (WL1) and the second word line (WL2) may be spaced apart from each other in the third direction (D3). The word lines (WL) located at the same level may be spaced apart from each other in the first direction (D1).

Each word line (WL) may have a line shape or a bar shape extending in the second direction (D2). The word line (WL) may intersect active patterns (ACT) located at the same level. For example, the first word line (WL1) may be located at the same level as the first active patterns (ACT1). The first word line (WL1) may intersect the first active patterns (ACT1). The second word line (WL2) may be located at the same level as the second active patterns (ACT2). The second word line (WL2) may intersect the second active patterns (ACT2). In some embodiments, the word line (WL) may surround the center of the active patterns (ACT) and extend in the second direction (D2).

The width of the word line (WL) in the first direction (D1) may be smaller than the width of the active pattern (ACT) in the first direction (D1).

The word line (WL) may include a conductive material. For example, the word line (WL) may include, but is not limited to, at least one of a doped semiconductor material (e.g., doped silicon, doped silicon-germanium, doped germanium), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a metal (e.g., tungsten, titanium, tantalum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide).

A gate insulating film (GI) may be disposed between a word line (WL) and an active pattern (ACT). The gate insulating film (GI) may surround the active pattern (ACT). The gate insulating film (GI) may include an insulating material. The gate insulating film (GI) may include, for example, silicon oxide.

A first gate separator (GS1) may be disposed between a word line (WL) and a gate insulating film (GI). The first gate separator (GS1) may be disposed between the word line (WL) and an active pattern separation structure (APS). The first gate separator (GS1) may extend in a third direction (D3) along a sidewall of the active pattern separation structure (APS).

The first gate separator (GS1) may include an insulating material. The first gate separator (GS1) may include, for example, silicon nitride.

A second gate separator (GS2) may be arranged between adjacent word lines (WL) in the third direction (D3). The second gate separator (GS2) may include an insulating material. The second gate separator (GS2) may include, for example, silicon oxide.

The first gate separator (GS1) and the second gate separator (GS2) may include different insulating materials. For example, the first gate separator (GS1) may include silicon nitride, and the second gate separator (GS2) may include silicon oxide.

A gate capping film (GCP) may be disposed between a gate insulating film (GI) and a second gate separator (GS2). A word line (WL) may be disposed between the gate capping film (CGP) and the first gate separator (GS1). The gate capping film (GCP) may include an insulating material. The gate capping film (GCP) may include, for example, silicon nitride.

A plurality of bit lines (BL) may be arranged on a first substrate (100). The plurality of bit lines (BL) may be arranged on a cell area (CA). The plurality of bit lines (BL) may be arranged in a grid shape along the first and second directions (D1, D2).

Each bit line (BL) may have a line shape or a pillar shape extending in the third direction (D3). The bit line (BL) may be electrically connected to active patterns (ACT) stacked in the third direction (D3). For example, one bit line (BL) may be electrically connected to a first active pattern (ACT1) and a second active pattern (ACT2).

The bit line (BL) may be arranged on a first sidewall (ACT_SW1) of the active pattern (ACT). The bit line (BL) may be connected to a first end of the active pattern (ACT).

A gate insulating film (GI), a first gate separator (GS1), and a second gate separator (GS2) may be disposed between a bit line (BL) and an interlayer insulating film (ILD). A gate capping film (GCP) may be disposed between a bit line (BL) and a word line (WL).

The bit line (BL) may include a conductive material. The bit line (BL) may include, for example, but is not limited to, at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

A plurality of cell embedded insulating films (CBIs) can be arranged on a first substrate (100). The plurality of cell embedded insulating films (CBIs) can be spaced apart from each other in a first direction (D1). Each cell embedded insulating film (CBI) can extend in a second direction (D2).

A cell embedded insulation film (CBI) can be arranged between adjacent bit lines (BL) in a second direction (D2). The cell embedded insulation film (CBI) can extend along a sidewall of the bit line (BL) in a third direction (D3).

The cell buried insulation (CBI) may include an insulating material. The cell buried insulation (CBI) may include, for example, silicon oxide.

A data storage pattern (CAP) may be placed on a first substrate (100). The data storage pattern (CAP) may be placed on a cell area (CA).

Data storage patterns (CAPs) can be arranged between adjacent bit lines (BLs) in the first direction (D1), between adjacent word lines (WLs) in the first direction (D1), and between adjacent active patterns (ACTs) in the first direction (D1).

An active pattern (ACT) and a word line (WL) may be arranged between a data storage pattern (CAP) and a bit line (BL). An active pattern separation structure (APS) may be arranged between the data storage pattern (CAP) and the word line (WL).

The data storage pattern (CAP) can be arranged on the second sidewall (ACT_SW2) of the active pattern (ACT). The data storage pattern (CAP) can be connected to the second end of the active pattern (ACT).

A data storage pattern (CAP) may include a plurality of storage electrodes (SE), capacitor dielectric films (CILs), and plate electrodes (PEs). Each of the storage electrodes (SEs), capacitor dielectric films (CILs), and plate electrodes (PEs) may form a data storage element (DS of FIG. 1) described using FIGS. 1 and 2.

A plurality of storage electrodes (SE) can be arranged along the first to third directions (D1, D2, D3). Each of the storage electrodes (SE) is spaced apart from each other. Each of the storage electrodes (SE) can be arranged on the second sidewall (ACT_SW2) of the active pattern (ACT). Each of the storage electrodes (SE) can be connected to the second end of the active pattern (ACT).

A capacitor dielectric film (CIL) can be disposed on the storage electrode (SE). The capacitor dielectric film (CIL) can be disposed between the storage electrode (SE) and the plate electrode (PE). The capacitor dielectric film (CIL) can be disposed between adjacent storage electrodes (SE). The capacitor dielectric film (CIL) can extend along the profile of the storage electrodes (SE).

The plate electrode (PE) can be disposed on the capacitor dielectric film (CIL). The plate electrode (PE) can be disposed between adjacent storage electrodes (SE). The plate electrode (PE) can extend in the second direction (D2) and the third direction (D3).

The storage electrode (SE) and the plate electrode (PE) may each include, but are not limited to, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide). As an example, the storage electrode (SE) may include a conductive metal nitride, a metal, and a conductive metal oxide.

The capacitor dielectric film (CIL) may include, for example, a high-k material (for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof). In a semiconductor memory device according to some embodiments, the capacitor dielectric film (CIL) may include a laminated film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially laminated. In a semiconductor memory device according to some embodiments, the capacitor dielectric film (CIL) may include hafnium (Hf).

The first cell insulating film (110) may be disposed on the active pattern (ACT) and the word line (WL). The first cell insulating film (110) may be disposed between adjacent bit lines (BL) in the first direction (D1). The first cell insulating film (110) may include an insulating material.

A plurality of word line pads (WP) may be arranged on a first substrate (100). The plurality of word line pads (WP) may be arranged on a pad area (EA). The plurality of word line pads (WP) may be arranged in a grid shape along the first and third directions (D1, D3).

The word line pads (WP) may be stacked in a third direction (D3). For example, a plurality of word line pads (WP) may include a first word line pad (WP1) and a second word line pad (WP2) located at different levels. The first word line pad (WP1) and the second word line pad (WP2) may be spaced apart from each other in the third direction (D3). The word line pads (WP) located at the same level may be spaced apart from each other in the first direction (D1).

The word line pads (WP) may have a step structure. The lengths of the word line pads (WP) stacked in the third direction (D3) in the second direction (D2) may be different from each other. For example, the length of the first word line pad (WP1) in the second direction (D2) may be longer than the length of the second word line pad (WP2) in the second direction (D2).

Each word line pad (WP) may have a line shape or a bar shape extending in the second direction (D2). The word line pad (WP) may be connected to a word line (WL) located at the same level. For example, the first word line pad (WP1) may be located at the same level as the first word line (WL1). The first word line pad (WP1) may be connected to the first word line (WL1). The second word line pad (WP2) may be located at the same level as the second word line (WL2). The second word line pad (WP2) may be connected to the second word line (WL2).

The width of the word line pad (WP) in the first direction (D1) may be greater than the width of the word line (WL) in the first direction (D1).

The word line pad (WP) may include a conductive material. For example, the word line pad (WP) may include, but is not limited to, at least one of a doped semiconductor material (e.g., doped silicon, doped silicon-germanium, doped germanium), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a metal (e.g., tungsten, titanium, tantalum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide).

A pad separation insulating film (PSD) may be disposed between adjacent word line pads (WP) in the third direction (D3). The pad separation insulating film (PSD) may include an insulating material. The pad separation insulating film (PSD) may include, for example, silicon oxide or silicon nitride.

A first pad embedded insulating film (PBI1) may be disposed between adjacent word line pads (WP) in a first direction (D1). The first pad embedded insulating film (PBI1) may be disposed on a sidewall of the word line pad (WP). For example, the word line pad (WP) may include a first sidewall and a second sidewall which are opposite to each other in the first direction (D1). The first pad embedded insulating film (PBI1) may be disposed on the second sidewall of the word line pad (WP).

The first pad embedded insulating film (PBI1) can extend in the second direction (D2). The first pad embedded insulating film (PBI1) can extend in the third direction (D3) along the sidewalls of the word line pads (WP) and the pad separation insulating film (PSD) that are stacked in the third direction (D3). The first pad embedded insulating film (PBI1) can overlap the data storage pattern (CAP) in the second direction (D2). The first pad embedded insulating film (PBI1) can include an insulating material.

A second pad embedded insulating film (PBI2) may be disposed on the pad area (EA). The second pad embedded insulating film (PBI2) may be disposed on a first sidewall of a word line pad (WP). The word line pad (WP) may be disposed between the first pad embedded insulating film (PBI1) and the second pad embedded insulating film (PBI2).

The second pad embedded insulating film (PBI2) may extend in the second direction (D2). The second pad embedded insulating film (PBI2) may extend in the third direction (D3) along sidewalls of word line pads (WP) and pad separation insulating films (PSD) that are stacked in the third direction (D3). The second pad embedded insulating film (PBI2) may overlap the bit line (BL) and the cell embedded insulating film (CBI) in the second direction (D2). The second pad embedded insulating film (PBI2) may include an insulating material.

A plurality of pad supporters (WPS) can be arranged on a first substrate (100). The plurality of pad supporters (WPS) can be arranged on a pad area (EA). The plurality of pad supporters (WPS) can be arranged in first and second directions (D1, D2). Each word line pad (WP) can surround pad supporters (WPS) arranged in the second direction (D2).

The pad supporter (WPS) can extend in a third direction (D3). The pad supporter (WPS) can penetrate the word line pads (WP) stacked in the third direction (D3).

The width of the pad supporter (WPS) in the first direction (D1) may be smaller than the width of the word line pad (WP) in the first direction (D1). The width of the pad supporter (WPS) in the first direction (D1) may be smaller than the width of the active pattern (ACT) in the first direction (D1).

The pad supporter (WPS) may include a supporter liner (161), a supporter filling film (162), and a supporter capping film (163). The supporter filling film (162) may be disposed on the supporter liner (161). The supporter filling film (162) may overlap word line pads (WP) laminated in a third direction (D3) in a first direction (D1).

A supporter liner (161) may be disposed between a word line pad (WP) and a supporter filling film (162) and between a pad separation insulating film (PSD) and the supporter filling film (162). The supporter liner (161) may surround the supporter filling film (162). The supporter liner (161) may extend along a side wall and a bottom surface of the supporter filling film (162). A supporter capping film (163) may be disposed on the supporter filling film (162).

The supporter liner (161) and the supporter capping film (163) may each include an insulating material. The supporter liner (161) and the supporter capping film (163) may each include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN).

The support liner (161) may include the same insulating material as the separation liner (151) of the active pattern separation structure (APS). For example, both the support liner (161) and the separation liner (151) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN).

The supporter filling film (162) may include a metal material. For example, the supporter filling film (162) may include tungsten (W).

The second cell insulating film (120) may be disposed on the pad area (EA). The second cell insulating film (120) may be disposed on the word line pads (WP). The upper surface of the second cell insulating film (120) may be coplanar with the upper surface of the first cell insulating film (110). The second cell insulating film (120) may include an insulating material.

The third cell insulating film (130) may be disposed on the first cell insulating film (110) and the second cell insulating film (120). The third cell insulating film (130) is illustrated as a single film, but is not limited thereto. The third cell insulating film (130) may be a multi-film in which a plurality of insulating films are laminated. The third cell insulating film (130) may include an insulating material.

The first connection line (132) may be arranged within the third cell insulating film (130). The first connection line (132) may be arranged on the word line pad (WP). The word line contacts (WC) may electrically connect the first connection line (132) and the word line pad (WP) by penetrating the second cell insulating film (120) and the third cell insulating film (130).

Since the plurality of word line contacts (WC) are connected to the word line pads (WP) having a step structure, the lengths of the word line contacts (WC) in the third direction (D3) may be different from each other. For example, the plurality of word line contacts (WC) may include a first word line contact (WC1) connected to a first word line pad (WP1) and a second word line contact (WC2) connected to a second word line pad (WP2). The length of the first word line contact (WC1) in the third direction (D3) may be longer than the length of the second word line contact (WC2) in the third direction (D3).

The second connection line (133) may be arranged within the third cell insulating film (130). The second connection line (133) may be arranged on the bit line (BL). The bit line contact (131) may electrically connect the second connection line (133) and the bit line (BL).

The first wiring structure (135) may be arranged within the third cell insulating film (130). The first wiring structure (135) may be arranged on the first connection line (132) and the second connection line (133). The first wiring structure (135) may be electrically connected to the first connection line (132) and the second connection line (133).

The first wiring structure (135) may include a vertical portion (135a) and a horizontal portion (135b). The vertical portion (135a) of the first wiring structure (135) may connect the first connection line (132) and the horizontal portion (135b) of the first wiring structure (135) and the first connection line (133) and the horizontal portion (135b) of the first wiring structure (135). The first wiring structure (135) is illustrated as having one layer, but is not limited thereto. When the first wiring structure (135) includes horizontal portions (135b) at different levels, the vertical portion (135a) may connect the horizontal portions (135b) at different levels.

The bit line contact (131), the word line contact (WC), the first connection line (132), the second connection line (133), and the first wiring structure (135) may each include a conductive material.

The first bonding pad (139) may be placed on the first wiring structure (135). The first bonding pad (139) may be electrically connected to the first wiring structure (135).

The first bonding pad (139) may include a conductive material. The first bonding pad (139) may include, for example, copper (Cu).

The peripheral circuit structure (PS) may be arranged on the cell structure (CS). The peripheral circuit structure (PS) and the cell structure (CS) may be bonded by dielectric bonding, chip to chip bonding, or Cu to Cu bonding. The peripheral circuit structure (PS) is illustrated as being arranged on the cell structure (CS), but is not limited thereto. Alternatively, the peripheral circuit structure (PS) may be arranged under the cell structure (CS).

The peripheral circuit structure (PS) may include a core and peripheral circuits. The peripheral circuit structure (PS) may include row and column decoders (2, 4 of FIG. 1), a sense amplifier (3 of FIG. 1), and control logic (5 of FIG. 1) described using FIGS. 1 and 2.

The peripheral circuit structure (PS) may include a second substrate (200), a peri transistor (PTR), a peri insulating film (210), a second wiring structure (215), and a second bonding pad (290).

The second substrate (200) may be bulk silicon or a silicon-on-insulator (SOI). Alternatively, the second substrate (200) may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

A peripheral transistor (PTR) may be placed on a second substrate (200). The peripheral transistor (PTR) may be, for example, an NMOS transistor or a PMOS transistor.

A ferry insulating film (210) may be placed on a second substrate (200). The ferry insulating film (210) may cover a ferry transistor (PTR). The ferry insulating film (210) may include an insulating material.

The second wiring structure (215) may be arranged within the ferry insulating film (210). The second wiring structure (215) may be arranged on the ferry transistor (PTR). The second wiring structure (215) may be electrically connected to the ferry transistor (PTR). The second wiring structure (215) may include a vertical portion (215a) and a horizontal portion (215b). The number of layers and arrangement of the illustrated second wiring structure (215) are merely exemplary and are not limited thereto.

The second bonding pad (219) may be disposed on the second wiring structure (215). The second bonding pad (219) may be electrically connected to the second wiring structure (215). The second bonding pad (219) may be in contact with the first bonding pad (139). The second bonding pad (219) may include a conductive material. The second bonding pad (219) may include, for example, copper (Cu).

The cell structure (CS) and the peripheral circuit structure (PS) can be bonded by the first bonding pad (139) and the second bonding pad (219).

A word line (WL) can be electrically connected to a peripheral transistor (PTR) through a word line pad (WP), a word line contact (WC), a first connection line (132), a first wiring structure (135), a first bonding pad (139), a second bonding pad (219), and a second wiring structure (219).

The bit line (BL) can be electrically connected to the peripheral transistor (PTR) through the bit line contact (131), the second connection line (133), the first wiring structure (135), the first bonding pad (139), the second bonding pad (219), and the second wiring structure (219).

FIGS. 10 to 53 are intermediate step drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. For convenience of explanation, any content that overlaps with the content explained using FIGS. 1 to 9 will be briefly explained or omitted.

Referring to FIGS. 10 to 12, a mold structure (MS) including a plurality of first sacrificial films (10) and a plurality of semiconductor films (20) alternately laminated on a first substrate (100) is formed.

The thickness of the first sacrificial film (10) in the third direction (D3) may be smaller than the thickness of the semiconductor film (20) in the third direction (D3).

The first sacrificial film (10) may be formed of a material having etch selectivity with respect to the semiconductor film (20). For example, the first sacrificial film (10) may include silicon germanium, and the semiconductor film (20) may include silicon. The first sacrificial film (10) and the semiconductor film (20) may be formed by performing an epitaxial growth process.

Referring to FIG. 13 and FIG. 14, a first embedded insulating film (11) and a second embedded insulating film (12) penetrating the laminated structure (MS) are formed.

The first buried insulating film (11) and the second buried insulating film (12) may be formed across the cell area (CA) and the pad area (EA). The first buried insulating film (11) and the second buried insulating film (12) may each extend in the second direction (D2). The first buried insulating film (11) and the second buried insulating film (12) may be alternately arranged along the first direction (D1). The first buried insulating film (11) may be spaced apart from the second buried insulating film (12) in the first direction (D1). The second buried insulating film (12) may be arranged between adjacent first buried insulating films (11). The first buried insulating film (11) and the second buried insulating film (12) may each include an insulating material.

Specifically, first, a plurality of trenches extending in a second direction (D2) are formed. The plurality of trenches can expose an upper surface of a first substrate (100). The plurality of trenches include first trenches and second trenches that are alternately arranged along the first direction (D1). Next, a first buried insulating film (11) is formed in the first trench, and a second buried insulating film (12) is formed in the second trench. The first buried insulating film (11) can fill the first trench. The second buried insulating film (12) can fill the second trench.

Referring to FIGS. 15 to 21, a plurality of pre-active pattern separation structures (pAPS) and a plurality of pad supports (WPS) are formed penetrating a laminated structure (MS).

A plurality of pre-active pattern separation structures (pAPS) can be formed on a cell area (CA). The plurality of pre-active pattern separation structures (pAPS) can be arranged in a lattice shape along first and second directions (D1, D2). The pre-active pattern separation structures (pAPS) can be arranged between a first buried insulating film (11) and a second buried insulating film (12). The pre-active pattern separation structures (pAPS) can extend in the first direction (D1).

As the pre-active pattern separation structure (pAPS) is formed, each semiconductor film (20) on the cell region (CA) can be separated into a plurality of active patterns (ACT). Each active pattern (ACT) can be defined by the pre-active pattern separation structures (pAPS), the first buried insulating film (11), and the second buried insulating film (12) adjacent to each other in the second direction (D2).

Hereinafter, the process of forming a pre-active pattern separation structure (pAPS) is described in detail using FIGS. 16, 17, 19, and 20.

Referring to FIGS. 16 and 17, a plurality of first cell trenches (CT1) penetrating the laminated structure (MS) are formed on the cell area (CA).

A plurality of first cell trenches (CT1) can be formed between the first buried insulating film (11) and the second buried insulating film (12). The plurality of first cell trenches (CT1) can be arranged along the first and second directions (D1, D2).

The first cell trench (CT1) can expose the upper surface of the first substrate (100). The first cell trench (CT1) can expose the sidewall of the first buried insulating film (11) and the sidewall of the second buried insulating film (12).

Referring to FIGS. 19 and 20, a pre-active pattern separation structure (pAPS) is formed within the first cell trench (CT1).

A pre-active pattern separation structure (pAPS) can fill the first cell trench (CT1). The pre-active pattern separation structure (pAPS) includes a separation liner (151), a pre-separation filling film (152p), and a separation capping film (153).

First, a separation liner (151) is formed within the first cell trench (CT1). The separation liner (151) may fill a portion of the first cell trench (CT1). The separation liner (151) may extend along the profile of the first cell trench (CT1).

The separation liner (151) may include an insulating material. The etch selectivity of the insulating material included in the separation liner (151) with respect to silicon may be greater than the etch selectivity of silicon nitride with respect to silicon. For example, the separation liner (151) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN).

Next, a pre-separation filling film (152p) is formed on the separation liner (151). The pre-separation filling film (152p) can fill at least a portion of the first cell trench (CT1). Specifically, a metal film can be formed on the separation liner (151). The metal film can be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD). The metal film can fill the first cell trench (CT1). Next, an etch-back process can be performed on the metal film to form the pre-separation filling film (152p).

A separation liner (151) may be placed between the laminated structure (MS) and the pre-separation peeling film (152p). The separation liner (151) may surround the pre-separation peeling film (152p).

The pre-separation peeling film (152p) may include a metal material. The pre-separation peeling film (152p) may include a metal material having a Young's modulus greater than that of silicon nitride. For example, the pre-separation peeling film (152p) may include tungsten (W).

Next, a separation capping film (153) is formed on the pre-separation peeling film (152p). The separation capping film (153) can cover the upper surface of the pre-separation peeling film (152p). The separation capping film (153) and the separation liner (151) can surround the pre-separation peeling film (152p).

The separating capping film (153) may include an insulating material. For example, the separating capping film (153) may include at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).

The separating capping film (153) may include the same insulating material as the separating liner (151). For example, both the separating capping film (153) and the separating liner (151) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN). In this case, the boundary between the separating capping film (153) and the separating liner (151) may not be distinguished.

Meanwhile, while the pre-active pattern separation structure (pAPS) is formed, a pad supporter (WPS) may be formed. A plurality of pad supporters (WPS) may be formed on the pad area (EA). The plurality of pad supporters (WPS) may be arranged in a grid shape along the first and second directions (D1, D2). The pad supporter (WPS) may be arranged between the first buried insulating film (11) and the second buried insulating film (12). The pad supporter (WPS) may extend in the first direction (D1).

The width of the pad supporter (WPS) in the first direction (D1) may be smaller than the width of the pre-active pattern separation structure (pAPS) in the first direction (D1).

The process of forming a pad supporter (WPS) is described in detail using FIG. 18 and FIG. 21.

Referring to FIG. 18, a plurality of first pad trenches (PT1) penetrating the laminated structure (MS) are formed on the pad area (EA).

A plurality of first pad trenches (PT1) can be formed between the first buried insulating film (11) and the second buried insulating film (12). The plurality of first pad trenches (PT1) can be arranged along the first and second directions (D1, D2). The first pad trenches (PT1) can be formed simultaneously with the first cell trenches (CT1).

The first pad trench (PT1) can expose the upper surface of the first substrate (100). The width of the first pad trench (PT1) in the first direction (D1) can be smaller than the width of the first cell trench (CT1) in the first direction (D1).

Referring to Fig. 21, a pad supporter (WPS) is formed within the first pad trench (PT1).

The pad supporter (WPS) can fill the first pad trench (PT1). The pad supporter (WPS) includes a supporter liner (161), a supporter filling film (162), and a supporter capping film (163).

First, a support liner (161) is formed within the first pad trench (PT1). The support liner (161) may fill a portion of the first pad trench (PT1). The support liner (161) may extend along the profile of the first pad trench (PT1).

The support liner (161) may include an insulating material. For example, the support liner (161) may include at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).

The support liner (161) may include the same insulating material as the separation liner (151) of the pre-active pattern separation structure (pAPS). Both the support liner (161) and the separation liner (151) may include at least one of silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN). In some embodiments, the support liner (161) may be formed simultaneously with the separation liner (151).

Next, a supporter filling film (162) is formed on the supporter liner (161). The supporter filling film (162) can fill at least a portion of the first pad trench (PT1).

The supporter filling film (162) may include a metal material. The supporter filling film (162) may include the same metal material as the pre-separation filling film (152p) of the pre-active pattern separation structure (pAPS). Both the supporter filling film (162) and the pre-separation filling film (152p) may include tungsten (W). In some embodiments, the supporter filling film (162) may be formed simultaneously with the pre-separation filling film (152p).

Next, a supporter capping film (163) is formed on the supporter filling film (162). The supporter capping film (163) and the supporter liner (161) may surround the supporter filling film (162). The supporter capping film (163) may include an insulating material. In some embodiments, the supporter capping film (163) may be formed simultaneously with the separation capping film (153) of the pre-active pattern separation structure (pAPS).

The first cell insulating film (110) can be formed on a laminated structure (MS), a pre-active pattern separation structure (pAPS), and a pad supporter (WPS).

Referring to FIGS. 22 to 25, the first sacrificial film (10) on the cell area (CA) is removed.

First, a second cell trench (CT2) and a third cell trench (CT3) are formed on the cell area (CA).

The second cell trench (CT2) can be formed by removing the first buried insulating film (11) on the cell area (CA). The second cell trench (CT2) can extend in the second direction (D2).

The third cell trench (CT3) can be formed by removing the second buried insulating film (12) on the cell area (CA). The third cell trench (CT3) can extend in the second direction (D2). The second buried insulating film (12) on the remaining pad area (EA) can be the first pad buried insulating film (PBI1).

The second cell trench (CT2) and the third cell trench (CT3) may each expose an upper surface of the first substrate (100). The second cell trench (CT2) and the third cell trench (CT3) may each expose a sidewall of the active pattern (ACT) and a sidewall of the first sacrificial film (10). The second cell trench (CT2) and the third cell trench (CT3) may expose a sidewall of the pre-active pattern separation structure (pAPS).

Next, an etching process is performed through the second cell trench (CT2) and the third cell trench (CT3) to remove the first sacrificial film (10). As the first sacrificial film (10) is removed, a first horizontal region (HR1) may be formed. The first horizontal region (HR1) may be a space formed by removing the first sacrificial film (10). As the first sacrificial film (10) is removed, the upper surface and the bottom surface of the active pattern (ACT) may be exposed.

Referring to FIGS. 26 and 27, a trim process is performed to reduce the thickness of the active pattern (ACT).

The trim process can be performed through the first horizontal region (HR1). As the trim process is performed, a portion of the active pattern (ACT) is removed, so that a thickness of the active pattern (ACT) in the third direction (D3) can be reduced. As the thickness of the active pattern (ACT) in the third direction (D3) is reduced, a length of the first horizontal region (HR1) in the third direction (D3) can be increased. The trim process can be a wet etching process.

Referring to FIG. 28 and FIG. 29, an interlayer insulating film (ILD) is formed within the first horizontal region (HR1).

An interlayer dielectric (ILD) can fill the first horizontal region (HR1). The interlayer dielectric (ILD) can include an insulating material. For example, the interlayer dielectric (ILD) can include silicon oxide.

The pre-active pattern separation structure (pAPS) can support the active patterns (ACT). Accordingly, even if the first sacrificial film (10) is removed, the active patterns (ACT) can remain spaced apart from each other in the third direction (D3). In order to support the active patterns (ACT) stacked in the third direction (D3), the pre-active pattern separation structure (pAPS) needs to have high rigidity.

However, when the pre-active pattern separation structure (pAPS) is formed of silicon oxide, silicon nitride, or a combination thereof, a part of the pre-active pattern separation structure (pAPS) may be removed together during the process of removing a part of the active pattern (ACT) through the trim process, which may lower the rigidity of the pre-active pattern separation structure (pAPS). In this state, when an interlayer insulating film (ILD) that fills the space between adjacent active patterns (ACTs) in the third direction (D3) is formed, the pre-active pattern separation structure (pAPS) may collapse.

The pre-active pattern separation structure (pAPS) of the present invention includes a pre-separation filling film (152p) including a metal material. The pre-separation filling film (152p) may include a metal material (e.g., tungsten (W)) having a Young's modulus higher than that of silicon nitride. Accordingly, the pre-active pattern separation structure (pAPS) of the present invention may have high rigidity compared to a structure formed of silicon oxide, silicon nitride, or a combination thereof. Through this, a method for manufacturing a semiconductor memory device with improved yield may be provided.

In addition, the pre-active pattern separation structure (pAPS) of the present invention includes a separation liner (151) including an insulating material (e.g., silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN)) having a smaller removal amount than silicon nitride during a trim process for an active pattern (ACT). The separation liner (151) surrounds a pre-separation filling film (152p). Accordingly, the pre-separation filling film (152p) may not be exposed during a trim process for the active pattern (ACT), and the structural stability of the pre-active pattern separation structure (pAPS) may be improved.

Referring to FIGS. 30 to 33, the pre-separation peeling film (152p) is replaced with a separation peeling film (152) to form an active pattern separation structure (APS).

Specifically, referring to FIGS. 30 and 31, first, a portion of the separation liner (151) exposed by the second cell trench (CT2) and the third cell trench (CT3) is removed. As a portion of the separation liner (151) is removed, a side wall of the pre-separation peeling film (152p) may be exposed.

Next, an etching process is performed through the second cell trench (CT2) and the third cell trench (CT3) to remove the pre-separation filling film (152p). As the pre-separation filling film (152p) is removed, an internal region (IR) may be formed. The internal region (IR) may be a space formed by removing the pre-separation filling film (152p).

Next, referring to FIG. 32 and FIG. 33, a separation filling film (152) is formed within the inner region (IR). The separation filling film (152) can fill the inner region (IR). The separation filling film (152) can include an insulating material. For example, the separation filling film (152) can include silicon oxide. The active pattern separation structure (APS) can include a separation liner (151), a separation filling film (152), and a separation capping film (153).

Referring to FIGS. 34 to 40, a plurality of word lines (WL) are formed that intersect with a plurality of active patterns (ACT) and are stacked in a third direction (D3).

First, referring to FIGS. 35 to 37, a third buried insulating film (13) filling a third cell trench (CT3) is formed. Next, an etching process is performed through the second cell trench (CT2) to remove a portion of the active pattern separation structure (APS) and a portion of the interlayer insulating film (ILD), thereby forming a second horizontal region (HR2).

The second horizontal region (HR2) may be a space formed by removing a portion of the active pattern separation structure (APS) and a portion of the interlayer dielectric film (ILD). As a portion of the active pattern separation structure (APS) and a portion of the interlayer dielectric film (ILD) are removed, a sidewall of the active pattern (ACT), a portion of the top surface of the active pattern (ACT), and a portion of the bottom surface of the active pattern (ACT) may be exposed.

Next, referring to FIGS. 38 to 40, a gate insulating film (GI) is formed on the second horizontal region (HR2). The gate insulating film (GI) may extend along the profile of the second horizontal region (HR). The gate insulating film (GI) may surround the active pattern (ACT). The gate insulating film (GI) may cover a sidewall of the interlayer insulating film (ILD). The gate insulating film (GI) may cover a sidewall of the active pattern separation structure (APS).

Next, a second sacrificial film may be formed on the gate insulating film (GI). The second sacrificial film may extend along the profile of the gate insulating film (GI). The second sacrificial film may fill a portion of the second horizontal region (HR2). The second sacrificial film may be, for example, silicon nitride.

The second sacrificial film includes a first portion that overlaps the active pattern (ACT) in a third direction (D3) and a second portion that does not overlap the active pattern (ACT) in the third direction (D3). The first portion of the second sacrificial film and the second portion of the second sacrificial film can be connected to each other.

The second portion of the second sacrificial film may include a roughness. The thickness of the second portion formed at the same level as the active pattern (ACT) in the first direction (D1) may be thicker than the thickness of the second portion formed at a different level from the active pattern (ACT) in the first direction (D1).

Next, a second gate separator (GS2) can be formed on the second sacrificial film. The second gate separator (GS2) can fill the remaining second horizontal region (HR2).

Next, a portion of the second sacrificial film is replaced with a word line (WL). Specifically, a portion of the second sacrificial film is removed. The remaining second sacrificial film may be a first gate separator (GS1). Next, word lines (WL) are formed on a space from which the second sacrificial film is removed. The word line (WL) may fill a portion of the space from which the second sacrificial film is removed. Each word line (WL) may be formed to be separated from each other in a third direction (D3) by the second gate separator (GS) and the remaining second sacrificial film.

Next, a gate capping film (CGP) is formed on the word line (WL). The gate capping film (CGP) can fill the remaining space from which the second sacrificial film is removed.

Referring to FIGS. 41 to 43, a plurality of bit lines (BL) are formed within the second cell trench (CT2). Forming the bit lines (BL) may include depositing a conductive film filling the second cell trench (CT2) and then removing a portion of the conductive film to divide the conductive film.

Before forming the bit line (BL), impurities may be doped into the active pattern (ACT) through a sidewall of the active pattern (ACT) exposed by the second cell trench (CT2). Accordingly, a first impurity region may be formed at a first end of the active pattern (ACT). The first impurity region may be in contact with the bit line (BL). The first impurity region may be formed by performing a gas phase doping (GPD) process or a plasma doping (PLAD) process through the second cell trench (CT2).

Next, a cell buried insulating film (CBI) is formed within the second cell trench (CT2). The cell buried insulating film (CBI) can fill the second cell trench (CT2) together with the bit line (BL).

Referring to FIGS. 44 to 48, a third buried insulating film (13), a portion of the active pattern separation structure (APS), and a portion of the interlayer insulating film (ILD) are removed to form a data storage pattern (CAP).

First, referring to FIGS. 45 and 46, the third buried insulating film (13) is removed to form a fourth cell trench (CT4). Next, a portion of the active pattern separation structure (APS) and a portion of the interlayer insulating film (ILD) are removed to form a third horizontal space (HR3). A portion of the active pattern separation structure (APS) and a portion of the interlayer insulating film (ILD) can be removed by performing an etching process through the fourth cell trench (CT4).

Next, referring to FIGS. 47 and 48, a plurality of storage electrodes (SE), capacitor dielectric films (CIL), and plate electrodes (PE) are sequentially formed within the third horizontal space (HR3) and the fourth cell trench (CT4).

Before forming the data storage pattern (CAP), impurities may be doped into the active pattern (ACT) exposed by the fourth cell trench (CT4) and the third horizontal space (HR3). Accordingly, a second impurity region may be formed at a second end of the active pattern (ACT). The second impurity region may be in contact with the storage electrode (SE). The second impurity region may be formed by performing a gas phase doping (GPD) process or a plasma doping (PLAD) process through the fourth cell trench (CT2) and the third horizontal space (HR3).

Referring to FIGS. 49 to 53, a plurality of word line pads (WP) are formed on a pad area (EA).

First, referring to FIGS. 50 and 51, a portion of the semiconductor film (20) on the pad area (EA) is removed to form a step structure. Next, a second cell insulating film (120) covering the semiconductor film (20) on the pad area (EA) is formed.

Next, the first buried insulating film (11) on the pad area (EA) is removed to form a second pad trench (PT2). The second pad trench (PT2) can expose a side wall of the laminated structure (MS) on the pad area (EA).

Next, referring to FIG. 52 and FIG. 53, the semiconductor film (20) on the pad area (EA) is replaced with a word line pad (WP), and the first sacrificial film (10) on the pad area (EA) is replaced with a pad separation insulating film (PSD).

Replacing the semiconductor film (20) on the pad area (EA) with a word line pad (WP) includes removing the semiconductor film (20) by performing an etching process through the second pad trench (PT2), and forming the word line pad (WP) on the space from which the semiconductor film (20) was removed.

Replacing the first sacrificial film (10) on the pad area (EA) with a pad separation insulating film (PSD) includes performing an etching process through the second pad trench (PT2) to remove the first sacrificial film (10), and forming a pad separation insulating film (PSD) on the space from which the first sacrificial film (10) was removed.

After the word line pad (WP) and pad separation insulating film (PSD) are formed, a second pad buried insulating film (PBI2) can be formed to fill the second pad trench (PT2).

Referring to FIGS. 5 to 9, a word line contact (WC) is formed on a word line pad (WP), and a bit line contact (131) is formed on a bit line (BL). A third cell insulating film (130) is formed on the word line contact (WC) and the bit line contact (131). Next, a first connection line (132) is formed on the word line contact (WC), and a second connection line (133) is formed on the bit line contact (131). Next, a first wiring structure (135) is formed on the first connection line (132) and the second connection line (133). Next, a first bonding pad (139) is formed on the first wiring structure (135).

Next, the cell structure (CS) and the peripheral circuit structure (PS) are bonded. The peripheral circuit structure (PS) includes a second substrate (200), a peripheral transistor (PTR), a second wiring structure (215), and a second bonding pad (219). The cell structure (CS) and the peripheral circuit structure (PS) can be bonded through the first bonding pad (139) and the second bonding pad (219).

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

100: 1st substrate CS: cell structure
ACT: Active Pattern APS: Active Pattern Separation Structure
WL: Word Line WP: Word Line Pad
WPS: Pad Supporter WC: Word Line Contact
BL: Bit line CAP: Data storage pattern
PS: Peripheral circuit structure PTR: Peripheral transistor
MS: Stacked structure pAPS: Free active pattern separation structure
152p: Free separation peeling film

Claims (10)

A laminated structure is formed in which a plurality of semiconductor films and a plurality of sacrificial films are alternately laminated on a substrate including a cell region and a pad region,
A plurality of embedded insulating films are formed that penetrate the above laminated structure, extend in a first direction, and are spaced apart from each other in a second direction intersecting the first direction,
On the cell region, a pre-active pattern separation structure is formed penetrating the laminated structure and extending in the second direction to separate each semiconductor film into a plurality of active patterns, wherein the pre-active pattern separation structure includes a pre-separation filling film including a metal material, and a separation liner disposed between the laminated structure and the pre-separation filling film.
A first trench is formed by removing a portion of the above-mentioned buried insulating film to expose a side wall of the above-mentioned laminated structure,
By removing the sacrificial layer, the upper and lower surfaces of the active pattern are exposed,
A method for manufacturing a semiconductor memory device, comprising performing a trimming process on the active pattern to reduce the thickness of the active pattern. In the first paragraph,
A method for manufacturing a semiconductor memory device, further comprising forming an active pattern separation structure by replacing the above-mentioned pre-separation peeling film with a separation peeling film including an insulating material. In the second paragraph,
Forming the above active pattern separation structure is:
By removing a portion of the above separation liner, the side wall of the above pre-separation peeling membrane is exposed,
Remove the above free separation peeling film,
A method for manufacturing a semiconductor memory device, comprising forming a separation peeling film on a space from which the above-mentioned pre-separation peeling film has been removed. In the first paragraph,
A method for manufacturing a semiconductor memory device, wherein the above-mentioned pre-separation peeling film includes a metal material having a Young's modulus greater than that of silicon nitride. In the first paragraph,
The above free active pattern separation structure further includes a separation capping film disposed on the above free separation filling film,
Forming the above free active pattern separation structure is:
Forming a second trench exposing the above substrate,
Within the second trench, the separation liner is formed extending along the profile of the trench,
On the above separation liner, a pre-separation filling film is formed to fill a portion of the second trench,
A method for manufacturing a semiconductor memory device, comprising forming a separation capping film covering an upper surface of the pre-separation filling film within the second trench. In the first paragraph,
forming a word line that intersects the above active pattern and extends in the first direction;
On the first sidewall of the above active pattern, a bit line is formed that is connected to the above active pattern and extends in a third direction intersecting the first direction and the second direction,
Further comprising forming a data storage pattern connected to the active pattern on the second side wall of the active pattern,
A method for manufacturing a semiconductor memory device, wherein the first sidewall of the active pattern is opposite to the second sidewall of the active pattern in the second direction. In Article 6,
While the above free active pattern separator is formed, a pad supporter penetrating the laminated structure is formed on the pad area of the substrate,
A method for manufacturing a semiconductor memory device, further comprising replacing a semiconductor film on the pad area with a word line pad. A substrate comprising a cell region and a pad region;
A plurality of first active patterns disposed on the cell area, arranged in a first direction, and including first sidewalls and second sidewalls opposite to a second direction intersecting the first direction;
A plurality of second active patterns arranged on the first active pattern and arranged in the first direction;
A bit line disposed on a first sidewall of the first active pattern, connected to the first active pattern, and extending in a third direction intersecting the first direction and the second direction;
A data storage pattern disposed on a second sidewall of the first active pattern and connected to the first active pattern;
A first word line disposed on the cell area, intersecting the first active pattern, and extending in the first direction;
A second word line disposed on the first word line, intersecting the second active pattern, and extending in the first direction;
A first word line pad disposed on the pad area, connected to the first word line, and extending in the first direction;
a second word line pad disposed on the first word line pad, connected to the second word line, and extending in the first direction; and
A pad supporter is included that penetrates the first word line pad and the second word line pad,
A semiconductor memory device, wherein the pad supporter includes a supporter filling film including a metal material, and a supporter liner disposed between the first word line pad and the supporter filling film and between the second word line pad and the supporter filling film. In Article 8,
A peripheral circuit structure disposed on the first word line pad and including a peri transistor,
A semiconductor memory device further comprising a word line contact connecting the first word line pad and the first transistor. In Article 8,
Further comprising an active pattern separation structure disposed between the adjacent second active patterns, overlapping the first active pattern and the second active pattern in the first direction, and extending in the third direction;
The above active pattern separation structure includes a separation liner disposed on a substrate and a separation peeling film disposed on the separation liner,
The above support liner and the above separation liner contain the same insulating material,
A semiconductor memory device, wherein the same insulating material comprises at least one of silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN).

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