KR20240177934A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device is provided, comprising: a conducting region extending in a first direction and a second direction intersecting the first direction; and a terminal region positioned at an end of the conducting region in the first direction, wherein the terminal region includes an n+ type substrate extending in the first direction and the second direction, an n-type layer positioned over a third direction intersecting the first direction and the second direction of the n+ type substrate, and an insulating layer positioned over the third direction of the n-type layer, wherein a length of the n-type layer along the third direction at any one point is greater than a length along the third direction at an end of the first direction.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

This invention relates to a semiconductor device and a method for manufacturing the same.

Semiconductors including power semiconductor devices are separated into single devices or chip units called die after the device manufacturing process is completed on a wafer basis.

This separation process is called dicing or wafer sawing and is the final step in the device manufacturing process.

The dicing process can be done mechanically using a diamond blade, or optically or chemically using a laser or plasma.

In the case of power semiconductors, dicing by physical methods using blades with high production speed is mainly used because they have relatively thick epi thicknesses.

In the case of blade dicing, since it is a method of physically grinding the wafer, chipping occurs. If the crack invades the element area, the element may be destroyed due to damage or may not operate properly.

One aspect of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, which can reduce process costs and time by implementing a step cut dicing method using only one blade, and increase yield by reducing the possibility of chipping.

A semiconductor device according to one aspect includes a conducting region extending in a first direction and a second direction intersecting the first direction, and a terminal region positioned at an end of the conducting region in the first direction, the terminal region including an n+ type substrate extending in the first direction and the second direction, an n-type layer positioned over a third direction intersecting the first direction and the second direction of the n+ type substrate, and an insulating layer positioned over the third direction of the n-type layer, wherein a length of the n-type layer along the third direction at any one point is greater than a length at an end of the first direction along the third direction.

The n-type layer may have a step portion with a different length in the third direction at the end in the first direction.

The insulating layer may also be located on the third direction of the step.

The n-type layer may have a sloped portion whose length in the third direction gradually decreases at the end in the first direction.

The insulating layer may include a buffer layer, a gate insulating film, an intermetallic insulating film, or a combination thereof.

The conducting region may include an n+ type substrate extending in the first direction and the second direction, an n-type layer positioned over a third direction of the n+ type substrate and having a trench opening upward in the third direction, a p-type region positioned within the n-type layer, a gate electrode positioned within the trench, and a source electrode and a drain electrode arranged to be insulated from the gate electrode.

The conductive region may further include a gate insulating film positioned between the trench and the gate electrode; an intermetallic insulating film positioned between the source electrode or drain electrode and the gate electrode; or a combination thereof.

The conducting region may include an n+ type substrate extending in the first direction and the second direction, an n-type layer positioned over a third direction of the n+ type substrate and having a trench opening upward in the third direction, a p-type region positioned within the n-type layer, an anode electrode positioned within the trench, and a cathode electrode arranged to be insulated from the anode electrode.

The semiconductor device may further include a connection region positioned between the first direction of the conducting region and the termination region.

The connection region may include an n+ type substrate extending in the first direction and the second direction, an n-type layer positioned over a third direction of the n+ type substrate, a p-type region positioned within the n-type layer, a lower gate runner positioned over the p-type region and connected to the gate electrode, and an upper gate runner positioned over the lower gate runner.

The connection region may further include a buffer layer positioned between the p-type region and the lower gate runner; a gate insulating film positioned between the p-type region and the lower gate runner; an intermetallic insulating film positioned over the lower gate runner and the buffer layer or the gate insulating film, exposing a portion of the lower gate runner; or a combination thereof.

A method for manufacturing a semiconductor device according to another aspect may include a step of preparing an n+ type substrate extending in a first direction and a second direction intersecting the first direction, a step of forming an n-type layer on a third direction intersecting the first direction and the second direction of the n+ type substrate, a step of forming a first trench in the n-type layer opening upward in the third direction, a step of forming an insulating layer on an inner surface of the first trench, and a step of manufacturing a terminal region including a step of cutting the insulating layer, the n-type layer, and the n+ type substrate downward in the third direction from a lower surface of the first trench.

The cutting step can be performed by inserting a blade having a width smaller than a length along the first direction of the first trench into the first trench.

The step of forming an insulating layer may include a step of forming a buffer layer, a step of forming a gate insulating film, a step of forming an intermetallic insulating film, or a combination thereof.

A method for manufacturing a semiconductor device may further include a step of manufacturing a conducting region, including a step of forming a second trench opening upward in a third direction in an n-type layer, a step of forming a gate insulating film inside the second trench, a step of forming a gate electrode inside the second trench, a step of forming an intermetallic insulating film over the gate electrode, and a step of forming a source electrode and a drain electrode so as to be insulated from the gate electrode.

The first trench and the second trench can be formed simultaneously in one process.

A method for manufacturing a semiconductor device may further include a step of manufacturing a connection region, including a step of forming a p-type region within an n-type layer, a step of forming a buffer layer over the p-type region, a step of forming a gate insulating film over the buffer layer, a step of forming a lower gate runner positioned over the gate insulating film and connected to a gate electrode, a step of forming an intermetal insulating film covering a portion of the lower gate runner, and a step of forming an upper gate runner positioned over the intermetal insulating film and connected to the lower gate runner exposed between the intermetal insulating films.

A semiconductor device and a method for manufacturing the same according to one aspect can implement a step cut dicing method using only one blade, thereby reducing process costs and required time, and increasing yield by reducing the possibility of chipping.

FIG. 1 is a cross-sectional drawing of a semiconductor device according to one embodiment.
FIG. 2 is a cross-sectional view corresponding to FIG. 1, showing a semiconductor device according to another embodiment.
FIG. 3 is a cross-sectional view corresponding to FIG. 1, showing a semiconductor device according to another embodiment.
Figure 4 is a cross-sectional view showing a manufacturing process of a semiconductor device according to conventional technology.
FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment.
FIG. 6 is a cross-sectional view showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment.

The advantages and features of the technology described hereinafter, and the methods for achieving them, will become clear with reference to the detailed implementation examples described below together with the accompanying drawings. However, the form in which it is implemented is not limited to the implementation examples disclosed below. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning that can be commonly understood by a person having ordinary skill in the art. In addition, terms defined in commonly used dictionaries shall not be ideally or excessively interpreted unless explicitly specifically defined. When a part throughout the specification is said to "include" a certain component, this does not mean that other components are excluded, but that other components can be further included, unless specifically stated otherwise.

Also, the singular includes the plural unless specifically stated otherwise in the text.

In order to clearly represent various layers and areas in the drawings, the thickness is enlarged and shown. Similar parts are given the same drawing reference numerals throughout the specification.

When we say that a part, such as a layer, membrane, region, or plate, is "on top of" another part, this includes not only cases where it is "directly on top of" that part, but also cases where there are parts in between. Conversely, when we say that a part is "directly on top of" another part, we mean that there are no parts in between.

FIG. 1 is a drawing illustrating a cross-section of a semiconductor device (1000) according to one embodiment.

The semiconductor element (1000) may extend in a first direction (D1) and a second direction (D2) intersecting the first direction (D1), and may be laminated in a third direction (D3) intersecting the first direction (D1) and the second direction (D2). For example, the semiconductor element (1000) may have upper and lower surfaces extending in the first direction (D1) and the second direction (D2) and facing each other in the third direction (D3). That is, the third direction (D3) may be a thickness direction of the semiconductor element (1000).

Figure 1 is a cross-sectional view cut in the first direction (D1) and the third direction (D3).

Referring to FIG. 1, the semiconductor element (1000) includes a conducting region (1100), a connection region (1200), and a termination region (1300). The conducting region (1100) is a region in which current flows when a forward voltage is applied, the termination region (1300) is a region located at the end of the conducting region (1100) in the first direction (D1), and the connection region (1200) is a region located between the conducting region (1100) and the termination region (1300) in the first direction (D1).

For example, the conducting region (1100) of the semiconductor device (1000) includes an n+ type substrate (100), an n- type layer (200), a p-type region (400), a gate electrode (700), a source electrode (800), and a drain electrode (900).

The n+ type substrate (100) may extend in a first direction (D1) and a second direction (D2) and have an upper surface and a lower surface facing each other in a third direction (D3).

For example, the n+ type substrate (100) may be an n+ type silicon carbide substrate. An n-type layer (200) is positioned on the upper surface of the n+ type substrate (100).

The n-type layer (200) of the conductive region (1100) has a second trench (212). The second trench (212) is opened to the upper surface of the n-type layer (200).

A p-type region (400) is located inside the n-type layer (200) and on the side of the second trench (212), i.e., next to it in the first direction (D1).

Optionally, the n+ type region (500) may be located inside the p-type region (400) and on the side of the second trench (212). Additionally, the p+ type region (not shown) may be located inside the p-type region (400) and may be located next to the n+ type region (500) in the first direction (D1).

A gate insulating film (620) is positioned inside the second trench (212), and a gate electrode (700) is positioned on the gate insulating film (620). The gate electrode (700) fills the inside of the second trench (212) and may protrude outside the second trench (212). The gate electrode (700) may include polysilicon or metal.

The gate insulating film (620) may include SiO ₂ , Si ₂ N ₃ , SiN, Al ₂ O ₃ , PSG (Phospho-Silicate Glass), USG (Undoped Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boro-Phospho-silicate Glass), or a combination thereof.

An intermetal insulating film (630) is positioned over the gate electrode (700). Optionally, the intermetal insulating film (630) may also be positioned over the n+ type region (500), the p+ type region (not shown), or the p type region (400).

The intermetal insulating film (630) may include SiO ₂ , Si ₂ N ₃ , SiN, Al ₂ O ₃ , PSG (Phospho-Silicate Glass), USG (Undoped Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boro-Phospho-silicate Glass), or a combination thereof. In addition, the intermetal insulating film (630) may include the same material as the gate insulating film (620).

A source electrode (800) is positioned on an intermetallic insulating film (630). The source electrode (800) is insulated from the gate electrode (700) by the intermetallic insulating film (630). The source electrode (800) may include an ohmic metal.

A drain electrode (900) is positioned on the lower surface of the n+ type substrate (100). The drain electrode (900) may include an ohmic metal.

The connection region (1200) of the semiconductor device (1000) includes an n+ type substrate (100), an n- type layer (200), a p-type region (400), a p-type termination structure (450), a lower gate runner (750), an upper gate runner (760), and a drain electrode (900).

A p-type region (400) located on the side of the second trench (212) adjacent to the terminal region (1300) extends to the connection region (1200). A buffer layer (610) may be located on the p-type region (400). A gate insulating film (620) may be located on the buffer layer (610).

The buffer layer (610) may include SiO ₂ , Si ₂ N ₃ , SiN, Al ₂ O ₃ , PSG (Phospho-Silicate Glass), USG (Undoped Silicate Glass), BSG (Boro-Silicate Glass), BPSG (Boro-Phospho-silicate Glass), or a combination thereof. In addition, the buffer layer (610) may include the same material as the gate insulating film (620).

A lower gate runner (750) is positioned on the buffer layer (610) or the gate insulating film (620). The lower gate runner (750) is connected to a gate electrode (700) positioned adjacent to the termination region (1300), and may be connected to a gate electrode (700) protruding outside the second trench (212), for example. The lower gate runner (750) may include the same material as the gate electrode (700), and may include polysilicon or a metal.

An intermetallic insulating film (630) is positioned on the lower gate runner (750) and the buffer layer (610) or the gate insulating film (620). The intermetallic insulating film (630) does not completely cover the lower gate runner (750) but exposes a portion of the lower gate runner (750).

An upper gate runner (760) is positioned on an intermetallic insulating film (630), and the upper gate runner (760) is connected to a lower gate runner (750) exposed between the intermetallic insulating films (630). The upper gate runner (760) may include the same material as the source electrode (800).

The lower gate runner (750) and the upper gate runner (760) are intended to quickly apply gate voltage to the gate electrode (700).

A p-type termination structure (450) is located in the n-type layer (200) of the connection region (1200). The p-type termination structure (450) includes a plurality of regions into which p-type ions are injected, and the regions into which p-type ions are injected are spaced apart from each other by a predetermined interval.

The thickness of the region where the p-type ions are implanted to form the p-type termination structure (450) is shallower than the depth of the second trench (212). Additionally, the thickness of the region where the p-type ions are implanted to form the p-type termination structure (450) may be the same as the thickness of the portion of the p-type region (400).

A buffer layer (610), a gate insulating film (620), and an intermetallic insulating film (630) extend over the n-type layer (200) of the p-type termination structure (450) and the termination region (1300).

The terminal region (1300) of the semiconductor device (1000) includes an n+ type substrate (100), an n- type layer (200), an insulating layer (600), and a drain electrode (900).

The insulating layer (600) includes a buffer layer (610), a gate insulating film (620), and an intermetal insulating film (630). The buffer layer (610) may extend from the connection region (1200) to the termination region (1300), and the gate insulating film (620) and the intermetal insulating film (630) may extend from the conductive region (1100) and the connection region (1200) to the termination region (1300).

The n-type layer (200) of the terminal region (1300) has a step portion (1310) having a different length, i.e., thickness, in the third direction (D3) at the end in the first direction (D1). For example, the n-type layer (200) of the terminal region (1300) may have a length (T1) in the third direction (D3) at a point in the first direction (D1) greater than a length (T2) in the third direction (D3) at the end in the first direction (D1).

That is, the length (T2) of the step portion (1310) along the third direction (D3) may be smaller than the length (T1) of the other n-type layer (200) along the third direction (D3). For example, the greater the difference between the length (T1) of the other n-type layer (200) along the third direction (D3) and the length (T2) of the step portion (1310) along the third direction (D3), the better the effect may be. In addition, as described below, the upper height of the length (T2) of the step portion (1310) along the third direction (D3) may be the same level as the bottom surface of the second trench (212) for forming the gate electrode (700), or may be higher in the third direction (D3) than the level of the bottom surface.

In addition, the length, i.e., width, of the step portion (1310) along the first direction (D1) is preferably narrower, but the width of the step portion (1310) is preferably wider than the thickness of the second blade (1402), and may include a process margin for forming the second dicing line.

At this time, the insulating layer (600) may also be positioned on the third direction (D3) of the step portion (1310). In addition, it may also be positioned next to the first direction (D1), that is, on the side wall of the step portion (1310).

In FIG. 1, the step portion (1310) is illustrated as having only one step, but the step portion (1310) may have two or more, three or more, five or more, ten or fewer, or five or fewer steps.

Below, a semiconductor device (1000) according to another embodiment will be described with reference to FIG. 2.

FIG. 2 is a cross-sectional view corresponding to FIG. 1, showing a semiconductor device (1000) according to another embodiment.

The embodiment illustrated in Fig. 2 is substantially the same as the embodiment illustrated in Fig. 1, so a description thereof will be omitted and the differences will be mainly explained.

In Fig. 1, the n-type layer (200) of the terminal region (1300) is illustrated as having a step portion (1310) with a different length in the third direction (D3) at the end in the first direction (D1).

In FIG. 2, the n-type layer (200) of the terminal region (1300) is illustrated as having an inclined portion (1320) whose length in the third direction (D3) gradually decreases at the end in the first direction (D1). That is, the end in the first direction (D1) of the terminal region (1300) may have a length (T1) in the third direction (D3) that gradually decreases as in FIG. 1 or gradually decreases as in FIG. 2.

Below, a semiconductor device (1000) according to another embodiment will be described with reference to FIG. 3.

FIG. 3 is a cross-sectional view corresponding to FIG. 1, showing a semiconductor device (1000) according to another embodiment.

The embodiment illustrated in Fig. 3 has many parts identical to the embodiment illustrated in Fig. 1, so a description thereof will be omitted and the differences will be mainly explained.

In FIG. 1, the conducting region (1100) is illustrated as including an n+ type substrate (100), an n- type layer (200), a p-type region (400), a gate electrode (700), a source electrode (800), and a drain electrode (900). That is, FIG. 1 illustrates a case where the semiconductor element (1000) is a MOSFET.

In FIG. 3, the current-carrying region (1100) is illustrated as including an n+-type substrate (100), an n-type layer (200), a p-type region (400), an anode electrode (810), and a cathode electrode (910). That is, FIG. 3 illustrates a case where the semiconductor element (1000) is an IGBT.

The n-type layer (200) of the conductive region (1100) has a second trench (212), and a p-type region (400) is located inside the second trench (212).

The anode electrode (810) is positioned on the n-type layer (200) and within the second trench (212). The anode electrode (810) may include Cr, Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, polycrystalline Si, oxides thereof, nitrides thereof, or alloys thereof. In addition, the anode electrode (810) may include a multilayer structure in which different metal films are laminated, for example, Pt/Au, Pt/Al, Pd/Au, Pd/Al, or Pt/Ti/Au and Pd/Ti/Au.

The cathode electrode (910) is positioned below the n+ type substrate (100) and makes ohmic contact with the n+ type substrate (100). The cathode electrode (910) may include Cr, Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, polycrystalline Si, oxides thereof, nitrides thereof, or alloys thereof. In addition, the cathode electrode (910) may include a multilayer structure in which different metal films are laminated, for example, Ti/Au or Ti/Al. In this case, in order to ensure ohmic contact between the cathode electrode (910) and the n+ type substrate (100), the layer of the cathode electrode (910) that makes contact with the n+ type substrate (100) may include Ti.

Hereinafter, a method for manufacturing a semiconductor device (1000) according to one embodiment will be described with reference to FIGS. 4 to 6.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor device (1000) according to a conventional technique, and FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device (1000) according to one embodiment. FIG. 6 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device (1000) according to one embodiment.

Referring to FIG. 4, the manufacturing process of a semiconductor element (1000) according to the prior art uses a step cut dicing method to prevent cracks occurring during blade dicing from encroaching on and growing into the area of a preliminary semiconductor element (1000_P).

For example, a preliminary semiconductor element (1000_P) is formed on a wafer fixing part (1500) (S1_P), and a first dicing line (dicing line or sawing line) having a wide width is formed primarily using a first blade (1401) having a wide width (S2_P), and then a second dicing line having a narrow width is formed secondly using a second blade (1402) having a narrow width (S3_P), thereby separating the preliminary semiconductor element (1000_P).

In this case, since two dicing processes are performed with two types of blades, the process cost and time increase.

On the other hand, referring to FIG. 5, the manufacturing process of the semiconductor device (1000) according to one embodiment is a step cut dicing method using only one second blade (1402).

A method for manufacturing a semiconductor device (1000) according to one embodiment of the present invention comprises: in a step (S1) of forming a preliminary semiconductor device (1000_P), forming a first trench (211) using an etching process; utilizing the first trench (211) as a first dicing line (dicing line or sawing line), forming a second dicing line having a narrower width using a second blade (1402) having a narrower width than the first trench (211); thereby separating the preliminary semiconductor device (1000_P).

That is, the method for manufacturing a semiconductor device (1000) according to one embodiment can improve process time and cost by replacing sawing by the first blade among the step cut dicing processes using two types of blades with a trench etching process. In addition, by reducing physical sawing by the blade, the chipping phenomenon that may cause device defects can be reduced.

For example, a method for manufacturing a semiconductor device (1000) according to one embodiment may include the steps of preparing an n+ type substrate (100), forming an n-type layer (200) on a third direction (D3) of the n+ type substrate (100), forming a first trench (211) that is opened upward in the third direction (D3) in the n-type layer (200), forming an insulating layer (600) on an inner surface of the first trench (211), and cutting the insulating layer (600), the n-type layer (200), and the n+ type substrate (100) downward in the third direction (D3) from a lower surface of the first trench (211), thereby manufacturing a termination region (1300).

At this time, the cutting step can be performed by inserting a second blade (1402) having a width smaller than the length along the first direction (D1) of the first trench (211) into the first trench (211).

Referring to FIG. 6, by using a hard mask (M1) having openings in both the area where the second trench (212) of the conductive area (1100) is to be formed and the area where the first trench (211) of the termination area (1300) is to be formed, the first trench (211) and the second trench (212) can be formed simultaneously in one process.

The step of forming the insulating layer (600) may include a step of forming a buffer layer (610), a step of forming a gate insulating film (620), a step of forming an intermetallic insulating film (630), or a combination thereof.

In a method for manufacturing a semiconductor device (1000) according to a conventional technology, the first dicing line is formed using a first blade (1401), so the insulating layer (600) inside the first dicing line is removed.

On the other hand, in the method for manufacturing a semiconductor device (1000) according to one embodiment, since the insulating layer (600) is formed after the first trench (211) is formed, the insulating layer (600) remains within the step portion (1310).

Hereinafter, with reference to FIGS. 1 and 6, a method for manufacturing a semiconductor device illustrated in FIG. 1 will be described.

After preparing an n+ type substrate (100), an n-type layer (200) is formed on the upper surface of the n+ type substrate (100).

The n+ type substrate (100) and the n-type layer (200) include a conducting region (1100), a connecting region (1200), and a termination region (1300). The n-type layer (200) can be formed by epitaxial growth or implantation of n-type ions.

A p-type region (400) is formed in the conducting region (1100) and the connecting region (1200), and a p-type termination structure (450) is formed in the termination region (1300). The p-type region (400) is formed by injecting p-type ions into the upper portion of the n-type layer (200). The p-type region (400) located adjacent to the termination region (1300) is formed to extend to the connecting region (1200), and is formed to be spaced apart from the p-type termination structure (450).

The p-type termination structure (450) is formed by injecting p-type ions into the upper surface of the n-type layer (200) of the termination region (1300). The p-type termination structure (450) includes a plurality of regions into which p-type ions are injected, and the regions into which p-type ions are injected are spaced apart from each other by a predetermined interval.

A p-type region (400) may also be formed in the region where the second trench (212) is to be formed. In this case, the second trench (212) is formed by etching the n-type layer (200) and the p-type region (400) of the conductive region (1100). At this time, the first trench (211) may be formed together in the termination region (1300). A wet etch may be used as a method of etching the n-type layer (200) and the p-type region (400).

When forming the first trench (211) and the second trench (212), a hard mask (M1) can be formed on the n-type layer (200) and the p-type region (400) except for the region where the first trench (211) and the second trench (212) are to be formed. The hard mask (M1) can include, for example, Si ₂ N ₃ .

A buffer layer (610) is formed on the n-type layer (200) of the p-type termination structure (450) and the termination region (1300), and a gate insulating film (620) is formed inside the first trench (211) and the second trench (212).

Next, a gate electrode (700) is formed on the gate insulating film (620), and a lower gate runner (750) is formed on the buffer layer (610).

Next, an intermetallic insulating film (630) is formed over the gate electrode (700) and the lower gate runner (750).

A contact hole is formed to expose a part of the lower gate runner (750) to the intermetallic insulating film (630), then a source electrode (800) is formed in the conducting region (1100), and an upper gate runner (760) is formed in the connecting region (1200). Then, a drain electrode (900) is formed on the lower surface of the n+ type substrate (100).

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also fall within the scope of the present invention.

1000: Semiconductor Device 1000_P: Spare Semiconductor Device
1100: Current zone 1200: Connection zone
1300: End zone
1310: Step section 1320: Slope section
1401: 1st Blade 1402: 2nd Blade
1500: Wafer holding parts
100: n+ type substrate
200: n-type layer
211: Trench 1 212: Trench 2
400: p-type region 450: p-type termination structure
600: Insulating layer 610: Buffer layer
620: Gate insulating film 630: Intermetal insulating film
700: Gate electrode
750: Lower Gate Runner 760: Upper Gate Runner
800: Source electrode 900: Drain electrode
810: Anode electrode 910: Cathode electrode
M1: Hard Mask

Claims (16)

A current-carrying region extending in a first direction and a second direction intersecting the first direction, and a terminal region located at the end of the current-carrying region in the first direction,
The above terminal area is,
An n+ type substrate extending in the first direction and the second direction,
an n-type layer positioned on a third direction intersecting the first direction and the second direction of the n+ type substrate, and
Including an insulating layer positioned on the third direction of the n-type layer,
The above n-type layer has a length along the third direction at any point greater than the length along the third direction at the end of the first direction.
Semiconductor devices. In paragraph 1,
A semiconductor device, wherein the n-type layer has a step portion with a different length in the third direction at the end in the first direction. In paragraph 1,
A semiconductor element, wherein the insulating layer is also positioned on the third direction of the step portion. In paragraph 1,
A semiconductor device, wherein the n-type layer has a sloped portion whose length gradually decreases in the third direction at the end of the first direction. In paragraph 1,
A semiconductor device, wherein the insulating layer includes a buffer layer, a gate insulating film, an intermetallic insulating film, or a combination thereof. In paragraph 1,
The above-mentioned transmission area is,
An n+ type substrate extending in the first direction and the second direction,
An n-type layer positioned above the third direction of the n+ type substrate and having a trench opening upward in the third direction,
A p-type region located within the above n-type layer,
a gate electrode positioned within the trench, and
A semiconductor device comprising a source electrode and a drain electrode arranged to be insulated from the gate electrode. In paragraph 1,
A semiconductor device, wherein the above-mentioned conducting region further includes: a gate insulating film positioned between the trench and the gate electrode; an intermetallic insulating film positioned between the source electrode or the drain electrode and the gate electrode; or a combination thereof. In paragraph 1,
The above-mentioned transmission area is,
An n+ type substrate extending in the first direction and the second direction,
An n-type layer positioned above the third direction of the n+ type substrate and having a trench opening upward in the third direction,
A p-type region located within the above n-type layer,
an anode electrode positioned within the trench, and
A semiconductor device comprising a cathode electrode arranged insulated from the anode electrode. In paragraph 1,
The semiconductor device further includes a connection region positioned between the first direction of the conducting region and the termination region,
The above connection area is,
An n+ type substrate extending in the first direction and the second direction,
An n-type layer positioned on the third direction of the n+ type substrate;
A p-type region located within the above n-type layer,
a lower gate runner positioned above the p-type region and connected to the gate electrode, and
A semiconductor device comprising an upper gate runner positioned above the lower gate runner. In Article 9,
The above connection area is,
A buffer layer positioned between the p-type region and the lower gate runner;
A gate insulating film positioned between the p-type region and the lower gate runner;
A semiconductor device further comprising: the lower gate runner; and an intermetallic insulating film positioned over the buffer layer or the gate insulating film, exposing a portion of the lower gate runner; or a combination thereof. A step of preparing an n+ type substrate extending in a first direction and a second direction intersecting the first direction,
A step of forming an n-type layer on a third direction intersecting the first direction and the second direction of the n+ type substrate,
A step of forming a first trench opening upward in the third direction in the n-type layer;
A step of forming an insulating layer on the inner surface of the first trench, and
A step of cutting the insulating layer, the n-type layer, and the n+ type substrate downward in the third direction from the lower surface of the first trench.
A method for manufacturing a semiconductor device, comprising a step of manufacturing a terminal region including a . In Article 11,
A method for manufacturing a semiconductor device, wherein the cutting step is performed by inserting a blade having a width smaller than a length of the first trench in the first direction into the first trench. In Article 11,
A method for manufacturing a semiconductor device, wherein the step of forming the insulating layer includes a step of forming a buffer layer, a step of forming a gate insulating film, a step of forming an intermetallic insulating film, or a combination thereof. In Article 13,
The method for manufacturing the above semiconductor device is:
A step of forming a second trench opening upward in the third direction in the n-type layer;
A step of forming the gate insulating film inside the second trench;
A step of forming a gate electrode inside the second trench;
A step of forming the intermetallic insulating film on the gate electrode;
A step of forming a source electrode and a drain electrode so as to be insulated from the gate electrode
A method for manufacturing a semiconductor device, further comprising a manufacturing step of a conductive region including a . In Article 14,
A method for manufacturing a semiconductor device, wherein the first trench and the second trench are formed simultaneously in one process. In Article 13,
The method for manufacturing the above semiconductor device is:
A step of forming a p-type region within the above n-type layer;
A step of forming the buffer layer on the p-type region;
A step of forming the gate insulating film on the buffer layer,
A step of forming a lower gate runner located on the gate insulating film and connected to the gate electrode;
a step of forming the intermetallic insulating film covering a portion of the lower gate runner, and
A step of forming an upper gate runner positioned on the intermetal insulating film and connected to the lower gate runner exposed between the intermetal insulating films,
A method for manufacturing a semiconductor device, further comprising a manufacturing step of a connection region.