KR20240177682A - Semiconductor package and method of manufacturing the semiconductor package - Google Patents

Abstract

A semiconductor package comprises: a lower package having a first lower package side surface orthogonal to an upper surface and extending in a first direction, and a second lower package side surface facing the first lower package side surface; an upper package which comprises a first upper package side surface stacked on the lower package through conductive connection members and extending in the first direction, and a second upper package side surface facing the first upper package side surface, wherein the first upper package side surface is located on the same plane as the first lower package side surface of the lower package, and the second upper package side surface is disposed to be spaced apart from the second lower package side surface by a predetermined distance to define an underfill area on the upper surface of the lower package; and an underfill member extending from the underfill area on the upper surface of the lower package to a space between the lower package and the upper package.

Description

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a POP (Package On Package) type stacked semiconductor package in which packages are stacked on top of each other, and a method for manufacturing the same.

Due to the advancement, speed, and miniaturization of electronic components such as mobile products, a method of stacking packages on top of packages has become a semiconductor mounting technology. In a package on package (PoP) device, an upper package can be mounted on a lower package via conductive connecting members such as solder balls. After the package is mounted on a board, joint cracks of the conductive connecting members occur due to thermal stress, which deteriorates board level reliability, and improvement in the thermal resistance of the processor chip of the lower package is required.

An object of the present invention is to provide a semiconductor package having improved board level reliability and improved heat dissipation characteristics.

Another object of the present invention is to provide a method for manufacturing the semiconductor package described above.

According to exemplary embodiments for achieving the above object of the present invention, a semiconductor package includes a lower package having a first lower package side surface extending in a first direction perpendicular to an upper surface and a second lower package side surface facing the first lower package side surface, an upper package having a first upper package side surface extending in the first direction and a second upper package side surface facing the first upper package side surface, which are laminated on the lower package via conductive connection members, the first upper package side surface being positioned on the same plane as the first lower package side surface of the lower package and the second upper package side surface being spaced apart from the second lower package side surface by a preset distance, thereby defining an underfill region on the upper surface of the lower package, and an underfill member extending from the underfill region on the upper surface of the lower package into a space between the lower package and the upper package.

According to exemplary embodiments for achieving the above object of the present invention, a semiconductor package includes a lower package having a first lower package side surface having a first planar area and extending in a first direction perpendicular to an upper surface and a second lower package side surface facing the first lower package side surface, an upper package laminated on the lower package via conductive connecting members and having a second planar area smaller than the first planar area and extending in the first direction and a second upper package side surface facing the first upper package side surface, the upper package having a center position shifted and aligned in a second direction perpendicular to the first direction with respect to a center of the lower package to define an underfill area between the second upper package side surface and the second lower package side surface on the upper surface of the lower package, and an underfill member extending in a horizontal direction from the underfill area on the upper surface of the lower package and filling between the lower package and the upper package.

According to exemplary embodiments for achieving the above object of the present invention, a semiconductor package includes a lower package having a first planar area, a first lower package side surface extending in a first direction perpendicular to an upper surface, and a second lower package side surface facing the first lower package side surface; an upper package having a second planar area smaller than the first planar area, and a first upper package side surface extending in the first direction and a second upper package side surface facing the first upper package side surface, the upper package having a center position shifted and aligned in a second direction perpendicular to the first direction with respect to a center of the lower package to define an underfill area between the second upper package side surface and the second lower package side surface on the upper surface of the lower package; and an underfill member extending in a horizontal direction from the underfill area on the upper surface of the lower package and filling between the lower package and the upper package. The lower package includes a first package substrate, at least one first semiconductor chip mounted on the first package substrate, vertical conductive connectors disposed on the first package substrate and electrically connected to the at least one first semiconductor chip, a first sealing member covering the at least one first semiconductor chip on the first package substrate and exposing one end of the vertical conductive connectors, and an interposer electrically connected to the vertical conductive connectors on the first sealing member and having upper connection pads. The conductive connection members are respectively disposed on the upper connection pads of the interposer. The first upper package side surface of the upper package and the first lower package side surface of the lower package are positioned on the same plane.

According to exemplary embodiments, a semiconductor package may include a lower package having a first planar area, an upper package laminated on the lower package via conductive connecting members and having a second planar area smaller than the first planar area, and an underfill member interposed between the lower package and the upper package. The upper package may be arranged asymmetrically on the lower package to define an underfill region on an upper surface of the lower package.

After mounting the upper package on the lower package at the board level, a liquid underfill material can be dispensed between the lower package and the upper package using the underfill area to form the underfill material. Accordingly, the underfill material can prevent joint cracks of the conductive connecting members and serve as a heat dissipation passage for heat dissipation of the processor chip of the lower package. Accordingly, the board level TC reliability and heat dissipation characteristics of the semiconductor package can be improved.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded within a scope that does not depart from the spirit and scope of the present invention.

FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments.
Figure 2 is a plan view of Figure 1.
Figure 3 is a plan view showing the lower package of Figure 1.
FIGS. 4 to 12 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.
FIG. 13 is a cross-sectional view showing a semiconductor package according to exemplary embodiments.
Figure 14 is an enlarged cross-sectional view of portion D of Figure 13.
FIG. 15 is a plan view showing a semiconductor package according to exemplary embodiments.
FIG. 16 is a cross-sectional view showing a semiconductor package according to exemplary embodiments.
FIGS. 17 to 25 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

Hereinafter, with reference to the attached drawings, a preferred embodiment of the present invention will be described in more detail.

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments. FIG. 2 is a plan view of FIG. 1. FIG. 3 is a plan view illustrating a lower package of FIG. 1. FIG. 3 is a plan view illustrating a state in which an upper package and conductive connecting members are removed from FIG. 2. FIG. 1 includes a cross-sectional portion taken along line A-A' of FIG. 2 and a cross-sectional portion taken along line B-B' of FIG. 3.

Referring to FIGS. 1 to 3, a semiconductor package (10) may include a lower package (P1), an upper package (P2) laminated on the lower package (P1) via conductive connecting members (650), and an underfill member (700) interposed between the lower package (P1) and the upper package (P2). In addition, the semiconductor package (10) may further include external connecting members (180) provided on a lower surface of the lower package (P1).

In addition, the semiconductor package (10) may be a multi-chip package (MCP) that includes different types of semiconductor chips. The semiconductor package (10) may be a system in package (SIP) that integrates semiconductor chips (e.g., memory chips and logic chips) that perform multiple functions in one package.

In exemplary embodiments, the lower package (P1) may include a first package substrate (100), at least one first semiconductor chip (200) mounted on the first package substrate (100), vertical conductive connectors (350) disposed on the first package substrate (100) and electrically connected to the at least one first semiconductor chip (200), a first sealing member (300) covering the at least one first semiconductor chip (200) on the first package substrate (100) and exposing one end of the vertical conductive connectors (350), and an interposer (400) electrically connected to the vertical conductive connectors (350) on the first sealing member (300).

The first package substrate (100) may be a substrate having an upper surface (101a) and a lower surface (101b) facing each other. For example, the first package substrate (100) may include a printed circuit board (PCB), a flexible substrate, a tape substrate, etc. The printed circuit board may be a multilayer circuit board having vias and various circuits therein.

The first package substrate (100) may include a plurality of stacked insulating layers (110) and wirings provided on each of the insulating layers. In addition, the first package substrate (100) may include a plurality of upper substrate pads (130) and a plurality of lower substrate pads (140). The wirings may include internal wirings as channels for electrical connection with different types of semiconductor chips.

The upper substrate pads (130) may be provided to be exposed from the upper surface (101a) of the first package substrate (100). The first upper insulating film (150) may be provided on the insulating layers and may expose at least some portions of the upper substrate pads (130). The lower substrate pads (140) may be provided to be exposed from the lower surface (101b) of the first package substrate (100). The lower insulating film (160) may be provided on the insulating layers and may expose at least some portions of the lower substrate pads (140).

In exemplary embodiments, the upper substrate pads (130) may include first substrate pads (130a) arranged in a central region of the first package substrate (100), i.e., a chip mounting region, and second substrate pads (130b) arranged in an edge region surrounding the chip mounting region. The first substrate pads (130a) may be arranged in an array form in the chip mounting region.

The first semiconductor chip (200) may be mounted on the chip mounting area (MR) of the first package substrate (100) via conductive bumps (220). The first semiconductor chip (200) may be placed such that the front surface, i.e., the active surface, on which the first chip pads (210) are formed faces the substrate (S). The first semiconductor chip (200) may have a rectangular shape with four sides when viewed in a plan view. The first chip pads (210) may be arranged in an array form on the entire front surface of the first semiconductor chip (200).

The first semiconductor chip (200) may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory chips. The first semiconductor chip may be a processor chip such as an ASIC or an AP (Application Processor) as a host such as a CPU, GPU, or SOC.

A first semiconductor chip (200) may be mounted on a first package substrate (100) by a flip chip bonding method. First chip pads (210) of the first semiconductor chip (200) may be electrically connected to first substrate pads (130a) of the first package substrate (100) by conductive bumps (220). For example, the conductive bumps (230) may include micro bumps (uBumps).

Additionally, an underfill member (230) may be underfilled between the first semiconductor chip (200) and the first package substrate (100). The underfill member may include a material having relatively high fluidity to effectively fill a small space between the first semiconductor chip and the substrate. For example, the underfill member may include an adhesive including an epoxy material.

The vertical conductive connectors (350) may be formed on the upper substrate pads (130) of the first package substrate (100), respectively. The vertical conductive connector (350) may extend in a vertical direction from the upper substrate pads (130) of the first package substrate (100). The vertical conductive connector (350) may include a solder ball. The vertical conductive connectors (350) may be electrically connected to the first semiconductor chip (200) by the wirings of the package substrate (100).

The height from the upper surface (101a) of the first package substrate (100) of the vertical conductive connector (350) may be greater than or equal to the height from the upper surface (101a) of the first package substrate (100) of the first semiconductor chip (200).

A first sealing member (300) may be provided to cover a first semiconductor chip (200) on a first package substrate (100). The first sealing member (300) may fill a space between vertical conductive connectors (350). The first sealing member (300) may expose one end of the vertical conductive connectors (350). The first sealing member (300) may include an epoxy mold compound (EMC).

An interposer (400) may be provided on the first sealing member (300). The interposer (400) may be a silicon interposer or a redistribution interposer having a plurality of wires formed therein. For example, the interposer (400) may include a plurality of insulating layers (410a, 410b, 410c) and wires provided in the insulating layers. The upper bonding pads (430) may be provided to be exposed from an upper surface (401a) of the interposer (400). The third insulating layer (410c) may expose at least some portions of the upper bonding pads (430). The lower bonding pads (440) may be provided to be exposed from an lower surface (401b) of the interposer (400). The first insulating layer (410a) may expose at least some portions of the lower bonding pads (440).

One end of the vertical conductive connectors (350) exposed by the first sealing member (300) can be bonded to the lower bonding pads (440) of the interposer (400). The vertical conductive connector (350) can extend vertically from the upper substrate pad (130) of the first package substrate (100) to the lower bonding pad (440) of the interposer (400).

As illustrated in FIG. 3, the lower package (P1) may have a rectangular shape having four sides when viewed in a plan view. The lower package (P1) may include a first lower package side (S11) and a second lower package side (S12) extending in a direction orthogonal to the upper surface (401a) and parallel to the second direction (Y direction) and facing each other, and a third lower package side (S13) and a fourth lower package side (S14) extending in a direction parallel to the first direction (X direction) orthogonal to the second direction and facing each other. The lower package (P1) may have a first planar area. For example, a width of the lower package (P1) in the first direction, that is, a distance between the first lower package side (S11) and the second lower package side (S12), may be 14.1 mm.

The lower package (P1) may include an upper surface (401a), that is, an upper surface (401a) of the interposer (400), which may include an upper package region (UPR) and an underfill region (DPR). Upper bonding pads (430) of the interposer (400) may be arranged within the upper package region (UPR). One side of the upper package region (UPR) may overlap with a first lower package side surface (S11). The underfill region (DPR) may extend along a second lower package side surface (S12) on one side of the upper package region (UPR). One side of the underfill region (DPR) may overlap with the second lower package side surface (S12). A length (L1) of the underfill region (DPR) in the first direction may be at least 0.5 mm.

In exemplary embodiments, the upper package (P2) may be mounted on the lower package (P1) via conductive connecting members (650).

The upper package (P2) may include a second package substrate (610), at least one second semiconductor chip (620a, 620b) mounted on an upper surface of the second package substrate (610), second conductive connecting members (630) electrically connecting second chip pads (622a, 622b) of the at least one second semiconductor chip (620a, 620b) to upper substrate pads (612) on an upper surface of the second package substrate (610), and a second sealing member (640) covering the at least one second semiconductor chip (620a, 620b) on the second package substrate (610).

A plurality of second semiconductor chips (620a, 620b) can be sequentially stacked on a second package substrate (610) by adhesive members. Bonding wires (630) of the second conductive connecting members can connect second chip pads (622a, 622b) of the second semiconductor chips (620a, 620b) to upper substrate pads (612) of the second package substrate (610).

The upper package (P2) includes two semiconductor chips mounted by a wire bonding method, but it will be understood that the number of the second semiconductor chips in the upper package, the mounting method, etc. are not limited thereto.

The second semiconductor chip (620a, 620b) may include a memory chip including a memory circuit. For example, the second semiconductor chip may include a volatile memory device such as an SRAM device, a DRAM device, and the like, and a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, and the like.

Conductive connecting members (650) may be interposed between the lower package (P1) and the upper package (P2) to electrically connect them. A gap may be formed between the upper package (P2) and the lower package (P1) by the conductive connecting members (650). The conductive connecting members (650) may be interposed between the upper bonding pads (430) arranged in the upper package region (UPR) of the lower package (P1) and the lower substrate pads (614) of the second package substrate (610) of the upper package (P2), respectively.

As illustrated in FIG. 2, the upper package (P2) may have a rectangular shape having four sides when viewed in a plan view. The upper package (P2) may include a first upper package side surface (S21) and a second upper package side surface (S21) that extend in a direction perpendicular to the upper surface and parallel to the second direction (Y direction) and face each other. The upper package (P2) may have a second planar area smaller than the first planar area of the lower package (P1). For example, the width of the upper package (P2) in the first direction, that is, the distance between the first upper package side surface (S21) and the second upper package side surface (S22), may be 12.4 mm.

The upper package (P1) can be arranged asymmetrically on the lower package (P2). The upper package (P2) can be placed on an upper package region (UPR) of the lower package (P1). A first upper package side surface (S21) of the upper package (P2) is positioned on the same plane as a first lower package side surface (S11) of the lower package (P1), and a second upper package side surface (S22) is placed apart from the second lower package side surface (12) by a first distance (L1) set in advance, so that the upper package (P2) can define an underfill region (DPR) on an upper surface of the lower package (P1). The position of the center (C2) of the upper package (P2) may be shifted in the first direction (-X direction) with respect to the center (C1) of the lower package (P1) to provide an underfill region (DPR) between the second upper package side (S22) and the second lower package side (S12) on the upper surface (401a) of the lower package (P1). The center (C2) of the upper package (P2) may be spaced apart from the center (C1) of the lower package (P1) by a preset second distance (L2). For example, the second distance (L2) may be smaller than the first distance (L1). The second distance (L2) may be half of the first distance (L1).

In exemplary embodiments, an underfill member (700) may be provided between the lower package (P2) and the upper package (P1). The underfill member (700) may include a horizontal extension portion (710a) extending horizontally from the underfill region (DPR) and filling a space between the lower package (P1) and the upper package (P2), and a vertical extension portion (710b) extending vertically from the underfill region (DPR) and covering at least a portion of a second upper package side surface (S22) of the upper package (P2). For example, the underfill member (700) may include a thermosetting resin, such as an epoxy resin.

Additionally, the lower package (P1) may include a dam structure (450) extending along one side of the underfill region (DPR) on the upper surface (401a) of the interposer (400). The dam structure (450) may have a preset height on the upper surface (401a) of the interposer (400). The dam structure (450) may extend along the second direction (Y direction) to be adjacent to the second lower package side surface (S12) within the underfill region (DPR) on the upper surface of the lower package (P1).

The dam structure (450) may be in contact with a portion of the outer surface of the underfill member (700). The dam structure (450) may prevent the underfill member dispensed in the underfill region (DPR) on the upper surface (401a) of the interposer (400) from flowing out through the second lower package side (S12).

In exemplary embodiments, external connection members (180) may be arranged on lower substrate pads (140) on the lower surface (101b) of the first package substrate (100) for electrical connection with an external device. For example, the external connection members (180) may be solder balls. The semiconductor package (10) may be mounted on a module substrate (not shown) via the solder balls to form a semiconductor module.

As described above, the semiconductor package (10) may include a lower package (P1) having a first planar area, an upper package (P2) laminated on the lower package (P1) via conductive connecting members (650) and having a second planar area smaller than the first planar area, and an underfill member (700) interposed between the lower package (P1) and the upper package (P2). The upper package (P2) may be arranged asymmetrically on the lower package (P1). A second upper package side surface (S22) of the upper package (P2) may be arranged to be spaced apart from a second lower package side surface (S12) of the lower package (P1) by a preset distance (L1) to define an underfill region (DPR) on an upper surface of the lower package (P1).

After mounting the upper package (P2) on the lower package (P1) at the board level, a liquid underfill material can be dispensed between the lower package (P1) and the upper package (P2) using the underfill region (DPR) to form an underfill material (700). Accordingly, the underfill material (700) can prevent joint cracks of conductive connecting members (650) and serve as a heat dissipation passage for heat dissipation of the processor chip (200) of the lower package (P1). Accordingly, the board level TC reliability of the semiconductor package (10) can be improved and the heat dissipation characteristics can be enhanced.

Below, a method for manufacturing the semiconductor package of Fig. 1 will be described.

FIGS. 4 to 12 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 4 to 8 and FIGS. 10 to 12 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 9 is a plan view of FIG. 8. FIG. 8 is a cross-sectional view taken along line C-C' of FIG. 9.

Referring to FIG. 4, a substrate (S) on which first package substrates are formed is provided, and at least one first semiconductor chip (200) can be mounted on the first package substrate.

In exemplary embodiments, the substrate (S) may be a multilayer circuit board having upper surfaces (101a) and lower surfaces (101b) facing each other. The substrate (S) may be a strip substrate for manufacturing a semiconductor strip, such as a printed circuit board (PCB). For example, the substrate (S) may include a printed circuit board (PCB), a flexible substrate, a tape substrate, or the like. The printed circuit board may be a multilayer circuit board having vias and various circuits therein.

The substrate (S) may include a package region (PR) on which a semiconductor chip is mounted and a cut region (CR) surrounding the package region (PR). As described below, after a plurality of semiconductor chips are respectively placed on the package regions (PR) of the substrate (S), the substrate (S) may be cut along the cut region (SR) that separates the package regions (PR) to be individualized into package substrates.

The substrate (S) may include a plurality of laminated insulating layers (110) and wirings provided on each of the insulating layers. In addition, the substrate (S) may include a plurality of upper substrate pads (130) and a plurality of lower substrate pads (140). The wirings may include internal wirings as channels for electrical connection with the first semiconductor chip (200).

For example, the insulating layers (110) may include a core layer, a first insulating layer provided on an upper surface of the core layer, and a second insulating layer provided on a lower surface of the core layer. The wirings may include a through via penetrating the core layer, an upper conductive pattern provided on an upper surface of the core layer, and a lower conductive pattern provided on a lower surface of the core layer.

The core layer may include a non-conductive material layer. The core layer may include a reinforced polymer, etc. The through via may electrically connect the upper conductive pattern and the lower conductive pattern by penetrating the core layer.

The upper substrate pads (130) may be provided to be exposed from the upper surface (101a) of the substrate (S). The upper substrate pads (130) may be provided on the first insulating layer and may be electrically connected to the upper conductive patterns. The first upper insulating film (150) may be provided on the first insulating layer and may expose at least a portion of the upper substrate pads (130).

The lower substrate pads (140) may be provided to be exposed from the lower surface (101b) of the substrate (100). The lower substrate pads (134) may be provided on the second insulating layer and may be electrically connected to the lower conductive patterns. The lower insulating film (160) may be provided on the second insulating layer and may expose at least a portion of the lower substrate pads (140).

For example, the first and second insulating layers may include an insulating material, such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. The first and second insulating layers may include a resin impregnated in a core material such as an organic fiber (glass fiber), such as a prepreg, FR-4, BT (Bismaleimide Triazine), etc. The upper insulating film and the lower insulating film may include a solder resist, etc.

In exemplary embodiments, the upper substrate pads (130) may include first substrate pads (130a) arranged in a central region of the package region (PR), i.e., a chip mounting region (MR), and second substrate pads (130b) arranged in an edge region surrounding the chip mounting region. The first substrate pads (130a) may be arranged in an array form in the chip mounting region.

Next, at least one first semiconductor chip (200) can be mounted on the package area (PR) of the substrate (S).

In exemplary embodiments, the first semiconductor chip (200) may be mounted on a chip mounting area (MR) of a substrate (S) via conductive bumps (220). The first semiconductor chip (200) may be placed such that the front surface (202), i.e., the active surface, on which the first chip pads (210) are formed faces the substrate (S). The first semiconductor chip (200) may have a rectangular shape with four side surfaces when viewed in a plan view. The first chip pads (210) may be arranged in an array form on the entire front surface (202) of the first semiconductor chip (200).

The first semiconductor chip (200) may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory chips. The first semiconductor chip may be a processor chip such as an ASIC or an AP (Application Processor) as a host such as a CPU, GPU, or SOC.

The first semiconductor chip (200) may be mounted on a substrate (S) by a flip chip bonding method. The first chip pads (210) of the first semiconductor chip (200) may be electrically connected to the first substrate pads (130a) of the substrate (S) by conductive bumps (220). For example, the conductive bumps (230) may include micro bumps (uBumps). The thickness of the first semiconductor chip (200) may be within a range of 40 μm to 110 μm.

Additionally, an underfill member (230) may be underfilled between the first semiconductor chip (200) and the substrate (S). The underfill member may include a material having relatively high fluidity to effectively fill a small space between the first semiconductor chip and the substrate. For example, the underfill member may include an adhesive including an epoxy material.

Referring to FIGS. 5 and 6, an interposer (400) can be placed on a substrate (S) via vertical conductive connectors (350).

As illustrated in FIG. 5, vertical conductive connectors (350) can be formed on lower bonding pads (440) on the lower surface (401b) of the interposer (400), and placed on the substrate (S) so that the vertical conductive connectors (350) face the substrate (S).

The interposer (400) may be a silicon interposer or a redistribution interposer having a plurality of wires formed therein. For example, the interposer (400) may include a plurality of insulating layers (410a, 410b, 410c) and wires provided within the insulating layers. The upper bonding pads (430) may be provided to be exposed from the upper surface (401a) of the interposer (400). The third insulating layer (410c) may expose at least some portions of the upper bonding pads (430). The lower bonding pads (440) may be provided to be exposed from the lower surface (401b) of the interposer (400). The first insulating layer (410a) may expose at least some portions of the lower bonding pads (440).

The vertical conductive connectors (350) may be formed on the lower bonding pads (440), respectively. The vertical conductive connector (350) may extend vertically from the lower bonding pad (440). The vertical conductive connector (350) may include a solder ball.

In exemplary embodiments, the interposer (400) may include a dam structure (450) extending along one side of the cut region (CR) on the upper surface (401a) of the interposer (400). The dam structure (450) may have a preset height on the upper surface (401a) of the interposer (400). As described below, the dam structure (450) may prevent an underfill material dispensed on the upper surface (401a) of the interposer (400) from flowing out to the outside.

As illustrated in FIG. 6, vertical conductive connectors (350) may be respectively arranged on second substrate pads (130b) of a substrate (S) by a solder ball attach process. The vertical conductive connectors (350) on the interposer (400) may be thermally bonded on an upper surface (101a) of the substrate (S). The vertical conductive connectors (350) may be bonded to the second substrate pads (130b) by a reflow process. The vertical conductive connectors (350) may be electrically connected to the first semiconductor chip (200) by the wirings of the substrate (S).

The height of the vertical conductive connector (350) from the upper surface (101a) of the substrate (S) may be greater than the height from the upper surface (101a) of the substrate (S) of the first semiconductor chip (200). Accordingly, the interposer (400) is supported on the substrate (S) by the vertical conductive connectors (350), and the lower surface (401b) of the interposer (400) may be spaced apart from the rear surface (204) of the first semiconductor chip (200) and the upper surface (101a) of the substrate (S), so that a space may be formed between the substrate (S) and the interposer (400).

Referring to FIG. 7, a first sealing member (300) covering a first semiconductor chip (200) can be formed on a substrate (S).

For example, a first sealing member (300) covering a first semiconductor chip (200) may be formed by injecting a molding material between a substrate (S) and an interposer (400) by a transfer molding process. The first sealing member (300) may fill a space between vertical conductive connectors (350). The first sealing member (300) may include an epoxy mold compound (EMC). The first sealing member (300) may include a UV resin, a polyurethane resin, a silicone resin, a silica filler, or the like.

Referring to FIGS. 8 and 9, external connection members (180) are respectively placed on lower substrate pads (140) on the lower surface (101b) of the substrate (S), and the substrate (S) can be diced to form individual lower packages (P1).

In exemplary embodiments, solder balls may be arranged as the external connection members on lower substrate pads (140) on a lower surface (101b) of the substrate (S). Subsequently, the substrate (S) may be cut along a cutting area (CR) that separates a plurality of package areas (PR) by a sawing process to be individualized into a plurality of lower packages (P1).

The lower package (P1) may include a first package substrate (100), at least one first semiconductor chip (200) mounted on the first package substrate (100), vertical conductive connectors (350) disposed on the first package substrate (100) and electrically connected to the at least one first semiconductor chip (200), a first sealing member (300) covering the at least one first semiconductor chip (200) on the first package substrate (100) and exposing one end of the vertical conductive connectors (350), and an interposer (400) electrically connected to the vertical conductive connectors (350) on the first sealing member (300).

As illustrated in FIG. 9, the lower package (P1) may have a rectangular shape having four sides when viewed in a plan view. The lower package (P1) may include a first lower package side (S11) and a second lower package side (S12) that extend in a direction orthogonal to the upper surface (401a) and parallel to the second direction (Y direction) and face each other, and a third lower package side (S13) and a fourth lower package side (S14) that extend in a direction parallel to the first direction (X direction) orthogonal to the second direction and face each other. The lower package (P1) may have a first planar area. For example, a width of the lower package (P1) in the first direction, that is, a distance between the first lower package side (S11) and the second lower package side (S12), may be 14.1 mm.

The lower package (P1) may include an upper package region (UPR) and an underfill region (DPR) on the upper surface (401a), i.e., the upper surface (401a) of the interposer (400). Upper bonding pads (430) of the interposer (400) may be arranged in the upper package region (UPR). One side of the upper package region (UPR) may overlap with the first lower package side surface (S11). The underfill region (DPR) may extend along the second lower package side surface (S12) on one side of the upper package region (UPR). One side of the underfill region (DPR) may overlap with the second lower package side surface (S12). A length (L1) of the underfill region (DPR) in the first direction may be at least 0.5 mm.

Referring to FIG. 10, an upper package (P2) can be laminated on a lower package (P1) via conductive connecting members (650).

In exemplary embodiments, the upper package (P2) may include a second package substrate (610), at least one second semiconductor chip (620a, 620b) mounted on an upper surface of the second package substrate (610), second conductive connecting members (630) electrically connecting second chip pads (622a, 622b) of the at least one second semiconductor chip (620a, 620b) to upper substrate pads (612) on an upper surface of the second package substrate (610), and a second sealing member (640) covering the at least one second semiconductor chip (620a, 620b) on the second package substrate (610).

A plurality of second semiconductor chips (620a, 620b) can be sequentially stacked on a second package substrate (610) by adhesive members. Bonding wires (630) of the second conductive connecting members can connect second chip pads (622a, 622b) of the second semiconductor chips (620a, 620b) to upper substrate pads (612) of the second package substrate (610).

The upper package (P2) includes two semiconductor chips mounted by a wire bonding method, but it will be understood that the number of the second semiconductor chips in the upper package, the mounting method, etc. are not limited thereto.

The second semiconductor chip (620a, 620b) may include a memory chip including a memory circuit. For example, the second semiconductor chip may include a volatile memory device such as an SRAM device, a DRAM device, and the like, and a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, and the like.

In exemplary embodiments, solder balls as the conductive connecting members are respectively formed on the lower substrate pads (614) of the lower surface of the package substrate (610) of the upper package (P2) by a solder ball attach process, and then the upper package (P2) can be mounted on the lower package (P1) via the conductive connecting members.

Conductive connecting members (650) can be interposed between the lower package (P1) and the upper package (P2) to electrically connect them. A gap (G) can be formed between the upper package (P2) and the lower package (P1) by the conductive connecting members (650). The conductive connecting members (650) formed on the lower substrate pads (614) of the second package substrate (610) of the lower package (P1) can be bonded to the upper bonding pads (430) arranged within the upper package region (UPR) of the interposer (400).

The upper package (P2) may have a rectangular shape having four sides when viewed in a plan view. The upper package (P2) may include a first upper package side surface (S21) and a second upper package side surface (S21) that extend in a direction perpendicular to the upper surface and parallel to the second direction (Y direction) and face each other. The upper package (P2) may have a second planar area smaller than the first planar area. For example, the width of the upper package (P2) in the first direction, that is, the distance between the first upper package side surface (S21) and the second upper package side surface (S22), may be 12.4 mm.

The upper package (P2) can be placed on the upper package region (UPR) of the lower package (P1). The first upper package side surface (S21) of the upper package (P2) is positioned on the same plane as the first lower package side surface (S11) of the lower package (P1), and the second upper package side surface (S22) is positioned spaced apart from the second lower package side surface (12) by a preset distance (L1), so that the upper package (P2) can expose an underfill region (DPR) on the upper surface of the lower package (P1). The position of the center of the upper package (P2) can be shifted in the first direction (-X direction) with respect to the center (C1) of the lower package (P1) to provide an underfill region (DPR) between the second upper package side surface (S22) and the second lower package side surface (S12) on the upper surface (401a) of the lower package (P1).

In this case, the dam structure (450) can extend along the second direction (Y direction) adjacent to the second lower package side (S12) within the underfill region (DPR) on the upper surface of the lower package (P1).

Referring to FIGS. 11 and 12, an underfill member (700) can be formed between the lower package (P2) and the upper package (P1).

As illustrated in FIG. 11, a liquid underfill solution (70) may be dispensed into a gap (G) between a lower package (P2) and an upper package (P1) while moving the dispenser nozzle (20) in a second direction (Y direction) along the underfill region (DPR) between the second upper package side (S22) and the second lower package side (S12). For example, the underfill solution may include an epoxy material. The underfill solution may flow from the underfill region (DPR) into the gap (G) between the lower package (P2) and the upper package (P1), and then be cured to form an underfill member (700).

At this time, the dam structure (450) can prevent the underfill solution (70) dispensed on the underfill region (DPR) on the upper surface (401a) of the interposer (400) from flowing out through the second lower package side (S12).

As illustrated in FIG. 12, the underfill member (700) may include a horizontal extension (710a) extending horizontally from the underfill region (DPR) and filling a space between the lower package (P1) and the upper package (P2), and a vertical extension (710b) extending vertically from the underfill region (DPR) and covering at least a portion of the second upper package side (S22) of the upper package (P2).

For example, the height from the upper surface of the lower package (P1) of the vertical extension (710b) may be 30% to 80% of the height from the upper surface of the lower package (P1) of the upper package (P2). The height from the upper surface of the lower package (P1) of the dam structure (450) may be within a range of 100 μm to 500 μm.

Accordingly, the upper package (P2) is mounted on the lower package (P1) at the board level, and then an underfill process is performed between the lower package (P1) and the upper package (P2) to complete the semiconductor package of Fig. 1 with secured reliability.

Fig. 13 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Fig. 14 is an enlarged cross-sectional view showing portion D of Fig. 13. The semiconductor package is substantially the same as the semiconductor package described with reference to Figs. 1 to 3 except for the configuration of the receiving groove. Accordingly, the same components are indicated by the same reference numerals, and further repetitive descriptions of the same components are omitted.

Referring to FIGS. 13 and 14, the lower package (P1) of the semiconductor package (11) may include an accommodation groove (452) extending along the second lower package side surface (S12) within an underfill region (DPR) on an upper surface (401a) of the lower package (P1). The accommodation groove (452) may have a preset depth from the upper surface (401a). The accommodation groove (452) may extend along a second direction (Y direction) adjacent to the second lower package side surface (S12) within the underfill region (DPR).

The receiving groove (452) can receive a portion of the underfill member (700). The receiving groove (452) can prevent the underfill member dispensed on the underfill region (DPR) on the upper surface (401a) of the interposer (400) from flowing out through the second lower package side (S12).

As illustrated in FIG. 14, the interposer (400) as a rewiring interposer may include first to third insulating layers (410a, 410b, 410c) sequentially laminated on a first molding member (300). The interposer (400) may include a lower connection pad (440) formed on one end of a vertical conductive connector (350) exposed by the first molding member (300) and provided in the first insulating layer (410a), and an upper bonding pad (430) provided in the third insulating layer (410c). The upper bonding pad (430) and the lower connection pad (440) may be electrically connected by a connecting wire (420).

The receiving groove (452) can be formed by performing a laser processing process on a plurality of insulating layers (410a, 410b, 410c) including the third insulating layer (410c). The receiving groove (452) can have a preset depth from the upper surface (401a) of the third insulating layer (410c). For example, the depth can be within a range of 10 μm to 250 μm.

Fig. 15 is a plan view showing a semiconductor package according to exemplary embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to Figs. 1 to 3, except for the arrangement of the upper package, the configuration of the underfill member and the dam structure. Accordingly, the same components are indicated by the same reference numerals, and further, a repeated description of the same components is omitted.

Referring to FIG. 15, the upper package (P2) can be arranged asymmetrically on the lower package (P1). The second upper package side (S22) of the upper package (P2) is spaced apart from the second lower package side (S12) of the lower package (P1) by a preset distance, and the fourth upper package side (S24) of the upper package (P2) is spaced apart from the fourth lower package side (S14) of the lower package (P1) by a preset distance and arranged so as to define an underfill region (DPR) on the upper surface of the lower package (P1). The first upper package side (S21) of the upper package (P2) can be positioned on the same plane as the first lower package side (S11) of the lower package (P1), and the third upper package side (S23) of the upper package (P2) can be positioned on the same plane as the third lower package side (S13) of the lower package (P1). An underfill region (DPR) can be defined between the second upper package side (S22) and the second lower package side (S12) on the upper surface (401a) of the lower package (P1) and between the fourth upper package side (S24) and the second lower package side (S14).

In exemplary embodiments, the lower package (P1) may include a first vertical extension (710b) that extends vertically from the underfill region (DPR) and covers at least a portion of a second upper package side (S22) of the upper package (P2) and a second vertical extension (710c) that covers at least a portion of a fourth upper package side (S24) of the upper package (P2). The first vertical extension (710b) may be provided between the second upper package side (S22) and the second lower package side (S12) on the upper surface (401a) of the lower package (P1), and the second vertical extension (710c) may be provided between the fourth upper package side (S24) and the second lower package side (S14) on the upper surface (401a) of the lower package (P1).

Additionally, the lower package (P1) may include a first dam structure (450a) extending along the second direction (Y direction) adjacent to the second lower package side (S12) within the underfill region (DPR) on the upper surface of the lower package (P1) and a second dam structure (450b) extending along the first direction (X direction) adjacent to the fourth lower package side (S14) within the underfill region (DPR). The first dam structure (450a) may contact a portion of the outer surface of the first vertical extension portion (710b), and the second dam structure (450b) may contact a portion of the outer surface of the second vertical extension portion (710c).

Fig. 16 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. The semiconductor package is substantially the same as the semiconductor package described with reference to Figs. 1 to 3, except for the configuration of the lower package. Accordingly, the same components are indicated by the same reference numerals, and a repeated description of the same components is omitted.

Referring to FIG. 16, the semiconductor package (12) may include a lower package (P1), an upper package (P2) laminated on the lower package (P1) via conductive connecting members (650), and an underfill member (700) interposed between the lower package (P1) and the upper package (P2).

In exemplary embodiments, the lower package (P1) may include a fan out package. The lower package (P1) may include a lower redistribution layer (100), at least one first semiconductor chip (200) mounted on the lower redistribution layer (100), vertical conductive pillars (360) disposed on the lower redistribution layer (100) and electrically connected to the at least one first semiconductor chip (200), a first sealing member (300) covering the at least one first semiconductor chip (200) on the lower redistribution layer (100) and exposing upper portions of the vertical conductive pillars (360), and an upper redistribution layer (400) electrically connected to the vertical conductive pillars (360) on the first molding member (300).

The lower redistribution layer (100) may be a front redistribution layer (FRDL) of the fan out package. The lower redistribution layer (100) may include first to fifth lower insulating films (110a, 110b, 110c, 110d, 110e) and at least two layers of stacked first redistribution lines (120). The first redistribution lines (120) may include first to third lower redistribution lines (120a, 120b, 120c) that are vertically stacked.

The upper bonding pads (130) may be exposed from the lower surface of the lower redistribution layer (100). The lower bonding pads (140) may be exposed from the lower surface of the lower redistribution layer (100). The upper bonding pads (130) may include first bonding pads (130a) arranged in a chip mounting area and second bonding pads (130b) arranged in a fan out area surrounding the chip mounting area.

The semiconductor chip (200) may be placed in a chip mounting area, which is a fan-in area of the lower redistribution layer (100). The semiconductor chip (200) may be mounted on an upper surface of the lower redistribution layer (100) by a flip chip bonding method. The semiconductor chip (200) may be placed such that the front surface (202), i.e., the active surface, on which chip pads (210) are formed faces the lower redistribution layer (100). The chip pads (210) of the semiconductor chip (200) may be electrically connected to the first redistribution lines (102) of the lower redistribution layer (100) by conductive bumps (220). The conductive bumps (220) may be respectively bonded to the first bonding pads (130a) on the uppermost first redistribution line (120c). For example, the challenge bump (220) may include a micro bump (uBump).

The vertical conductive pillars (360) as vertical conductive structures can be respectively arranged on the second bonding pads (130b) located in the fan out region of the lower redistribution layer (100).

The first sealing member (300) can cover the semiconductor chip (200) and the plurality of vertical conductive pillars (360) on the upper surface of the lower rewiring layer (100). The first sealing member (300) can expose the upper portions of the vertical conductive pillars (360).

The upper redistribution layer (400) may be disposed on the upper surface of the first sealing member (300). The upper redistribution layer (400) may include first to third upper insulating films (410a, 410b, 410c) that are laminated and second redistribution lines (402) within the first to third upper insulating films (410a, 410b, 410c). The second redistribution lines (402) may include first and second upper redistribution lines (412, 422). Upper bonding pads (430) may be disposed on each of the second upper redistribution lines (422) as the uppermost redistribution lines.

The lower package (P1) may have a rectangular shape having four sides when viewed in a plan view. The lower package (P1) may include a first lower package side (S11) and a second lower package side (S12) that extend in a direction parallel to each other and face each other. The lower package (P1) may have a first planar area.

The lower package (P1) may include an upper package region (UPR) and an underfill region (DPR) on an upper surface of the upper redistribution layer (400). Upper bonding pads (430) of the upper redistribution layer (400) may be arranged within the upper package region (UPR). One side of the upper package region (UPR) may overlap with the first lower package side surface (S11). The underfill region (DPR) may extend along the second lower package side surface (S12) on one side of the upper package region (UPR). One side of the underfill region (DPR) may overlap with the second lower package side surface (S12).

In exemplary embodiments, the upper package (P2) may be mounted on the lower package (P1) via conductive connecting members (650).

The upper package (P2) may have a rectangular shape having four sides when viewed in a plan view. The upper package (P2) may include a first upper package side (S21) and a second upper package side (S21) that extend in a direction parallel to each other and face each other. The upper package (P2) may have a second planar area smaller than the first planar area of the lower package (P1).

The upper package (P1) can be arranged asymmetrically on the lower package (P2). The upper package (P2) can be placed on the upper package region (UPR) of the lower package (P1). The first upper package side surface (S21) of the upper package (P2) is positioned on the same plane as the first lower package side surface (S11) of the lower package (P1), and the second upper package side surface (S22) is positioned spaced apart from the second lower package side surface (12) by a preset distance (L1), so that the upper package (P2) can expose an underfill region (DPR) on the upper surface of the lower package (P1). The position of the center of the upper package (P2) can be shifted in one direction with respect to the center of the lower package (P1) to provide an underfill region (DPR) between the second upper package side surface (S22) and the second lower package side surface (S12) on the upper surface of the lower package (P1).

In exemplary embodiments, the underfill member (700) may include a horizontal extension (710a) extending horizontally from the underfill region (DPR) and filling a space between the lower package (P1) and the upper package (P2), and a vertical extension (710b) extending vertically from the underfill region (DPR) and covering at least a portion of the second upper package side (S22) of the upper package (P2).

Additionally, the lower package (P1) may include a dam structure (450) extending adjacent to the second lower package side surface (S12) within the underfill region (DPR) on the upper surface of the upper redistribution layer (400). The dam structure (450) may have a preset height on the upper surface of the upper redistribution layer (400). The dam structure (450) may contact a portion of an outer surface of the underfill member (700). The dam structure (450) may prevent the underfill member dispensed in the underfill region (DPR) on the upper surface (401a) of the upper redistribution layer (400) from flowing outward past the second lower package side surface (S12).

Below, a method for manufacturing the semiconductor package of Fig. 16 will be described.

FIGS. 17 to 25 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

Referring to FIG. 17, a lower redistribution layer (100) having first redistribution lines (120) can be formed on a carrier substrate (C1).

In exemplary embodiments, the carrier substrate (C1) may include a wafer substrate as a base substrate for arranging a plurality of semiconductor chips on the lower re-wiring layer and forming a molding member covering them. The carrier substrate (C1) may have a shape corresponding to a wafer on which a semiconductor process is performed. For example, the carrier substrate (C1) may include a silicon substrate, a glass substrate, a non-metallic or metallic plate, etc.

The carrier substrate (C1) may include a package region (PR) on which the semiconductor chip is mounted and a cut region (CR) surrounding the package region (PR). As described below, the lower redistribution layer (100) formed on the carrier substrate (C1) and the molding member may be cut along the cut region (CR) that separates a plurality of package regions (MR) and may be individualized.

In exemplary embodiments, a first lower insulating film (110a) having lower bonding pads (140) formed thereon may be formed on a carrier substrate (C1). Although not illustrated in the drawing, after forming a release film, a barrier metal layer, a seed layer, and the first lower insulating film on the carrier substrate (C1), the first lower insulating film may be patterned to form openings exposing the first bonding pad regions. Subsequently, a plating process may be performed on the seed layer to form lower bonding pads (140) within the openings.

For example, the first lower insulating film (110a) may include a polymer, a dielectric film, etc. The first lower insulating film (110a) may include a photosensitive insulating material (PID), an insulating film such as ABF, etc. The first lower insulating film may be formed by a spin coating process, a vapor deposition process, etc.

The lower bonding pad (140) may be a bump pad. The bump pad may include a solder pad or a pillar pad. For example, the lower bonding pad may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

Next, a second lower insulating film (110b) covering the lower bonding pads (140) is formed on the first lower insulating film (110a), and then the second lower insulating film (110b) is patterned to form first openings exposing at least a portion of each of the lower bonding pads (140).

Thereafter, first lower re-wires (120a) electrically connected to the lower bonding pads (140) through the first openings can be formed on the second lower insulating film (110b).

For example, the first lower redistribution line (120a) can be formed by forming a seed film on a portion of the second lower insulating film (110b) and within the first opening, and then patterning the seed film and performing an electrolytic plating process. Accordingly, at least a portion of the first lower redistribution line (120a) can be in direct contact with the lower bonding pad (140) through the first opening. For example, the first lower redistribution line can include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

Similarly, a third lower insulating film (110c) covering the first lower re-wires (120a) can be formed on the second lower insulating film (110b), and the third lower insulating film (110c) can be patterned to form second openings exposing at least portions of the first lower re-wires (120a). Then, second lower re-wires (120b) that directly contact the first lower re-wires (120a) can be formed on the third lower insulating film (110c) through the second openings.

Thereafter, a fourth lower insulating film (110d) covering the second lower re-wires (120b) can be formed on the third lower insulating film (110c), and the fourth lower insulating film (110d) can be patterned to form third openings exposing at least parts of the second lower re-wires (120b). Subsequently, third lower re-wires (120c) that directly contact the second lower re-wires (120b) can be formed on the fourth lower insulating film (110d) through the third openings.

Thereafter, a fifth lower insulating film (110e) covering the third lower rewiring lines (120c) can be formed on the fourth lower insulating film (110d).

Accordingly, a lower redistribution layer (100) having first to fifth lower insulating films (110a, 110b, 110c, 110d, 110e) can be formed. The lower redistribution layer (100) can be a front redistribution layer (FRDL) of a fan out package. The lower redistribution layer (100) can include at least two layers of stacked first redistribution lines (120). The lower bonding pads (140) can be exposed from a lower surface of the lower redistribution layer (100). The first redistribution lines (120) can include first to third lower redistribution lines (120a, 120b, 120c) that are vertically stacked. For example, the thickness of the first redistribution layer (100) can be within a range of 5 μm to 50 μm.

Next, upper bonding pads (162) can be formed on the uppermost first redistribution lines (142) on the upper surface of the lower redistribution layer (100).

For example, the fifth lower insulating film (110e) may be patterned to form openings that expose the third lower rewires (120c), respectively. The third lower rewires (120c) exposed by the openings may be uppermost rewires. A portion of the uppermost rewires may include a rewire pad portion.

Next, upper bonding pads (130) can be formed on the third lower re-wiring lines (120c) exposed by the openings by a plating process. The upper bonding pads can include a metal material. The upper bonding pads can include the same material as the third lower re-wiring line (120c). The upper bonding pads can include copper (Cu). The upper bonding pads (130) can include first bonding pads (130a) arranged in a central area of the package area (PR), that is, a chip mounting area, and second bonding pads (130b) arranged in an edge area surrounding the chip mounting area.

Referring to FIG. 18, at least one semiconductor chip (200) may be mounted on the upper surface of the lower redistribution layer (100), and vertical conductive pillars (360) may be formed around the semiconductor chip (200) on the upper surface of the lower redistribution layer (100).

In exemplary embodiments, a plurality of vertical conductive pillars (360) may be respectively formed on second bonding pads (130b) located in an edge region of the lower redistribution layer (100), i.e., a fan-out region. A seed film and a photoresist pattern may be sequentially formed on the lower redistribution layer (100), and an electrolytic plating process may be performed to fill the openings of the photoresist pattern with a conductive material to form the vertical conductive pillars (360). For example, the vertical conductive pillar (360) may include copper (Cu). The lower end of the vertical conductive pillar (360) may be bonded to the second bonding pad (130b). Subsequently, the photoresist pattern may be removed by a strip process.

Next, the semiconductor chip (200) may be placed in a chip mounting area, which is a fan-in area of the lower redistribution layer (100). The semiconductor chip (200) may be mounted on an upper surface of the lower redistribution layer (100) by a flip chip bonding method. The semiconductor chip (200) may be placed such that the front surface (202), i.e., the active surface, on which chip pads (210) are formed faces the lower redistribution layer (100). The chip pads (210) of the semiconductor chip (200) may be electrically connected to the first redistribution lines (102) of the lower redistribution layer (100) by conductive bumps (220). The conductive bumps (220) may be respectively bonded to the first bonding pads (130a) on the uppermost first redistribution line (120c). For example, the challenge bump (220) may include a micro bump (uBump).

Referring to FIG. 19, a first sealing member (300) covering a semiconductor chip (200) and a plurality of vertical conductive pillars (360) may be formed on an upper surface of a lower redistribution layer (100). For example, the first sealing member (300) may include an epoxy mold compound (EMC). The first sealing member (300) may include a first sealing portion covering a rear surface (204), i.e., an upper surface, of the semiconductor chip (200) and a second sealing portion covering an upper surface of the lower redistribution layer (100) around the semiconductor chip (200). The first sealing member (300) may expose upper portions of the vertical conductive pillars (360).

Referring to FIGS. 20 to 22, an upper rewiring layer (400) having second rewiring lines (402) electrically connected to vertical conductive pillars (360) can be formed on a first sealing member (300).

As illustrated in FIG. 20, after forming a first upper insulating film (410a) on the upper surface of the first sealing member (300), the first upper insulating film (410a) may be patterned to form openings (411a) that expose the upper portions of the vertical conductive pillars (360), respectively. The first upper insulating film (410a) may include a polymer, a dielectric film, or the like. The first upper insulating film (410a) may be formed by a vapor deposition process, a spin coating process, or the like.

As illustrated in FIG. 21, after forming a seed film on and within portions of the vertical conductive pillars (360) exposed by the openings (411a), the seed film may be patterned and an electroplating process may be performed to form first upper redistribution lines (412). Accordingly, at least portions of the first upper redistribution lines (412) may be electrically connected to the vertical conductive pillars (360) through the openings (411a). The first upper redistribution lines may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

Thereafter, a second upper insulating film (410b) is formed on the first upper insulating film (410a), and then the second upper insulating film (410b) is patterned to form openings (411b) exposing the first upper re-wires (412).

As illustrated in Fig. 22, second upper re-wires (422) can be formed in direct contact with the first upper re-wires (412) through openings (411b) on the second upper insulating film (410b).

Accordingly, the second rewiring lines (402) may include at least two layers of stacked first upper rewiring lines (412) and second upper rewiring lines (422). In this case, the first upper rewiring line (412) may correspond to the lowest rewiring line among the second rewiring lines, and the second upper rewiring line (422) may correspond to the highest rewiring line among the second rewiring lines.

Next, upper bonding pads (430) may be formed on the second upper re-wirings (422) as the uppermost re-wiring, respectively, and a third upper insulating film (410c) exposing at least a portion of the upper bonding pads (430) on the second upper re-wiring (422) may be formed on the second upper insulating film (410b). The third upper insulating film (410c) may serve as a passivation film.

Accordingly, an upper redistribution layer (400) having second redistribution lines (402) as a backside redistribution layer (BRDL) can be formed on the first sealing member (300). The upper redistribution layer (400) can include first to third upper insulating films (410a, 410b, 410c) that are stacked and second redistribution lines (402) within the first to third upper insulating films (410a, 410b, 410c). The second redistribution line (402) can include first and second upper redistribution lines (412, 422).

The number, size, arrangement, etc. of the upper insulating films and the upper redistribution lines of the upper redistribution layer are provided as examples, and it will be understood that the present invention is not limited thereto.

Thereafter, a dam structure (450) extending along one side of the cut region (CR) on the upper surface of the upper re-distribution layer (400) may be included. The dam structure (450) may have a preset height on the upper surface of the upper re-distribution layer (400). As described below, the dam structure (450) may prevent an underfill material dispensed on the upper surface of the upper re-distribution layer (400) from flowing out to the outside.

Referring to FIG. 23, the carrier substrate (C1) is removed, external connection members (180) are formed on the outer surface of the lower redistribution layer (100), i.e., the lower bonding pads (140) on the lower surface, and the individual lower redistribution layers (100) are separated through a sawing process to form individual lower packages (P1).

In exemplary embodiments, solder balls may be arranged as the external connection members on the lower substrate pads (140) on the lower surface of the lower redistribution layer (100). Subsequently, the lower redistribution layer (100) may be cut along a cutting region (CR) that separates a plurality of package regions (PR) by a sawing process to be individualized into a plurality of lower packages (P1).

The lower package (P1) may include a lower redistribution layer (100), at least one first semiconductor chip (200) mounted on the lower redistribution layer (100), vertical conductive pillars (360) positioned on the lower redistribution layer (100) and electrically connected to the at least one first semiconductor chip (200), a first sealing member (300) covering the at least one first semiconductor chip (200) on the lower redistribution layer (100) and exposing upper portions of the vertical conductive pillars (360), and an upper redistribution layer (400) electrically connected to the vertical conductive pillars (360) on the first molding member (300).

The lower package (P1) may have a rectangular shape having four sides when viewed in a plan view. The lower package (P1) may include a first lower package side (S11) and a second lower package side (S12) that extend in a direction parallel to each other and face each other. The lower package (P1) may have a first planar area.

The lower package (P1) may include an upper package region (UPR) and an underfill region (DPR) on an upper surface of the upper redistribution layer (400). Upper bonding pads (430) of the upper redistribution layer (400) may be arranged within the upper package region (UPR). One side of the upper package region (UPR) may overlap with the first lower package side surface (S11). The underfill region (DPR) may extend along the second lower package side surface (S12) on one side of the upper package region (UPR). One side of the underfill region (DPR) may overlap with the second lower package side surface (S12).

Referring to FIG. 24, an upper package (P2) can be laminated on a lower package (P1) via conductive connecting members (650).

In exemplary embodiments, solder balls as the conductive connecting members are respectively formed on the lower substrate pads (614) of the lower surface of the package substrate (610) of the upper package (P2) by a solder ball attach process, and then the upper package (P2) can be mounted on the lower package (P1) via the conductive connecting members.

Conductive connecting members (650) may be interposed between the lower package (P1) and the upper package (P2) to electrically connect them. A gap (G) may be formed between the upper package (P2) and the lower package (P1) by the conductive connecting members (650). The conductive connecting members (650) formed on the lower substrate pads (614) of the second package substrate (610) of the lower package (P1) may be bonded to upper bonding pads (430) arranged within the upper package region (UPR) of the upper redistribution layer (400).

The upper package (P2) may have a rectangular shape having four sides when viewed in a plan view. The upper package (P2) may include a first upper package side (S21) and a second upper package side (S21) that extend in a direction parallel to each other and face each other. The upper package (P2) may have a second planar area smaller than the first planar area.

The upper package (P2) can be placed on the upper package region (UPR) of the lower package (P1). The first upper package side surface (S21) of the upper package (P2) is positioned on the same plane as the first lower package side surface (S11) of the lower package (P1), and the second upper package side surface (S22) is positioned spaced apart from the second lower package side surface (12) by a preset distance (L1), so that the upper package (P2) can expose an underfill region (DPR) on the upper surface of the lower package (P1). The position of the center of the upper package (P2) can be shifted in one direction with respect to the center of the lower package (P1) to provide an underfill region (DPR) between the second upper package side surface (S22) and the second lower package side surface (S12) on the upper surface of the lower package (P1).

In this case, the dam structure (450) can extend in one direction adjacent to the second lower package side (S12) within the underfill region (DPR) on the upper surface of the lower package (P1).

Referring to FIG. 25, an underfill member (700) can be formed between the lower package (P2) and the upper package (P1) by performing processes identical or similar to those referred to in FIGS. 11 and 12.

In exemplary embodiments, the underfill member (700) may include a horizontal extension (710a) extending horizontally from the underfill region (DPR) and filling a space between the lower package (P1) and the upper package (P2), and a vertical extension (710b) extending vertically from the underfill region (DPR) and covering at least a portion of the second upper package side (S22) of the upper package (P2).

For example, the height from the upper surface of the lower package (P1) of the vertical extension (710b) may be 30% to 80% of the height from the upper surface of the lower package (P1) of the upper package (P2). The height from the upper surface of the lower package (P1) of the dam structure (450) may be within a range of 100 μm to 500 μm.

Accordingly, the upper package (P2) is mounted on the lower package (P1) at the board level, and then an underfill process is performed between the lower package (P1) and the upper package (P2) to complete the semiconductor package of Fig. 16 with secured reliability.

The semiconductor package described above may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as a central processing unit (CPU, MPU), an application processor (AP), volatile memory devices such as an SRAM device, a DRAM device, and nonvolatile memory devices such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, and the like.

Although the present invention has been described above with reference to embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

10, 11, 12: Semiconductor package 50: Dispenser nozzle
100: 1st package substrate, lower redistribution layer
130, 430: Top substrate pad 140, 440: Bottom substrate pad
180: Absence of external connection 200: First semiconductor chip
210: 1st chip pad 220: Conductive bump
300: First sealing member 350: Vertical conductive connector
360: Vertical challenge pillar 400: Interposer, upper redistribution layer
450: Dam structure 452: Receiving home
610: Second package substrate 620, 620a, 620b: Second semiconductor chip
630: Second conductive connecting member 640: Second sealing member
650: No challenging connection 700: No underfill
710a: Horizontal extension 710b, 710c: Vertical extension

Claims (10)

A lower package having a first lower package side surface extending in a first direction and perpendicular to the upper surface and a second lower package side surface facing the first lower package side surface;
An upper package having a first upper package side extending in the first direction and a second upper package side facing the first upper package side, the first upper package side being positioned on the same plane as the first lower package side of the lower package and the second upper package side being positioned so as to be spaced apart from the second lower package side by a preset distance, thereby defining an underfill area on an upper surface of the lower package; and
A semiconductor package comprising an underfill member extending from the underfill region on the upper surface of the lower package into a space between the lower package and the upper package. A semiconductor package in accordance with claim 1, wherein the underfill member further includes a vertical extension extending vertically from the underfill region and covering at least a portion of a side surface of the second upper package of the upper package. A semiconductor package in claim 1, wherein the preset distance is at least 0.5 mm. A semiconductor package in accordance with claim 1, wherein the lower package further includes a dam structure extending along a side surface of the second lower package within the underfill dispensing region on the upper surface of the lower package and protrudingly formed to have a preset height on the upper surface. A semiconductor package in accordance with claim 1, wherein the lower package further includes a receiving groove extending along a side surface of the second lower package within the underfill region on the upper surface of the lower package and having a predetermined depth from the upper surface. In the first paragraph, the lower package has a third lower package side extending in a second direction orthogonal to the first direction and a fourth lower package side facing the third lower package side,
The upper package has a third upper package side extending in the second direction and a fourth lower package side facing the third upper package side,
A semiconductor package in which the third upper package side surface of the upper package is positioned on the same plane as the third lower package side surface of the lower package, and the fourth upper package side surface is positioned at a predetermined distance from the fourth lower package side surface, thereby defining a second underfill region on an upper surface of the lower package. In the first paragraph, the lower package
1st package substrate;
At least one first semiconductor chip mounted on the first package substrate;
Vertical conductive connectors disposed on the first package substrate and electrically connected to at least one first semiconductor chip;
A first sealing member covering the at least one first semiconductor chip on the first package substrate and exposing one end of the vertical conductive connectors; and
An interposer electrically connected to the vertical conductive connectors on the first sealing member and having upper connection pads,
A semiconductor package wherein the above conductive connecting members are respectively positioned on the upper connection pads of the interposer. A semiconductor package in claim 7, wherein the at least one first semiconductor chip is arranged such that the front surface on which the first chip pads are formed faces the first package substrate. A semiconductor package in accordance with claim 7, wherein the first package substrate includes a lower redistribution layer having lower redistribution lines, and the interposer includes an upper redistribution layer having upper redistribution lines electrically connected to the vertical conductive connectors. A lower package having a first lower package side surface having a first planar area, a first lower package side surface extending in a first direction and perpendicular to the upper surface, and a second lower package side surface facing the first lower package side surface;
An upper package having a second planar area smaller than the first planar area, the first upper package side extending in the first direction and a second upper package side facing the first upper package side, the center position of which is shifted and aligned in a second direction orthogonal to the first direction with respect to the center of the lower package, thereby defining an underfill region between the second upper package side and the second lower package side on the upper surface of the lower package; and
A semiconductor package including an underfill member extending horizontally from the underfill region on the upper surface of the lower package and filling a space between the lower package and the upper package.