KR20240166284A - Ferroelectric logic-in-memory tunneling device and ferroelectric logic-in-memory tunneling device manufacturing method - Google Patents

Abstract

Disclosed are a ferroelectric logic-in-memory tunneling device and a method for manufacturing a ferroelectric logic-in-memory tunneling device. The ferroelectric logic-in-memory tunneling device may include a substrate; and a ferroelectric member formed on the substrate, each including at least one first layer including HfO ₂ and one second layer including ZrO ₂ , wherein the first layer and the second layer are alternately laminated.

Description

{FERROELECTRIC LOGIC-IN-MEMORY TUNNELING DEVICE AND FERROELECTRIC LOGIC-IN-MEMORY TUNNELING DEVICE MANUFACTURING METHOD}

The present invention relates to a ferroelectric logic-in-memory tunneling device and a method for manufacturing a ferroelectric logic-in-memory tunneling device.

Complex topological polar textures have been observed as a result of spatially varying ferroelectric polarization orientation over a range of nanometers. In particular, topological polar textures in ferroelectrics have attracted much attention in recent years due to their unique polarization-orientation properties, leading to potential applications in memory devices. Ideally, these nanometer-sized polar textures have the potential to provide integrated state-of-the-art nanoelectronics for ultra-high-density storage where crosstalk between adjacent bits can be ignored. In fact, this is far greater than current ferroelectric storage technologies, on the order of terabit per square inch. However, the ability to precisely control the order parameter (here, polarization) of these topological states in response to external stimuli (i.e., electric fields) is critical and essential to realizing the potential of polar textures in nanoelectronics and memory storage. Although topologically polar nanotextures have recently been observed in superlattices and lead/strontium titanate layers have been transferred, the direct integration of ultrathin ferroelectric materials into silicon-based technologies using simple growth techniques and their effective use in multilevel programmable memory and processing devices has not yet been demonstrated. The resurgence of cutting-edge micro/nanoelectronics in the context of ferroelectric materials has been attributed to the discovery of ferroelectricity in ultrathin hafnium oxide (HfO ₂ ). Because of their strong polarization (>40 C cm ^-2 ), scalability, and compatibility with silicon, HfO ₂ , zirconium oxide (ZrO ₂ ), and their alloys are considered as the emerging ferroelectrics for mainstream semiconductor electronics at the nanoscale. However, like traditional ferroelectric materials, HfO ₂ -based devices have two stable polarization states that can be switched from one stable state to the other using an external electric field, which limits their use in principle to store binary bits of memory, which limits their applications in multilevel storage and processing devices. In contrast, topological polar textures vary in polarization direction and may offer unique possibilities to enable orientation control, resulting in the ability to store multilevel memories as well as execute logic-in-memory operations within a single device.

One object of the present invention is to provide a ferroelectric logic-in-memory tunneling device that provides ultra-high-speed non-volatile layered current switching.

Another object of the present invention is to provide a method for manufacturing the ferroelectric logic-in-memory tunneling element.

In one aspect, the present invention provides a ferroelectric logic-in-memory tunneling element, comprising: a substrate; and a ferroelectric member formed on the substrate, each including at least one first layer including HfO ₂ and at least one second layer including ZrO ₂ , wherein the first layer and the second layer are alternately laminated.

In one embodiment, the ferroelectric logic-in-memory tunneling element may further include two or more electrodes spaced apart and connected to the ferroelectric portion.

In one embodiment, the substrate may comprise silicon (Si).

In one embodiment, the ferroelectric portion may have both the uppermost layer and the lowermost layer as first layers.

In one embodiment, the ferroelectric portion may include five layers.

In one embodiment, the orientation of the chemical species included in the ferroelectric portion may be random.

In another aspect, the present invention provides a method for manufacturing a ferroelectric logic-in-memory tunneling element, comprising: a first layer forming step of forming a first layer including HfO ₂ on a substrate; and a second layer forming step of forming a second layer including ZrO ₂ on the substrate; alternately performing these steps to form a ferroelectric portion;

In one embodiment, the first layer forming step and the second layer forming step can be performed by atomic layer deposition (ALD).

In one embodiment, the atomic layer deposition of the first layer may use Tetrakis(dimethylamido)hafnium (TDMAH) as a precursor.

In one embodiment, the atomic layer deposition of the second layer may use TEMAZ (Tetrakis(ethylmethylamino)zirconium) as a precursor.

In one embodiment, the method may further include an electrode forming step of forming two or more electrodes spaced apart from each other and connected to the ferroelectric portion.

In one embodiment, the substrate can be prepared as a substrate including silicon (Si).

In one embodiment, the first layer forming step and the second layer forming step can be performed so that both the uppermost layer and the lowermost layer of the ferroelectric portion become the first layer.

In one embodiment, the first layer forming step and the second layer forming step can be performed a total of five times.

In another aspect, the present invention provides a ferroelectric logic-in-memory tunneling device manufactured by a method for manufacturing a ferroelectric logic-in-memory tunneling device, the method including: forming a first layer including HfO ₂ on a substrate; and forming a second layer including ZrO ₂ on the substrate; alternately performing a ferroelectric part forming step; thereby forming a ferroelectric part.

In one embodiment, the orientation of the chemical species included in the ferroelectric portion may be random.

A ferroelectric logic-in-memory tunneling device according to an embodiment of the present invention can provide ultra-high-speed non-volatile layered current switching.

The ferroelectric logic-in-memory tunneling device can be implemented through a method for manufacturing the ferroelectric logic-in-memory tunneling device according to an embodiment of the present invention.

FIG. 1 is a schematic diagram illustrating a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention.
FIG. 2 is a flowchart schematically illustrating a method for manufacturing a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention.
Figures 3a to 6d are drawings showing experimental examples of the present invention and experimental results according to the experimental examples.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention can be modified in various ways and can have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. In describing each drawing, similar reference numerals are used for similar components. In the attached drawings, the dimensions of structures are illustrated larger than actual dimensions in order to ensure clarity of the present invention.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" and the like are intended to specify the presence of a feature, number, step, operation, component or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

FIG. 1 is a schematic diagram illustrating a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention.

Referring to FIG. 1, a ferroelectric logic-in-memory tunneling element (100) according to an embodiment of the present invention may include a substrate (110); and a ferroelectric portion (120) formed on the substrate (110), each including at least one first layer (121) including HfO ₂ and at least one second layer (122) including ZrO ₂ , wherein the first layer (121) and the second layer (122) are alternately laminated.

The substrate (110) is a member that provides support for forming a laminated structure of a ferroelectric logic-in-memory tunneling device (100) according to an embodiment of the present invention. The substrate (110) can provide physical support for forming a laminated structure, and the laminated structure is formed on the substrate (110), which can affect the properties of the laminated structure. Therefore, the material of the substrate (110), etc., can be selected according to the desired characteristics of the ferroelectric logic-in-memory tunneling device (100) according to an embodiment of the present invention. In one embodiment, the substrate (110) can include silicon (Si).

The above ferroelectric portion (120) is a member forming a laminated structure of a ferroelectric logic-in-memory tunneling element (100) according to an embodiment of the present invention. The above ferroelectric portion (120) can provide characteristics such as ultra-high-speed non-volatile multilayer current switching of the ferroelectric logic-in-memory tunneling element (100) according to an embodiment of the present invention. In order to perform the above functions, the material, shape, structure, etc. of the lower member included in the ferroelectric portion (120) can be selected.

In one embodiment, the ferroelectric portion (120) may include a first layer (121) including HfO ₂ . In one embodiment, the ferroelectric portion (120) may include a second layer (122) including ZrO ₂ . In one embodiment, the ferroelectric portion (120) may include a structure in which the first layer (121) including HfO ₂ and the second layer (122) including ZrO ₂ are alternately laminated.

In one embodiment, the ferroelectric logic-in-memory tunneling element (100) may further include two or more electrodes spaced apart from each other and connected to the ferroelectric portion (120). The electrodes may be respectively connected to the ferroelectric portion (120) to provide a conductive path. A voltage may be applied to the conductive path including the electrodes and/or a current may flow to change and/or measure the electrical characteristics of the ferroelectric portion (120).

In one embodiment, the ferroelectric portion (120) may have both the uppermost layer and the lowermost layer as the first layer (121). As described above, the ferroelectric portion (120) may include a structure in which the first layer (121) including HfO ₂ and the second layer (122) including ZrO ₂ are alternately laminated, so in the embodiment, the ferroelectric portion (120) may include an odd total of the first layer (121) and the second layer (122). In one embodiment, the ferroelectric portion (120) may include five layers.

As long as the above-described ferroelectric portion (120) exhibits the above-described function through the above-described material, shape, and structure, the microscopic characteristics of the above-described ferroelectric portion (120) are not particularly limited. In one embodiment, the orientation of the chemical species included in the above-described ferroelectric portion (120) may be random.

FIG. 2 is a flowchart schematically illustrating a method for manufacturing a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention.

Referring to FIG. 2, a method (200) for manufacturing a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention may include a ferroelectric part forming step (S210) of forming a ferroelectric part by alternately performing a first layer forming step (S211) of forming a first layer including HfO ₂ on a substrate; and a second layer forming step (S212) of forming a second layer including ZrO ₂ on the substrate.

The description of the method (200) for manufacturing a ferroelectric logic-in-memory tunneling element according to the above-described embodiment of the present invention applies identically or similarly to the same or similar terms or configurations in the description of the ferroelectric logic-in-memory tunneling element according to the above-described embodiment of the present invention.

The above first layer forming step (S211) is a step of forming a first layer including HfO ₂ on a substrate. The above second layer forming step (S212) is a step of forming a second layer including ZrO ₂ on the substrate. In the context of the present specification, the term "forming on a substrate" is not limited to forming in direct contact with the substrate, and includes forming on another layer in a state where a significantly thin level of another layer is formed on the substrate.

The above ferroelectric portion forming step (S210) is a step in which the first layer forming step (S211) and the second layer forming step (S212) are alternately performed. By alternately performing the first layer forming step (S211) and the second layer forming step (S212), the ferroelectric portion formed through the ferroelectric portion forming step (S210) can include a structure in which the first layer formed by the first layer forming step (S211) and the second layer formed by the second layer forming step (S212) are alternately laminated.

As described above, as long as the first layer and the second layer can be formed, the method of forming the first layer and the second layer is not particularly limited. In one embodiment, the first layer forming step (S211) and the second layer forming step (S212) can be performed by deposition. In one embodiment, the first layer forming step (S211) and the second layer forming step (S212) can be performed by atomic layer deposition (ALD).

As long as the materials, shapes, and structures of the first and second layers described above can be implemented, the materials (precursors) and process variables of the atomic layer deposition are not particularly limited. In one embodiment, the atomic layer deposition of the first layer can use TDMAH (Tetrakis(dimethylamido)hafnium) as a precursor. In one embodiment, the atomic layer deposition of the second layer can use TEMAZ (Tetrakis(ethylmethylamino)zirconium) as a precursor.

The material, shape, and structure of the substrate on which the first layer forming step (S211) and the second layer forming step (S212) are performed are not particularly limited. In one embodiment, the substrate may be prepared as a substrate including silicon (Si).

Specifically, in one embodiment, TDMAH may be used as a precursor for forming a first layer including HfO ₂ . The formation of the first layer may be performed at a temperature of about 250 ° C. while setting the temperature to about 60 ° C. and setting the Ar and O ₂ line temperatures to about 80 ° C. The operating pressure may be maintained at about 0.5 Torr. The cleaning and heating of the Ar and O ₂ lines may be performed for about 200 seconds, with an Ar flow of about 300 sccm to the precursor line, a vapor pressure line of about 100 sccm, and an O ₂ flow of about 300 sccm to the oxygen line. The TDMAH supply and purge may be performed for about 2 seconds and about 15 seconds, respectively, and the O ₂ supply may be performed for about 4 seconds. Sequentially, an O ₂ plasma treatment is performed at an RF power of about 50 or about 100 W for about 2 seconds, and finally, the O ₂ is purged for about 10 seconds. This cycle was repeated for the loop to increase the required thickness.

For ZrO ₂ growth, the substrate temperature can be set to about 200 ℃ and TEMAZ precursor can be used. The growth can be performed by feeding (about 2 s) and purging (about 15 s). The O ₂ feeding and purging can be performed for about 4 s and about 10 s, respectively. Between the O ₂ feeding and purging, the O ₂ plasma treatment can be performed for about 2 s at an RF power of about 50 to 100 W. The growth of the two films (U-HZO) and (N-HZO) can be performed under similar conditions except for the O ₂ plasma treatment. The U-HZO film can be noted for the O ₂ plasma of about 100 W. The final line purge can be performed for about 300 s.

The method (200) for manufacturing a ferroelectric logic-in-memory tunneling element according to an embodiment of the present invention does not exclude the addition of additional steps and/or processes. In one embodiment, it may further include an electrode forming step of forming two or more electrodes spaced apart from each other and connected to the ferroelectric portion. The electrode formed by the electrode forming step may provide a conductive path to the ferroelectric portion.

In one embodiment, the first layer forming step (S211) and the second layer forming step (S212) can be performed so that both the uppermost layer and the lowermost layer of the ferroelectric portion become first layers. In order to perform the first layer forming step (S211) and the second layer forming step (S212) so that both the uppermost layer and the lowermost layer become first layers as described above, the first layer forming step (S211) can be performed first, and/or the sum of the total number of times the first layer forming step (S211) and the second layer forming step (S212) are performed can be an odd number. In one embodiment, the first layer forming step (S211) and the second layer forming step (S212) can be performed a total of five times.

Meanwhile, a ferroelectric logic-in-memory tunneling device according to an embodiment of the present invention can be manufactured by a method for manufacturing a _{ferroelectric} logic-in-memory tunneling device, including a ferroelectric portion forming step, which alternately performs a first layer forming step of forming a first layer including HfO ₂ on a substrate; and a second layer forming step of forming a second layer including ZrO 2 on the substrate; to form a ferroelectric portion. In one embodiment, the orientation of chemical species included in the ferroelectric portion can be random.

Hereinafter, embodiments of the present invention will be described in detail. However, the embodiments described below are only some embodiments of the present invention, and the scope of the present invention is not limited to the embodiments described below.

Manufacturing example

TDMAH was used as a precursor for the formation of HfO ₂ . The formation of HfO ₂ was performed at 250 °C with the canister temperature set to 60 °C and the Ar and O 2 line temperatures set to 80 °C. The operating pressure was maintained at 0.5 Torr. The purging and heating of the Ar and O ₂ lines were performed for 200 s with an Ar flow of 300 sccm to the precursor line, a vapor pressure line of 100 sccm, and an O ₂ flow of 300 sccm to the oxygen line. Thereafter, TDMAH supply and purge were performed for 2 s and 15 s, respectively, followed by an O 2 supply of 4 s. Sequential O 2 plasma treatment was performed for 2 s at an RF power of 50 or 100 W, and finally, O ₂ was purged for 10 s. This cycle was repeated for the loop to increase the required thickness.

For ZrO ₂ growth, the substrate temperature was set to 200 ℃ and TEMAZ precursor was used. The growth was performed by feeding (2 s) and purging (15 s). O ₂ feeding and purging were performed for 4 s and 10 s, respectively. O ₂ plasma treatment was performed for 2 s at an RF power of 50–100 W between O ₂ feeding and purging. The growth of both films (U-HZO) and (N-HZO) was performed under similar conditions except for the O ₂ plasma treatment. For example, O ₂ plasma treatment at 50 W led to N-HZO film, whereas U-HZO film was observed for 100 W of O ₂ plasma. The final line purge was performed for 300 s.

Experimental example

PFM measurements were performed using a conductive AFM tip (AC240 TM). VPFM was performed at a contact resonance frequency of 365 kHz and an AC voltage of 1 V was applied to the probe. These lateral PFM measurements were performed at a frequency closer to the lateral tip surface resonance (ca. 1018 kHz) with an AC voltage of 1 V and the experiments were performed at different tip-sample orientations (by rotating the sample with respect to the tip). All AFM-based measurements were collected at a constant force (F) of 68 nN to eliminate the possibility of mechanical writing.

Measurements of cross-sectional TEM, EELS, and EDS elemental mapping were all performed on a JEOL JEM-2100 F transmission electron microscope. Bulk charge transport was performed on a Keithley 4200 source meter. The electrical properties of the devices were determined in a vacuum probe station operating at room temperature using a semiconductor device parameter analyzer (Keithley 4200) and a home-built electrical circuit. The semiconductor pulse generator (model 4225-PMU and 4225-RPM) was used to generate the voltage pulses. The pulse measurement unit of the 4200A was utilized to generate ultra-fast voltage pulses and observe the transient current response to obtain the measurements. The Zive SP1 (ZIVELAB) was used to measure the logic-in-memory processing when properly connected to the probe station.

Experimental Results

The information provided by piezoresponse force microscopy (PFM) particularly probes the polarization orientation of ferroelectric materials. For example, the 180° topological inversion and subsequent sharp peak observed at the domain boundaries in the amplitude map indicate the presence of well-aligned (i.e., 180°) ferroelectric domains, as illustrated in the upper schematic diagram of Fig. 3a. In contrast, the PFM topology and amplitude change gradually for small dimensions (<10 nm) of complex or non-180° domain walls, as illustrated in the lower two cartoon diagrams of Fig. 3a. The gradual change in the vertical PFM (VPFM) amplitude can reveal that the ferroelectric material has a complex polar organization.

For the observation of polarization direction and effective utilization as a memory device, uniform Hf _0.5 Zr _0.5 O ₂ (hereinafter referred to as U-HZO) and nanolaminated HfO ₂ /ZrO ₂ /HfO ₂ /ZrO ₂ /HfO ₂ (hereinafter referred to as N-HZO) thin films were directly prepared. Oxide (SiO 2, 2 nm) was covered on the Si substrate using the atomic layer deposition technique as shown in the schematic diagram of Fig. 3b. The initial growth was confirmed by the cross-sectional transmission electron microscope (TEM) image depicted below the corresponding schematic diagram of Fig. 3b.

As previously established, U-HZO films show the presence of 180° domains (Fig. 3c). This is associated with the abrupt change in the out-of-plane (i.e., vertical) PFM (VPFM) topology image and the amplitude at the domain wells (see the line profiles in the right panel of Fig. 3c). In contrast, for N-HZO films, the VPFM topology and amplitude (Fig. 3d) vary gradually over space, as also confirmed by the line profiles in Fig. 3d, indicating that the domains in N-HZO are not 180° but complex domains. Therefore, we investigated the polarization direction in N-HZO using vector PFM. In contrast to U-HZO films, side-view PFM (LPFM) imaging provides direct microscopic evidence for the in-plane polarization in N-HZO films, as shown in Fig. 3e. The pronounced contrast change in the LPFM topology image along the sharp line in the amplitude image at the topology change boundary suggests in-plane polarization with 180° domain inversion, as can also be seen in the line profile in Fig. 3e. For clarity, Fig. 3f is a zoomed-in view of VPFM (Fig. 3d) and LPFM (Fig. 3e), which demonstrate the presence of in-plane and out-of-plane domains that can generate complex domain patterns. The VPFM topology and amplitude change gradually, while the abrupt change in LPFM topology and amplitude change indicate the complex polarization in the N-HZO device.

To find the possible directions of in-plane polarization in N-HZO, LPFM was measured by rotating the sample clockwise by 30° at a time. In particular, the topological images of the LPFM amplitude and the sharp lines consistently indicate a 180° topological reversal of the in-plane polarization. This suggests that the in-plane polarization can have rotational symmetry, resulting in a wide variety of nanoscale domain patterns, including skyrmion-like polar textures. To reveal the complex nature of the domains, the amplitudes of LPFM (Fig. 3e) and VPFM (Fig. 3d) are added and plotted in Fig. 3g and the associated histograms. Among the possible polarization directions, Fig. 3h shows a schematic representation of the in-plane and out-of-plane polar textures. Indeed, the PFM imaging indicates that the film contains complex nanodomain patterns. This could be due to several governing mechanisms, including the HfO ₂ and ZrO ₂ interfaces, nanoparticle structures, and/or deformation.

To understand the complex domain formation, high-resolution cross-sectional TEM images were performed. The brightness change from top to bottom, as delineated by the yellow dashed line in Fig. 4a, is due to the presence of HfO ₂ -ZrO ₂ nanolaminates with high crystal quality and homogeneous interfaces. The complete HfO ₂ -ZrO ₂ nanolaminate structure is provided by large-scale high-angle annular dark-field (HAADF) and TEM imaging. A pre-written MATLAB script was used to fit the atomic intensities to a two-dimensional Gaussian function to determine the central atomic positions. This function generates quantitative atomic displacements (with picometer resolution). The calculated in-plane intensity distributions (i.e., fitted atomic positions) corresponding to the TEM image (Fig. 4a) are plotted in Fig. 4b, where the HfO ₂ and ZrO ₂ layers are delineated by the yellow dashed lines. Subsequently, the relative atomic displacements were estimated and displayed in the color map in Fig. 4c, which is indeed closely related to the polarization direction. Interestingly, the atomic displacements did not vary consistently throughout the film, but rather exhibited a broad distribution, for example, while in-situ atomic displacements were observed in one part, the other parts showed downward displacements, as shown in the enlarged image at the bottom of Fig. 4c. The N-HZO film has a wide range of atomic displacements with different directions, which may be one of the key factors for the complex polarization.

These complex nanodomains may play a crucial role in generating exceptionally high switchable polarizations, which may lead to the development of proof-of-principle memory storage concepts. Therefore, in the next step, we attempted to flip the polarization direction of the N-HZO film using a nanoscale probe, as illustrated in Fig. 4d. A voltage of +8.0 V (referred to as the write voltage, Vw) was applied between the DC tip and the sample, and a square area (0.5 × 0.5 μm ² ) was scanned in contact mode. Subsequently, the VPFM phase and amplitude signals were mapped over a large area (1.2 × 1.2 μm ² ) in the absence of a DC current, and are shown in the respective images in Fig. 4e . Both the PFM phase contrast and the PFM amplitude change relative to the surrounding area due to Vw, indicating polarization reversal (Fig. 4e ). It can be confirmed that there is no sharp peak at the boundary between the original (i.e., no Vw) and flipped (after Vw application) regions, as delineated by the black square boxes in Fig. 4e. In contrast, the amplitude varies throughout the written region, indicating a complex polarization flipping that is not 180°. In addition, since the surface topography before and after voltage application does not change, local filament formation can be ruled out.

Also, scanning the surface with different Vw values, as schematically indicated by the blue box in Fig. 4f, produces distinct changes in the VPFM topology (middle image) and amplitude map (right image), demonstrating the tunable modulation of the effective polarization orientation. In fact, the VPFM topology and amplitude vary with Vw, for example, the amplitude is For Vw = +8.0 V, the effective polarization flips to 20 pm, whereas it enhances to 180 pm. These different levels of reversal in the polarization amplitude demonstrate that the NH ZO device has different possible polarization directions, which in turn allows the device to store multilevel memories. Furthermore, to find the rewritability, the region was scanned with Vw of −7.0 V, which is expected to reverse the effective polarization with respect to Vw of +7.0 V, as schematically indicated by the red and blue boxes in Fig. 4g. Simultaneously, two other locations (area sizes = 0.7 × 0.7 μm ² and 0.5 × 0.5 μm ² ) were scanned with Vw of +8.0 and +7.0 V, respectively, which can evidence the relative change in amplitude as well as the phase shift. As expected, Vw induces an effective polarization flipping, whereas for Vw of −7.0 V, the sound in the top-center region shows the opposite polarity with respect to the center part, indicating polarization reversal. At the same time, it can be seen that the PFM amplitude is effectively modified. For example, when Vw is +7.0 V, the amplitude is It changes to 120pm and scans the area where Vw is 7.0V to return to the original level ( 10 pm) to provide rewritable amplitude modulation. The PFM images in Figs. 4f and 4g were acquired by sequential writing and reading of each pattern, so that the relative changes in the final images are shown. The same area was scanned multiple times during this process. Therefore, to avoid misunderstanding, the scale bar of the PFM step was considered as an arbitrary unit. In addition, the complex nature of polarization and amplitude variation in the film PFM topology may provide the possibility to store multilevel memory storage. In addition, the negligible change in amplitude at -7.0 V indicates that the device polarization can be flipped to the original direction.

At this point, the effective _d33 values for both U-HZO and N-HZO were measured under the influence of small alternating currents. It can be seen that the _d33 value for U-HZO (hereafter referred to as _d33 UHZO) is 60 pm ·V- ¹ . In contrast, the _d33 value is enhanced to 160 pm ·V- ¹ for N-HZO film (hereafter referred to as _d33 NHZO), which is an improvement of 167%. These enhancements in _d33 and multilevel _VPFM amplitude indicate that N- _HZO films may provide a better alternative not only for storing high-density multilevel memory but also for performing processing within the memory, which is difficult to obtain in contrast to well-studied uniform _Hf0.5Zr0.5O2 films, which have only two possible polarization directions.

The ability to change the direction of the dipole polarization implies an attractive potential for developing innovative nanoscale memory and logic devices. The surface area (1 × 1 ^μm2 ) was scanned in contact mode with Vw = -8.0 and the current was mapped sequentially with a read voltage (Vr) of +3.0 V. The surface exhibits very low current levels (<10 pA, i.e., close to the noise level of the system used) with Vr = +3.0 V, as shown in the left current map in Fig. 5a. After scanning the region with Vw = +8.0 V, a highly conductive pattern emerges even when the same Vr = +3.0 V, as can be seen in the middle current map in Fig. 5a. As expected from the PFM analysis, the prominent current pattern can be attributed to the complex polarization orientation of the device. In particular, the current can be restored to the original level (i.e., <10 pA, Vr = +3.0 V) after scanning the same region with Vw = -8.0, confirming the nanoscale rewritable memory. Additionally, the magnitude of the current level at fixed Vr of +3.0 V increases as Vw increases from +4.0 V to +8.0 V (see Fig. 5b), which in turn suggests that multilevel current conduction can be maintained through the device.

To realize N-HZO films for memory applications, Au/Cr was formed on N-HZO/Si devices and charge transport was observed. The IV measurements of Au/Cr/N-HZO/Si provide further confirmation that Vw-controlled effective modulation of charge transport occurs. The IV curves after applying short voltage pulse widths (d, i.e., full width half maxima (FWHM) = 100 ns) of ±6.0 and ±8.0 V are shown in Fig. 5c. The pristine device, i.e., the device without Vw applied, exhibits very high resistance (R > 1012, i.e., the limitation of the system used), as shown in the red curve in Fig. 5c. In contrast, the current increases to a completely different high level (i.e., at Vr = +0.3 V) after applying a short Vw pulse of +6.0 V (d = 100 ns), as shown in the blue curve in Fig. 5c. 4×10 ^-8 A). What is important is that the current level switches frequently from high to low, but also to higher values (i.e., It is also possible to move to higher values by increasing the ^R On (i.e., Vr=+0.3 V, green curve in Fig. 5c), thereby providing multilevel current conductance at room temperature (RT) with the magnitude of Vw~+8.0 V (d = 100 ns). R _On (i.e., 10 ⁶ Ω) and R _Off (i.e., It is also clear that the switching potential can be reversed between the Vw of +8.0 and -8.0 V (d = 100 ns) at different levels (10 ¹² Ω), yielding an On/Off ratio larger than 10 ⁶ . Although it is generally expected that sub-nanometer thicknesses will be used to design FTJs, several other contributing factors such as device geometry, defect states, crystal orientation, and chemical composition may contribute to the change transport in the devices.

To verify the ultrafast switching, we first applied a short pulse (Vw = -8.0 V, d = 100 nm) to 10 randomly selected devices at lower levels (i.e., 10 ^-12 A) was programmed. Then, the current was monitored at Vr of +0.5 V while a short pulse (Vw = +8.0 V, d = 100 ns) was applied during the measurement. As expected from the IV curve, the current was initially low (<10 ^-12 A). However, after applying a short pulse of Vw (+8.0 V, d = 100 ns), the current increased to a higher level ( Set the rise time to 10 ^-6 A) Ultra-fast switching of 83 ns was confirmed (see Fig. 5d). Ultra-fast current switching for many cycles (>10 ³ ) was further tested by applying periodic write (Vw = +8.0, d = 200 ns) and erase pulses (-8.0 V, d = 200 ns) as shown in Fig. 5e and Fig. 5f. In fact, the device shows very stable current flipping while maintaining an On/Off ratio of more than 10 ⁶ , which is one of the key results for applying the device to real applications. In addition, the current level can be switched to completely different levels depending on the magnitude of the applied voltage. When Vw is +7.0 V, the current level can be switched to completely different levels. It is set to 10-6A to provide multi-level memory storage (see Fig. 5f). At this time, the energy (En = V × I × d) consumption during a write operation was also calculated, and it is about 3.2 pJ per bit, which is within the range of the latest memory devices.

The tunability of the multilevel R value was further verified. After applying a Vw cycle in the range of ±4.0 to ±8.0 V, the R vs. Vw characteristics fixed at Vr = +0.5 V for d = 100 ns (see Fig. 5g) are shown in Fig. 5g. As Vw increases, R remains high (i.e., off-state, >10 ¹² Ω) and does not change significantly between 0 → +3.5 V, but above that, R decreases sharply and remains at a low level for a Vw of +4.0 V (i.e., on-state, 10 ⁹ Ω). In contrast, R is relatively low ( 10 ⁹ ) is maintained, and further decreasing Vw resets the R value to the original level (>10 ¹² Ω). Also, the R _on /R _off ratio depends on the size of the Vw scanning window, for example, the R _On /R _Off ratio is ± 4.0 when Vw is 10 ³ half-face, after increasing Vw to ±8.0 The R vs. Vw curves showed a marked and significant hysteresis loop opening depending on the amplitude of Vw, indicating that the device can store multilevel nonvolatile bipolar programmable memory with an adjustable R _On /R _Off ratio at RT. This controlled variation of R _On ^/ R _Off is further computed as the tunneling resistance (TER) value, which is defined as (R _On - R _Off )/R _Off × 100%, and the TER is found to be 10 ⁸ %. Crucially, memory retention is one of the key features to significantly reduce power consumption. Therefore, to evaluate the data retention capability, R was evaluated at a constant Vr = +0.5 V for 4000 s after applying a single Vw pulse with different amplitudes (i.e., +4.0, +6.0, +7.0, and +8.0 V, d = 100 ns). As can be seen in Figure 5h, R remains at the flipped level and does not show any noticeable change with the number of cycles and/or the measurement period, indicating that the device stores data in nonvolatile programmable bipolar memory.

Ferroelectric polarization reversal is the most likely cause of resistive switching at the junction. Figure 5i shows simplified electrostatic potential profiles for two possible polarization directions (not limiting the invention). A positive pulse applied to the top electrode causes the polarization to be downwards, which modulates the potential barrier in a way that allows relatively smooth current flow, leading to the R _On state. On the other hand, a negative Vw flips the polarization upwards, resulting in high resistance values measured. Since the direction and amplitude of the effective polarization depend substantially on the magnitude of Vw (as seen from the PFM analysis, see Fig. 4), the height of the effective tunneling barrier can take on several values, leading to multilayer current conduction.

Now that we have demonstrated multilevel memory storage, we can implement a simple two-terminal device that performs logic operations using it. Most logic operations can be performed on a single device by combining the logic inputs (i.e., p and q) and the initial memory state of the device, which is determined by the inputs to two terminals (i.e., T1 and T2). By implementing logic concepts such as variables p and q, terminals T1 (upper electrode) and T2 (lower electrode), and logic values "0" and "1", we were able to realize a multi-logic memory framework.

As used in standard terminology, the logic variables p and q were 0 or 1, which correspond to the voltage levels applied to terminals T1 and T2, for example, 0 representing a low potential (i.e., 0 V) and 1 representing a high potential (i.e., +4.0 V). That is, voltages of +4.0×T1 and -4×T2 were applied to terminals T1 and T2, respectively, generating an effective potential difference of 4×(T1-T2) between the two electrodes. This operation results in output logic values "1" and "0" corresponding to voltages of +4.0 V (i.e., T1 = 1 and T2 = 0) or -4.0 V (i.e., T1 = 0 and T2 = 1), respectively. Also, as illustrated in the cartoon diagram of Fig. 6a, if the initial state Z' is known, we perform the inverse implication (RIMP) for Z' = "1", or the inverse implication (NIMP) for Z' = "0". In contrast, if the previous state Z' is unknown, we can specify the actual state by applying the following equation.

Z = (T1 RIMP T2) × Z' + (T1 NIMP T2) × (not Z')

For example, if Z' = "1" and T1 = q and T2 = p, this equation reduces to the implication (IMP):

Z = (q RIMP p) × 1 = p IMP q

In fact, depending on the Z' state, the device switches only for certain combinations of inputs. For example, a current level of "01", which occurs when T1 = 0 and T2 = 0, elicits the default function or state Z.

As can be seen from the initialization at the top of each panel in Fig. 6b, the output value can vary depending on the initial state, so in order to remove the randomness of the output value, the device uses a positive pulse to set the initial value to "0". To verify the logic operation such as NOR, a pulse bias voltage sequence was executed. As shown in Fig. 6c, the operations related to the need for different types of logic were performed (indicated in Cycles 1-3). Once the logic operation is completed, the result is stored in the memory without any intermediate readout step, and consequently the final output was read out at a voltage of Vr = +1.0 V (indicated by R at the top of the panel in Fig. 6b). In this context, a high current is represented by the number "0", while a low current is represented by the number "1". As a test, the combination of RIMP and NIMP can be used to implement the NOR logic using the following equation.

Z = p NOR q = ("0" RIMP p) × (not q) + ("0" NIMP p) × q

Through this test, we were able to derive a logic table for NOR, and when we compared it with the truth table of the Boolean function, we found that the two tables are compatible with each other (see Fig. 6c). Interestingly, our single device can execute 14 logic functions (Fig. 6d) with very high reproducibility.

As schematically shown in Fig. 6a, multilevel logic functions can be achieved in N-HZO-based devices beyond two stages. However, the magnitude of the operating voltages must be changed. Realizing multiple logic operations within a single device helps to reduce the need for spatially interconnecting multi-terminal devices. By performing input operations, most logic operations can be performed using a single device. However, one of the essential criteria is that the device has dynamic and highly stable current (or resistance) flipping in response to a sequence of input voltage pulses. It is also worth mentioning that 14 logic operations can be performed here by a combination of voltage pulses on the two-terminal electrodes. The complex polarization is advantageous for storing multilevel memory storage, which ultimately addresses the processing that is difficult to achieve with conventional ferroelectric tunnel junctions.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

100 Ferroelectric Logic-in-Memory Tunneling Devices
110 board
120 Ferroelectric section
121 Layer 1
122 2nd layer
200 Method for fabricating ferroelectric logic-in-memory tunneling devices

Claims (15)

substrate; and
A ferroelectric member formed on the substrate, each of which includes at least one layer of a first layer including HfO ₂ and a second layer including ZrO ₂ , wherein the first layer and the second layer are alternately laminated;
Ferroelectric logic-in-memory tunneling device. In the first paragraph,
The above ferroelectric logic-in-memory tunneling element further includes two or more electrodes spaced apart from each other and connected to the ferroelectric portion.
Ferroelectric logic-in-memory tunneling device. In the first paragraph,
The above substrate comprises silicon (Si).
Ferroelectric logic-in-memory tunneling device. In the first paragraph,
The above ferroelectric part has both the top and bottom layers as the first layer.
Ferroelectric logic-in-memory tunneling device. In paragraph 4,
The above ferroelectric portion comprises five layers,
Ferroelectric logic-in-memory tunneling device. In the first paragraph,
The orientation of the chemical species included in the above ferroelectric portion is random.
Ferroelectric logic-in-memory tunneling device. A ferroelectric member forming step comprising: a first layer forming step of forming a first layer including HfO ₂ on a substrate; and a second layer forming step of forming a second layer including ZrO ₂ on the substrate; alternately performing the steps; to form a ferroelectric member;
Method for fabricating ferroelectric logic-in-memory tunneling devices. In Article 7,
The first layer forming step and the second layer forming step are performed by atomic layer deposition (ALD).
Method for fabricating ferroelectric logic-in-memory tunneling devices. In Article 8,
The atomic layer deposition of the first layer above uses TDMAH (Tetrakis(dimethylamido)hafnium) as a precursor,
The atomic layer deposition of the second layer above uses TEMAZ (Tetrakis(ethylmethylamino)zirconium) as a precursor.
Method for fabricating a ferroelectric logic-in-memory tunneling device. In Article 7,
An electrode forming step of forming two or more electrodes spaced apart from each other and connected to the ferroelectric portion is further included;
Method for fabricating ferroelectric logic-in-memory tunneling devices. In Article 7,
The above substrate is prepared as a substrate containing silicon (Si).
Method for fabricating a ferroelectric logic-in-memory tunneling device. In Article 7,
The first layer forming step and the second layer forming step are performed so that both the uppermost and lowermost layers of the ferroelectric portion become the first layer.
Method for fabricating ferroelectric logic-in-memory tunneling devices. In Article 12,
The above first layer forming step and the above second layer forming step are performed a total of 5 times.
Method for fabricating ferroelectric logic-in-memory tunneling devices. A ferroelectric logic-in-memory tunneling device manufactured by a method for manufacturing a ferroelectric logic-in-memory tunneling device, comprising: a first layer forming step of forming a first layer including HfO ₂ on a substrate; and a second layer forming step of forming a second layer including ZrO ₂ on the substrate; alternately performing the steps of forming a ferroelectric portion;
Ferroelectric logic-in-memory tunneling device. In Article 14,
The orientation of the chemical species contained in the above ferroelectric portion is random.
Ferroelectric logic-in-memory tunneling device.