KR20240165898A - Semiconductor memory devices and methods of manufacturing the same - Google Patents

Abstract

A semiconductor memory device comprises storage electrodes arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of which extends in a third direction perpendicular to the first and second directions, and line support patterns provided between adjacent rows, each of which extends in the first direction and is arranged in the second direction, wherein each of the storage electrodes has a square shape in a planar view.

Description

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

The present application relates to a semiconductor memory device.

Due to their characteristics such as miniaturization, multi-functionality, and/or low manufacturing cost, semiconductor devices are attracting attention as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that perform computational processing of logic data, and hybrid semiconductor devices that include memory elements and logic elements.

Recently, as electronic devices become faster and consume less power, semiconductor devices embedded in them are required to have faster operating speeds and/or lower operating voltages. In order to meet these requirements, semiconductor devices are becoming more highly integrated.

Meanwhile, as the integration of semiconductor devices deepens, the electrical characteristics and reliability of semiconductor elements may deteriorate. Accordingly, much research is being conducted to improve the electrical characteristics and reliability of semiconductor devices.

The technical problem to be solved by the present application is to provide a semiconductor memory device with improved electrostatic capacity and a method for manufacturing the same.

A semiconductor memory device according to one embodiment of the present application comprises storage electrodes arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of which extends in a third direction perpendicular to the first and second directions, and line support patterns provided between adjacent rows, each of which extends in the first direction and is arranged in the second direction, wherein each of the storage electrodes may have a square shape in a planar view.

According to one embodiment of the present application, a semiconductor memory device includes: sequentially forming a sacrificial film and a support film on a substrate; forming first trenches extending in a first direction within the sacrificial film and the support film to define preliminary support patterns and preliminary sacrificial patterns extending in the first direction; forming storage electrode lines within the first trenches; patterning the storage electrode lines, the preliminary support patterns, and the preliminary sacrificial patterns to form second trenches extending in a second direction intersecting the first direction, storage electrodes, support patterns, and sacrificial patterns; the storage electrodes are arranged in the first and second directions to form rows and columns, and selectively depositing additional support patterns on the support patterns to form line support patterns, wherein each of the line support patterns is disposed between the adjacent columns and includes the support patterns and the additional support patterns alternately arranged in the first direction, and each of the storage electrodes may have a square shape in a planar view.

One embodiment of the present application provides a semiconductor memory device with improved electrostatic capacitance and a method for manufacturing the same.

FIG. 1 is a plan view showing a semiconductor memory device according to one embodiment of the present application.
Figure 2 is a cross-sectional view taken along lines A-A', B-B', and C-C' of Figure 1.
FIG. 3 is a cross-sectional view showing a semiconductor memory device according to one embodiment of the present application.
FIG. 4 is a cross-sectional view showing a semiconductor memory device according to one embodiment of the present application.
FIGS. 5A to 10A are plan views showing a method for manufacturing a semiconductor memory device according to one embodiment of the present application.
FIGS. 5b to 10b are cross-sectional views taken along lines A-A', B-B', and C-C' of FIGS. 5a to 10a, respectively.

Hereinafter, embodiments of the present application will be described in more detail with reference to the attached drawings.

Fig. 1 is a plan view showing a semiconductor memory device according to one embodiment of the present application. Fig. 2 is a cross-sectional view taken along lines A-A', B-B', and C-C' of Fig. 1.

Referring to FIGS. 1 and 2, a semiconductor memory device according to one embodiment of the present application may include a substrate (100), an interlayer insulating film (200) provided on the substrate (100), and capacitors (300) provided on the interlayer insulating film (200).

More specifically, a semiconductor memory device according to an embodiment of the present application may include a plurality of memory cells, and each of the memory cells may include a selection element and a storage element. Here, the storage element may store data, and the selection element may access a specific storage element in the memory cells to perform a read and write operation of data. In one embodiment, the storage element may correspond to a capacitor (300). In one embodiment, the selection element may be a transistor. For example, the selection element may be a MOS field effect transistor. The selection elements may be provided on a substrate (100), and an interlayer insulating film (200) may cover the selection elements. Details of the transistors that may be used as the selection elements will be described later.

The substrate (100) may be a semiconductor substrate including a semiconductor material, such as, for example, a silicon single crystal substrate, a germanium substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. The interlayer insulating film (200) may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low-k film. In addition, the interlayer insulating film (200) may function as an etch-stop film of a semiconductor memory device according to one embodiment of the present application.

The capacitors (300) may include storage electrodes (310), a capacitor dielectric film (350), and a common electrode (370). The storage electrodes (310) may be arranged in a first direction (D1) and a second direction (D2) intersecting the first direction (D1) to form rows and columns. In addition, the storage electrodes (310) may extend in a third direction (D3) perpendicular to the first and second directions (D1, D2), respectively. The storage electrodes (310) may be provided on an upper surface of the interlayer insulating film (200), respectively.

The storage electrodes (310) can be spaced apart from each other at a constant interval in the first direction (D1) and the second direction (D2). In other words, the storage electrodes (310) can be arranged in the first direction (D1) and the second direction (D2) in a planar view. For example, the storage electrodes (310) can be arranged in a checkerboard pattern in a planar view.

In one embodiment, each of the storage electrodes (310) may be electrically connected to a terminal of a corresponding one of the selection elements. In this case, the storage electrodes (310) may penetrate the interlayer insulating film (200). The storage electrodes (310) may accumulate charges stored in the memory cells. That is, the storage electrodes (310) may function as a capacitor that stores data signals by storing charges received from the selection elements of the semiconductor memory device.

The storage electrodes (310) may include a conductive material. The storage electrode (310) may include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. In one embodiment, the storage electrode (310) may include titanium nitride (TiN).

In one embodiment, each of the storage electrodes (310) may have a square shape in a planar view. For example, each of the storage electrodes (310) may have a square shape in a planar view.

The storage electrodes (310) according to one embodiment of the present application have a square shape in a planar view, so that the surface area can be increased. Here, the surface area can mean an area that can face the common electrode (370).

When the surface area of the storage electrodes (310) increases, the space in which an electric field can be formed can be expanded. As a result, the physical space in which charges can be accumulated within the electrodes can be increased. That is, the density of charges within the storage electrodes (310) can be increased. As a result, the capacitance of the semiconductor memory device can be increased.

In one embodiment, line support patterns (330) may be provided. Each of the line support patterns (330) may be provided between the rows of adjacent storage electrodes (310). The line support patterns (330) may extend in a first direction (D1) and be arranged in a second direction (D2).

The line support patterns (330) can be in contact with the storage electrodes (310). More specifically, the line support patterns (330) can be in contact with side surfaces of each of the storage electrodes (310) that are parallel to the first direction (D1). That is, the line support patterns (330) can be in contact with the side surfaces of the storage electrodes (310) and extend in the first direction (D1) across the storage electrodes (310).

The line support patterns (330) can physically support the storage electrodes (310) so that they can be stably maintained by coming into contact with the storage electrodes (310). The line support patterns (330) can also electrically insulate the storage electrodes (310). More specifically, the line support patterns (330) can prevent the storage electrodes (310) from collapsing due to external force or stress. In addition, the line support patterns (330) can prevent electrical interference between the storage electrodes (310).

The line support patterns (330) may be composed of an insulating material having etch selectivity with respect to the storage electrodes (310). The line support patterns may include, for example, silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof.

In one embodiment, each of the line support patterns (330) may include a plurality of stacked line support patterns, and the plurality of stacked line support patterns (330) may be spaced apart from each other in the third direction (D3). In other words, the line support patterns (330) may form a structure that is stacked in the third direction (D3) and may be spaced apart from each other in the third direction (D3). Here, the number of stacked line support patterns (330) may vary. For example, as illustrated in FIG. 2, the line support patterns (330) may be stacked in three layers.

In one embodiment, each of the line support patterns (330) may include support patterns (331) and additional support patterns (333). More specifically, each of the line support patterns (330) may include support patterns (331) and additional support patterns (333) that are alternately and repeatedly arranged in the first direction (D1) and directly connected to each other.

The support patterns (331) can be in contact with the storage electrodes (310). More specifically, the support patterns (331) can be in contact with the storage electrodes (310) of the rows of adjacent storage electrodes (310). That is, the support patterns (331) included in each of the line support patterns (330) can be in contact with the side surfaces of the storage electrodes (310) of the rows of adjacent storage electrodes, respectively.

The additional support patterns (333) may be those portions of the line support patterns (330) that do not come into contact with the storage electrodes (310). More specifically, the additional support patterns (333) may be provided in portions of the line support patterns (330) where the support patterns (331) are not provided, thereby forming the line support patterns (330) together with the support patterns (331). For example, each of the support patterns (331) and each of the additional support patterns (333) may be alternately arranged in a first direction (D1) in a planar view, thereby forming the line support patterns (330). The line support patterns (330) may be arranged in a second direction (D2) in a planar view.

In one embodiment, the additional support patterns (333) may each include edge portions (333a) and an intermediate portion (333b). Here, the edge portions (333a) may be both end portions adjacent to the support patterns (331) in the additional support pattern (333), and the intermediate portion (333b) may be a central portion provided between the edge portions (333a) in the additional support pattern (333). In one embodiment, the thickness of the intermediate portion (333b) may be smaller than the thicknesses of the edge portions (333a). Similarly, the width of the intermediate portion (333b) may be smaller than the widths of the edge portions (333a). Here, the thickness may be the length in the third direction (D3) of the additional support pattern (333) as illustrated in FIG. 2, and the width may be the length in the second direction (D2) of the additional support pattern (333) as illustrated in FIG. 1.

In one embodiment, unlike that illustrated in FIG. 2, the additional support patterns (333) may extend on the upper surfaces of the support patterns (331). For example, an additional support pattern (333) having an upwardly convex shape may be additionally formed on the upper surface of each of the support patterns (331). Accordingly, the additional support pattern (333) may be provided on the upper surface of each of the support patterns (331) to form a mushroom shape. However, the embodiment of the present application is not limited thereto, and the formation of the additional support pattern (333) on the upper surface of each of the support patterns (331) may be omitted.

In one embodiment, the support patterns (331) and the additional support patterns (333) may include silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. Additionally, the support patterns (331) and the additional support patterns (333) may be formed of substantially the same material as each other.

A capacitor dielectric film (350) may be provided on the storage electrodes (310), the line support patterns (330), and the interlayer insulating film (200). The capacitor dielectric film (350) may be conformally formed on the storage electrodes (310), the line support patterns (330), and the interlayer insulating film (200). In addition, unlike what is illustrated in FIG. 2, the capacitor dielectric film (350) may include a plurality of films.

The capacitor dielectric film (350) can insulate between the common electrode (370) and the storage electrodes (310). As a result, the charges stored in the memory cells cannot move to the common electrode (370) and can be accumulated on the surface of the storage electrodes (310). That is, the capacitor dielectric film (350) can perform a function of accumulating the charges stored in the memory cells on the surface of the storage electrode (310).

The capacitor dielectric film (350) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material including a metal, or a combination thereof.

A common electrode (370) may be provided on the capacitor dielectric film (350). The common electrode (370) may fill a space between the storage electrodes (310), the line support patterns (330), and the capacitor dielectric film (350).

The common electrode (370) can store charges with the storage electrodes (310) and the capacitor dielectric film (350) interposed therebetween. More specifically, when voltage is applied to the capacitors (300), charges having opposite signs to the charges accumulated in the storage electrodes (310) can be accumulated on the surface of the common electrode (370). Accordingly, the charges of the common electrode (370) and the storage electrodes (310) can form an electric field, and data transmitted from the selection elements through the electric field can be stored in the capacitors (300). In addition, the capacitors (300) can determine data signals transmitted from the selection elements through the difference in the amount of charges between the common electrode (370) and the storage electrodes (310).

The common electrode (370) may include a doped n-type impurity or a p-type impurity. The common electrode (370) may include, for example, a metal, a metal nitride, a metal silicide, doped silicon-germanium, or a combination thereof.

Meanwhile, examples of transistors that can be used as the above selection elements are described below.

FIG. 3 is a cross-sectional view illustrating a semiconductor memory device according to one embodiment of the present application. More specifically, the left cross-sectional view of FIG. 3 may correspond to a cross-sectional view taken along the width direction of a bit line, and the right cross-sectional view may correspond to a cross-sectional view taken along the width direction of a word line.

Referring to FIG. 3, active patterns (AP) may be provided. The active patterns (AP) may be provided between element separation patterns (IP). Each of the active patterns (AP) may have an island shape separated from each other and may have a bar shape extending in a direction perpendicular to the width direction and the length direction of the bit lines (BL). Here, the extension direction of the active patterns (AP) may be perpendicular to the lower surface of the substrate (100). In a planar view, the active patterns (AP) may be parts of the substrate (100) surrounded by the element separation patterns (IP).

In one embodiment, first impurity regions and second impurity regions may be provided within the active patterns (AP). The second impurity regions may be provided within both edge regions of each of the active patterns (AP). Each of the first impurity regions may be interposed between the second impurity regions within each of the active patterns (AP). For example, each of the first impurity regions may be provided on a lower surface of each of the bit line contacts (BTC). The first impurity regions may include impurities of the same conductivity type (e.g., N type) as the second impurity regions.

Device isolation patterns (IP) may be arranged in the substrate (100) and may define active patterns (AP). The device isolation patterns (IP) may be arranged spaced apart from each other in the width direction and the length direction of the bit line (BL), respectively. The device isolation patterns (IP) may include an insulating material. The device isolation patterns (IP) may include, for example, at least one of silicon oxide or silicon nitride, or a combination thereof.

The word lines (WL) may be provided within the active patterns (AP). In one embodiment, the word lines (WL) may be provided in plural. The word lines (WL) may extend in a direction parallel to the width direction of the bit lines (BL) and may be spaced apart from each other in a direction parallel to the length direction of the bit lines (BL). For example, a pair of word lines (WL) adjacent to each other in the length direction of the bit lines (BL) may cross each of the active patterns (AP). That is, the word lines (WL) may extend in the width direction of the bit lines (BL) and penetrate the active patterns (AP) and the device isolation patterns (IP). The word lines (WL) may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, polysilicon doped with impurities, or a combination thereof.

A word line insulating pattern (WLI) may be provided between a word line (WL) and the active pattern (AP), and between the word line (WL) and a device isolation pattern (IP). A word line capping pattern (WLC) may be provided on an upper surface of the word line (WL) to cover the word line (WL). The word line insulating pattern (WLI) and the word line capping pattern (WLC) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

A buffer pattern (BF) may be provided on the substrate (100). More specifically, the buffer pattern (BF) may be provided on upper surfaces of the active patterns (AP), the device isolation patterns (IP), and the word lines (WL). That is, the buffer pattern (BF) may cover the active patterns (AP), the device isolation patterns (IP), and the word lines (WL). The buffer pattern (BF) may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof.

The bit lines (BL) may be provided on the element isolation pattern (IP) and the active patterns (AP). In one embodiment, the bit lines (BL) may be provided in plural. The bit lines (BL) may extend in a direction parallel to the width direction of the word lines (WL) and may be spaced apart from each other in a direction parallel to the length direction of the word lines (WL). Here, the width direction of the word lines (WL) may be substantially the same as the length direction of the bit lines (BL), and the length direction of the word lines (WL) may be substantially the same as the width direction of the bit lines (BL). That is, the bit lines (BL) and the word lines (WL) may be orthogonal to each other in a planar view. The bit lines (BL) may include a conductive metal material. The bit lines (BL) may include, for example, tungsten, rubidium, molybdenum, or titanium, or a combination thereof.

A bit line capping pattern (BCP) may be provided on an upper surface of a bit line (BL). In one embodiment, a plurality of bit line capping patterns (BCP) may be provided. The bit line capping patterns (BCP) may extend in the width direction of the word lines (WL) along the corresponding bit line (BL), respectively, and may be spaced apart from each other in the length direction of the word lines (WL). The bit line capping pattern (BCP) may vertically overlap the bit line (BL). The bit line capping pattern (BCP) may include, for example, silicon nitride.

A bit line contact (BTC) may be provided within each of the first recessed regions (RS1). The first recessed regions (RS1) may be provided on top of the active patterns (AP) and on top of the device isolation pattern (IP) adjacent to the top of the active patterns (AP). Each of the first recessed regions (RS1) may be spaced apart from each other in the width direction of the bit lines (BL) and the length direction of the bit lines (BL) in a planar view.

Since the bit line contacts (BTC) are provided in each of the first recessed regions (RS1), the bit line contacts (BTC) can be provided on the upper surfaces of each of some of the active patterns (AP). Here, the some may mean those of the active patterns (AP) in which the first impurity region is provided. That is, the bit line contacts (BTC) can be connected to the first impurity regions in the active patterns (AP), respectively. The bit line contacts (BTC) can be spaced apart from each other in the width direction of the bit lines (BL) and the length direction of the bit lines (BL) in a planar view. The bit line contacts (BTC) can be provided between the active patterns (AP) and the bit lines (BL), respectively. The bit line contacts (BTC) can electrically connect a corresponding bit line (BL) among the bit lines (BL) and a corresponding first impurity region.

The buried pattern (BP) can fill each of the first recessed regions (RS1). The buried pattern (BP) can conformally cover at least a portion of the inner surface of the first recessed region (RS1) and side surfaces of the bit line contact (BTC). That is, the buried pattern (BP) can fill the remaining portion except for the portion in which the bit line contact (BTC) is provided within the first recessed region (RS1). The buried pattern (BP) can include, for example, silicon oxide, silicon nitride, or a combination thereof.

A bit line spacer (SPC) may be provided on side surfaces of a bit line (BL) and side surfaces of a bit line capping pattern (BCP). The bit line spacer (SPC) may cover the side surfaces of the bit line (BL) and the side surfaces of the bit line capping pattern (BCP).

In one embodiment, the bit line spacer (SPC) can cover an upper surface of the bit line capping pattern (BCP). The bit line spacer (SPC) can contact the side surfaces of the bit line capping pattern (BCP). The bit line spacer (SPC) can include, for example, silicon oxide, silicon nitride, or a combination thereof. In one embodiment, the bit line spacer (SPC) can include an empty space including an air layer (i.e., an air gap).

The storage electrode contacts (SC) may be provided between neighboring bit lines (BL). In one embodiment, the storage electrode contacts (SC) may be provided in plural. The storage electrode contacts (SC) may be spaced apart from each other in the width direction of the bit lines (BL) and the length direction of the bit lines (BL) in a planar view, respectively. Each of the storage electrode contacts (SC) may fill each of the second recess regions (RS2) provided on the second impurity regions in the active patterns (AP). Accordingly, each of the storage electrode contacts (SC) may be electrically connected to each of the corresponding second impurity regions. The storage electrode contacts (SC) may include, for example, at least one of polysilicon, a conductive metal material, or a combination thereof.

A landing pad (LP) may be provided on the storage electrode contact (SC). In one embodiment, a plurality of landing pads (LP) may be provided. For example, each of the landing pads (LP) may be provided on an upper surface of each of the storage electrode contacts (SC). In addition, each of the landing pads (LP) may be provided between adjacent filling patterns (FP) and between bit line spacers (SPC). The landing pads (LP) may be spaced apart from each other in the width direction of the bit lines (BL) and the length direction of the bit lines (BL) in a planar view. That is, each of the landing pads (LP) may be electrically connected to each of the corresponding storage electrode contacts (SC).

The landing pad (LP) may include a lower landing pad and an upper landing pad. The lower landing pad may be a lower region of the landing pad (LP) and may vertically overlap a corresponding storage electrode contact (SC). The upper landing pad may be an upper region of the landing pad (LP) and may be shifted in the width direction of the bit line from the lower landing pad. The landing pad (LP) may include, for example, tungsten, titanium, tantalum, or a combination thereof.

The filling pattern (FP) can surround each of the landing pads (LP). The filling pattern (FP) can be provided between adjacent landing pads (LP). In a planar view, the filling pattern (FP) can have a mesh shape including holes penetrated by the landing pads (LP). That is, the filling pattern (FP) can define a plurality of landing pads (LP) in a planar view. In one embodiment, the filling pattern (FP) can include an empty space (i.e., an air gap) including an air layer therein. The filling pattern (FP) can include, for example, silicon nitride, silicon oxide, or silicon oxynitride, or a combination thereof.

In one embodiment, each of the storage electrodes (310) may be provided on the upper surfaces of the landing pads (LP). In addition, the description of the storage electrodes (310), the line support patterns (330), the capacitor dielectric film (350), and the common electrode (370) may be substantially the same and/or similar to those described above.

The active patterns (AP) including a portion of the above-described word line (WL) and the second impurity regions and the first impurity region provided between the second impurity regions can constitute one transistor. The transistor can be, for example, a recessed channel array transistor (RCAT).

Meanwhile, other types of transistors that can be used as the above selection elements are described below.

Fig. 4 is a cross-sectional view showing a semiconductor memory device according to one embodiment of the present application. More specifically, the left cross-sectional view of Fig. 4 may correspond to a cross-sectional view taken along the width direction of a word line, and the right cross-sectional view may correspond to a cross-sectional view taken along the width direction of a bit line.

Referring to FIG. 4, active patterns (AP) may be provided. The active pattern (AP) may be provided between the word line (WL) and the back gate line (BG). In one embodiment, the semiconductor memory device may include a plurality of active patterns (AP). The active patterns (AP) may be provided on upper surfaces of the bit lines (BL). Each of the active patterns (AP) may be arranged in the width direction and the length direction of the bit lines (BL) in a planar view. The active patterns (AP) may extend in a direction perpendicular to the width direction and the length direction of the bit lines (BL). That is, the active patterns (AP) may be orthogonal to the bit lines (BL).

In one embodiment, the active pattern (AP) can include a first source/drain region, a second source/drain region, and a channel region. The first source/drain region can be formed at an upper portion of the active pattern (AP), and the second source/drain region can be formed at a lower portion of the active pattern (AP).

In one embodiment, the first source/drain region can be connected to a landing pad (LP), and the second source/drain region can be connected to a bit line (BL). The first and second source/drain regions can function as a source or a drain, respectively. The channel region can function as a passage through which carriers move between the source and the drain. The first and second source/drain regions can be regions doped with impurities having different conductivity types from the channel region. For example, when the channel region includes impurities of the first conductivity type, the first and second source/drain regions can be regions doped with impurities of the opposite second conductivity type. For example, the impurities of the first conductivity type can be p-type impurities such as boron (B), a group III element, and the impurities of the second conductivity type can include n-type impurities such as phosphorus (P) and/or arsenic (As), a group V element.

A bit line (BL) is provided and can extend in the width direction of the word line (WL).

That is, the bit line (BL) may extend vertically intersecting the word line (WL). In one embodiment, the semiconductor memory device may include a plurality of bit lines (BL), and the bit lines (BL) may be spaced apart from each other at a constant interval along the length direction of the word line (WL). More specifically, the bit lines (BL) may be respectively arranged in the length direction of the word line (WL) and may extend in the width direction of the word line (WL) to be connected to the lower surfaces of the active patterns (AP). The bit line (BL) may include a conductive metal material. The bit line (BL) may include, for example, tungsten, rubidium, molybdenum, titanium, or a combination thereof.

A bit line insulating pattern (BIP) may be provided on a lower surface of the bit lines (BL). The bit line insulating pattern (BIP) may be a film in which an insulating material is conformally formed on lower surfaces of the active patterns (AP), lower surfaces of the bit lines (BL), lower surfaces of the word line capping patterns (WLC), and lower surfaces of the back gate capping patterns (BGC). The bit line insulating pattern (BIP) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a low-k insulating material, or a combination thereof.

A bit line dielectric film (DI) may be provided on the lower surfaces of the bit lines (BL). The bit line dielectric film (DI) may be a film conformally formed on the lower surface of the bit line insulating pattern (BIP). The bit line dielectric film (DI) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material including a metal, or a combination thereof.

A gap structure (SH) may be provided between bit lines (BL) and on a lower surface of a bit line dielectric film (DI). In one embodiment, the gap structure (SH) may function as a shielding line of a semiconductor memory device. The gap structure (SH) may extend in a direction parallel to a longitudinal direction of the bit lines (BL) between the bit lines (BL) and on the bit line dielectric film (DI). The gap structure (SH) may be made of, for example, a conductive material and may include an air gap therein. In one embodiment, the gap structure (SH) may be omitted.

A word line (WL) may be provided between a word line separation pattern (WIP) and an active pattern (AP). More specifically, the word line (WL) may be provided between one side of the word line separation pattern (WIP) and one side of the active pattern (AP). In addition, a lower surface of the word line (WL) may be located at a higher level than a lower surface of the active pattern (AP). That is, the word line (WL) may be spaced apart from upper surfaces of the bit lines (BL) in a direction parallel to an extension direction of the active pattern (AP).

The word line (WL) may extend in the width direction of the bit line (BL). That is, the word line (WL) may extend vertically intersecting the bit line (BL). In one embodiment, the semiconductor memory device may include a plurality of word lines (WL). The word lines (WL) may be spaced apart from each other at a constant interval along the length direction of the bit line (BL). As illustrated in the left cross-section of FIG. 4, each of the word lines (WL) may be provided on one side of each of the active patterns (AP). The word line (WL) may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, polysilicon doped with impurities, or a combination thereof.

A word line insulating pattern (WLI) may be provided between the word line (WL) and the active pattern (AP). More specifically, as illustrated in the left cross-section of FIG. 4, the word line insulating pattern (WLI) may be provided between one side of the word line (WL) on which the word line separation pattern (WIP) is not provided and one side of the active pattern (AP). The word line insulating pattern (WLI) may extend in the width direction of the bit line (BL) like the word line (WL). In one embodiment, the word line insulating pattern (WLI) may be provided in plural. Each of the word line insulating patterns (WLI) may be spaced apart from each other at a constant interval along the length direction of the bit line (BL).

Word line capping patterns (WLC) may be provided on upper surfaces of the word lines (WL) and lower surfaces of the word lines (WL). More specifically, the word line capping patterns (WLC) may be provided on upper surfaces of opposite word lines (WL) that are adjacent to each other to electrically insulate between the word lines (WL) and the storage electrodes (310). In addition, the word line capping patterns (WLC) may be provided on lower surfaces of opposite word lines (WL) that are adjacent to each other to electrically insulate between the word lines (WL) and the bit lines (BL).

Word line separation patterns (WIP) can be provided between adjacent and opposing word lines (WL), respectively. More specifically, the word line separation patterns (WIP) can be provided between adjacent word lines (WL) and between word line capping patterns (WLC) corresponding to adjacent word lines (WL). That is, the word line separation patterns (WIP) can electrically insulate between adjacent word lines (WL) together with the word line capping patterns (WLC).

The word line insulation patterns (WLI), word line capping patterns (WLC), and word line separation patterns (WIP) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

A back gate line (BG) may be provided between adjacent active patterns (AP). More specifically, the back gate line (BG) may be provided between back gate insulating patterns (BGI) facing each other. A lower surface of the back gate line (BG) may be located at a higher level than a lower surface of the active pattern (AP). In addition, the lower surface of the back gate line (BG) may be located at a level substantially equal to or higher than a lower surface of the word line (WL). That is, the back gate line (BG) may be spaced apart from upper surfaces of the bit lines (BL) in a direction parallel to an extension direction of the active pattern (AP).

The back gate line (BG) may extend in the width direction of the bit line (BL). That is, the back gate line (BG) may extend so as to perpendicularly intersect the bit line (BL). In one embodiment, the semiconductor memory device may include a plurality of back gate lines (BG), and each of the back gate lines (BG) may be spaced apart from each other by a constant interval along the length direction of the bit line (BL). That is, each of the back gate lines (BG) may be arranged parallel to the word line (WL). As illustrated in the left cross-section of FIG. 4, each of the back gate lines (BG) may be provided on a different side of each of the active patterns (AP). Here, the different side may mean a side opposite to the one side of the side of the active patterns (AP) on which the word line (WL) is provided, that is, the other side on which the word line (WL) is not provided. The back gate line (BG) may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, doped polysilicon, or a combination thereof.

A back gate insulating pattern (BGI) may be provided between the back gate line (BG) and the active pattern (AP). More specifically, as illustrated in the left cross-section of FIG. 4, the back gate insulating pattern (BGI) may be provided on each of the two side surfaces of the back gate line (BG). That is, the back gate insulating patterns (BGI) may be provided on both side surfaces of the back gate line (BG) to cover both side surfaces of the back gate line (BG). The back gate insulating patterns (BGI) may extend in the width direction of the bit line (BL) like the back gate lines (BG). Each of the back gate insulating patterns (BGI) may be spaced apart from each other at a constant interval along the length direction of the bit line (BL).

Back gate capping patterns (BGC) may be provided on upper surfaces of the back gate lines (BG) and lower surfaces of the back gate lines (BG). Additionally, the back gate capping patterns (BGC) may be provided between back gate insulating patterns (BGI). The back gate capping patterns (BGC) may electrically insulate between the active patterns (AP) and the back gate lines (BG), and between the bit lines (BG) and the back gate lines (BG).

The back gate insulating patterns (BGI) and back gate capping patterns (BGC) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

In one embodiment, each of the storage electrodes (310) may be provided on the upper surfaces of the active patterns (AP). In addition, the description of the storage electrodes (310), the line support patterns (330), the capacitor dielectric film (350), and the common electrode (370) may be substantially the same and/or similar to the above-described contents.

Part of the active pattern (AP), the word line (WL), and the back gate line (BG), including the first source/drain region (SD1), the second source/drain region (SD2), and the channel region (CA) described above, can constitute one transistor. The transistor can be, for example, a vertical channel transistor (VCT).

Below, a method for manufacturing capacitors according to one embodiment of the present application is described.

FIGS. 5A to 10A are plan views showing a method for manufacturing a semiconductor memory device according to one embodiment of the present application. FIGS. 5B to 10B are cross-sectional views taken along lines A-A', B-B', and C-C' of FIGS. 5A to 10A, respectively.

Referring to FIGS. 5A and 5B, a substrate (100) may be prepared. The substrate (100) may be, for example, a silicon substrate, a germanium substrate, and/or a silicon-germanium substrate. An interlayer insulating film (200) may be formed on an upper surface of the substrate (100). The interlayer insulating film (200) may be formed by at least one of an oxidation process and a deposition process.

In some embodiments, the transistors and bit lines (BL) of FIG. 3 may be formed before the interlayer insulating film (200) is formed. Alternatively, the transistors and bit lines (BL) of FIG. 4 may be formed before the interlayer insulating film (200) is formed.

Thereafter, a sacrificial film and a supporting film may be sequentially formed on the upper surface of the substrate (100). The sacrificial film may include, for example, silicon oxide. The supporting film may include, for example, silicon nitride, silicon boron nitride, silicon carbon nitride, or a combination thereof. The formation of the sacrificial film and the supporting film may be formed by at least one of an oxidation process or a deposition process.

In one embodiment, the sacrificial film and the support film may be alternately and repeatedly formed in multiple numbers. For example, three support films may be formed on the substrate (100) in a third direction (D3) perpendicular to the upper surface of the substrate (100), and a sacrificial film may be formed on each upper surface of the three support films, thereby forming three stacked sacrificial films. The stacked sacrificial films may be spaced apart from each other in the third direction (D3). However, the number of sacrificial films and support films formed is not limited thereto, and for example, one sacrificial film and one support film may be formed on the substrate (100).

Next, a patterning process may be performed on the sacrificial films and the support films to form first trenches (TCH1). The first trenches (TCH1) may extend from the uppermost surface of the support films toward the lowermost surface of the sacrificial film. That is, the first trenches (TCH1) may penetrate the support films and the sacrificial films in a direction opposite to the third direction (D3). Each of the first trenches (TCH1) may extend in the first direction (D1) in a planar view and may be arranged in a second direction (D2) intersecting the first direction (D1).

Meanwhile, the first trench (TCH1) may not penetrate the interlayer insulating film (200) in FIG. 5b. However, the embodiments of the present application are not limited thereto. The first trench (TCH1) may penetrate the interlayer insulating film (200), as shown in FIGS. 3 and 4.

Due to the formation of the first trenches (TCH1), preliminary support patterns (330P) and preliminary sacrificial patterns (210P) can be defined. The preliminary support patterns (330P) and the preliminary sacrificial patterns (210P) can each extend in the first direction (D1) and be arranged in the second direction (D2).

Referring to FIGS. 6A and 6B, a storage electrode film may be formed in the first trenches (TCH1) to fill the first trenches (TCH1). The formation of the storage electrode film may be performed through a deposition process. Thereafter, an etching process may be performed on the storage electrode film to expose the preliminary support patterns (330P). The etching process may be performed through a chemical mechanical polishing process. Accordingly, storage electrode lines (310L) may be formed. Each of the storage electrode lines (310L) may be formed in each of the first trenches (TCH1). Each of the storage electrode lines (310L) may extend in a first direction (D1) in a planar view and may be arranged in a second direction (D2) intersecting the first direction.

The storage electrode lines (310L) may include a metal, a metal nitride, a metal silicide, or a combination thereof. The storage electrode lines (310L) may include, for example, titanium nitride (TiN).

Referring to FIGS. 7A and 7B, a patterning process may be performed on the storage electrode lines (310L), the preliminary support patterns (330P), and the preliminary sacrificial patterns (210P) to form second trenches (TCH2), storage electrodes (310), the support patterns (331), and the sacrificial patterns (210).

More specifically, the storage electrode lines (310L), the preliminary support patterns (330P), and the preliminary sacrificial patterns (210P) may be patterned in a second direction (D2) in a planar view so that second trenches (TCH2) extending in the second direction (D2) may be formed. The second trenches (TCH2) may penetrate the storage electrode lines (310L), the preliminary support patterns (330P), and the preliminary sacrificial patterns (210P) in an opposite direction to the third direction (D3). Each of the second trenches (TCH2) may extend in the second direction (D2) in a planar view and may be arranged in the first direction (D1).

Meanwhile, the second trench (TCH2) may not penetrate the interlayer insulating film (200) in FIG. 7b. However, the embodiments of the present application are not limited thereto. The second trench (TCH2) may penetrate the interlayer insulating film (200), as shown in FIGS. 3 and 4.

By forming the second trenches (TCH2), storage electrodes (310), support patterns (331), and sacrificial patterns (210) can be defined. At this time, the storage electrodes (310) can be arranged in the first and second directions (D1, D2) to form rows and columns. In addition, the support patterns (331) and the sacrificial patterns (210) can be in contact with the storage electrodes (310) of the rows of the adjacent storage electrodes (310).

By forming the first trenches (TCH1) and the second trenches (TCH2), each of the storage electrodes (310) according to one embodiment of the present application can have a square shape in a planar view.

Referring to FIGS. 8a and 8b, a deposition process may be performed on sacrificial patterns (210) and storage electrodes (310) to form a first deposition-inhibiting layer (230) and a second deposition-inhibiting layer (250).

More specifically, a first deposition-inhibiting layer (230) can be formed on the exposed surfaces of the sacrificial patterns (210). The first deposition-inhibiting layer (230) can include, for example, polymethylmethacrylate (PMMA), alkylsilane, ethylene, propylene, trifluoroethylene (TFE), hexafluoropropylene (HFP), polytetrafluoroethylene (PTFE), or a combination thereof. In one embodiment, the first deposition-inhibiting layer (230) can include dimethylaminotrimethylsilane (DMATMS), dimethyldimethylaminosilane (DMADMS), or dimethylamino-fluorosilane.

Next, a second deposition-inhibiting layer (250) can be formed on the exposed surfaces of the storage electrodes (310). The second deposition-inhibiting layer (250) can include, for example, polymethylmethacrylate (PMMA), alkylsilane, ethylene, propylene, trifluoroethylene (TFE), hexafluoropropylene (HFP), polytetrafluoroethylene (PTFE), or a combination thereof. In one embodiment, the second deposition-inhibiting layer (250) can include a different material than the first deposition-inhibiting layer (230). The second deposition-inhibiting layer (250) can include, for example, 5-decyne, an alkyl phosphonic acid, a phosphonic acid, and a carboxylic acid, or a combination thereof.

The first and second deposition-suppressing layers (230, 250) may be formed through a deposition process. The first and second deposition-suppressing layers (230, 250) may be formed through, for example, a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or a spin coating method, respectively.

Referring to FIGS. 9a and 9b, an area selective deposition process may be performed on support patterns (331) to form additional support patterns (333).

More specifically, the deposition of the additional support patterns (333) can be performed on surfaces exposed on the substrate (100). At this time, the deposition rate of the additional support patterns (333) on the support patterns (331) can be greater than the deposition rate of the additional support patterns (333) on the first and second deposition-inhibiting layers (230, 250). In other words, the first deposition-inhibiting layer (230) and the second deposition-inhibiting layer (250) can inhibit the deposition of the additional support patterns (333). Accordingly, the selective deposition of the additional support patterns (333) can be performed on the exposed surfaces of the support patterns (331). Accordingly, the additional support patterns (333) can be formed on side surfaces of the support patterns (331) that are parallel to the second direction (D2). As a result, in a planar view, the support patterns (331) and the additional support patterns (333) can be connected to each other to form a plurality of lines, each of which is arranged alternately and repeatedly in the first direction (D1), and the lines can be arranged in the second direction (D2) to form line support patterns (330).

In one embodiment, although not shown, additional support patterns (333) may be formed on the upper surfaces of the support patterns (331) and may extend from portions formed on the side surfaces of the support patterns (331) that are parallel to the second direction (D2). Accordingly, the additional support patterns (333) may extend in the first direction (D1).

In one embodiment, each of the additional support patterns (333) may include edge portions (333a) adjacent to the support patterns (331) and an intermediate portion (333b) provided between the edge portions (333a). Since the additional support patterns (333) are formed from side surfaces of the support patterns (331) that are parallel to the second direction (D2), they may be formed sequentially from the edge portions (333a) to the intermediate portion (333b). In one embodiment, the level of the lower surface of each of the additional support patterns (333) may increase from the edge portion (333a) to the intermediate portion (333b).

In one embodiment, the additional support patterns (333) may include silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof.

Referring to FIGS. 10A and 10B , the first and second deposition-inhibiting layers (230, 250) can be removed. The removal of the first and second deposition-inhibiting layers (230, 250) can be performed, for example, through an etching process, a cleaning process, a deposition process, or a heat treatment process. In one embodiment, the removal of the first and second deposition-inhibiting layers (230, 250) can be performed simultaneously. For example, the first and second deposition-inhibiting layers (230, 250) can be removed through a plasma cleaning process using ammonia (NH ₃ ), nitrogen fluoride (NF ₃ ), or nitrogen (N ₂ ).

Thereafter, an etching process may be performed to remove the sacrificial patterns (210). The etching process may be performed using a material having etching selectivity with respect to the line support patterns (330) and the storage electrodes (310). As a result, selective etching of the sacrificial patterns (210) may be performed while maintaining the line support patterns (330) and the storage electrodes (310).

Referring again to FIGS. 1 and 2, an oxidation process or a deposition process may be performed, whereby a capacitor dielectric film (350) may be conformally formed on the storage electrodes (310) and the line support patterns (330) and the interlayer insulating film (200).

Thereafter, a deposition process may be performed so that a common electrode (370) may be formed on the capacitor dielectric film (350). The common electrode (370) may fill the empty space between the storage electrodes (310), the line support patterns (330), and the capacitor dielectric film (350).

Through the above-described process, capacitors (300) of a semiconductor memory device according to one embodiment of the present application can be finally formed.

Although the present application has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes may be made to the present application without departing from the spirit and technical scope of the present invention as set forth in the claims below.

Therefore, the technical scope of the present application should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

100 board 300 capacitor
310 storage electrode 330 line support pattern
331 Support Pattern 333 Additional Support Pattern
333a edge 333b middle
350 capacitor dielectric film 370 common electrode

Claims (10)

Storage electrodes arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each extending in a third direction perpendicular to the first and second directions; and
Each of the line support patterns is provided between the adjacent rows, extending in the first direction and arranged in the second direction,
A semiconductor memory device wherein each of the above storage electrodes has a square shape in a planar view. In the first paragraph,
Each of the above line support patterns:
It comprises support patterns and additional support patterns which are arranged alternately and repeatedly in the first direction and are directly connected to each other,
A semiconductor memory device wherein the support patterns are in contact with the storage electrodes of the adjacent rows. In the second paragraph,
Each of the above additional support patterns includes edge portions adjacent to the support patterns and an intermediate portion provided between the edge portions,
A semiconductor memory device wherein the thickness of the middle portion is smaller than the thicknesses of the edge portions. In the second paragraph,
Each of the above additional support patterns includes edge portions adjacent to the support patterns and an intermediate portion provided between the edge portions,
A semiconductor memory device wherein the width of the middle portion is smaller than the widths of the edge portions. In the second paragraph,
A semiconductor memory device wherein the additional support patterns and the support patterns include silicon nitride (SiN), silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. In the first paragraph,
Each of the above line support patterns comprises a plurality of stacked line support patterns,
A semiconductor memory device wherein the plurality of stacked line support patterns are spaced apart from each other in the third direction. In the first paragraph,
A capacitor dielectric film conformally provided on the storage electrodes and the line support patterns; and
A semiconductor memory device further comprising a common electrode provided on the capacitor dielectric film. Forming a sacrificial film and a support film sequentially on a substrate;
Forming first trenches extending in a first direction within the sacrificial film and the support film to define preliminary support patterns and preliminary sacrificial patterns extending in the first direction;
Forming storage electrode lines within the above first trenches;
Patterning the storage electrode lines, the preliminary support patterns and the preliminary sacrificial patterns to form second trenches, storage electrodes, support patterns and sacrificial patterns extending in a second direction intersecting the first direction, the storage electrodes being arranged in the first and second directions to form rows and columns; and
Including forming line support patterns by selectively depositing additional support patterns on the above support patterns,
Each of the above line support patterns is arranged between the adjacent rows and includes the support patterns and the additional support patterns alternately arranged in the first direction,
A method for manufacturing a semiconductor memory device, wherein each of the above storage electrodes has a square shape in a planar view. In Article 8,
Selectively depositing the additional support patterns on the above support patterns:
Selectively depositing a first deposition-inhibiting layer on the exposed surfaces of the above sacrificial patterns;
Selectively depositing a second deposition-inhibiting layer on the exposed surfaces of the storage electrodes; and
Including selectively depositing the additional support patterns on the exposed surfaces of the support patterns,
A method for manufacturing a semiconductor memory device, wherein the deposition rate of the additional support patterns on the support patterns is greater than the deposition rate of the additional support patterns on the first and second deposition-suppressing layers. In Article 8,
Each of the above additional support patterns includes edge portions adjacent to the support patterns and an intermediate portion provided between the edge portions,
A method for manufacturing a semiconductor memory device, wherein the level of each of the lower surfaces of the above-described additional support patterns increases from the edge portion to the middle portion.

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