KR20240144675A - Display apparatus - Google Patents

Abstract

The present invention provides a display device having excellent durability, comprising: a substrate; a first organic insulating layer located on the substrate; a first conductive pattern located on the first organic insulating layer; a first inorganic insulating layer interposed between the first organic insulating layer and the first conductive pattern and patterned to have the same shape as the first conductive pattern; and a first transparent conductive layer located on the first conductive pattern and patterned to have the same shape as the first conductive pattern.

Description

Display apparatus {Display apparatus}

Embodiments of the present invention relate to a display device, and more particularly, to a display device having excellent durability.

Typically, display devices such as organic light-emitting display devices have thin film transistors arranged in each (sub)pixel to control the brightness, etc. of each (sub)pixel. These thin film transistors control the brightness, etc. of the corresponding (sub)pixel according to transmitted data signals, etc.

However, these conventional display devices had a problem in that they were highly likely to be damaged by external impact.

The present invention is intended to solve various problems including the above problems, and aims to provide a display device with excellent durability. However, these tasks are exemplary and the scope of the present invention is not limited thereby.

According to one aspect of the present invention, a display device is provided, comprising: a substrate; a first organic insulating layer positioned on the substrate; a first conductive pattern positioned on the first organic insulating layer; a first inorganic insulating layer interposed between the first organic insulating layer and the first conductive pattern and patterned to have the same shape as the first conductive pattern; and a first transparent conductive layer positioned on the first conductive pattern and patterned to have the same shape as the first conductive pattern.

The outer surface of the first transparent conductive layer and the outer surface of the first conductive pattern can form a continuous surface.

The outer surface of the first transparent conductive layer, the outer surface of the first conductive pattern, and the outer surface of the first inorganic insulating layer can form a continuous surface.

When viewed in a direction perpendicular to the substrate, the area of the first transparent conductive layer and the area of the first conductive pattern may be the same.

When viewed in a direction perpendicular to the substrate, the area of the first transparent conductive layer, the area of the first conductive pattern, and the area of the first inorganic insulating layer may be the same.

The above first transparent conductive layer may have a first hole that exposes a portion of the upper surface of the first conductive pattern.

A second organic insulating layer is further provided on the first organic insulating layer so as to cover the first transparent conductive layer, and the second organic insulating layer may have a second hole corresponding to the first hole.

When viewed in a direction perpendicular to the substrate, the second hole can overlap the first hole.

The area of the above first hole may be larger than the area of the above second hole.

The area of the first hole at the second interface between the first transparent conductive layer and the second organic insulating layer may be narrower than the area of the first hole at the imaginary plane between the first interface and the second interface between the first transparent conductive layer and the first conductive pattern.

The area of the first hole in the second interface may be equal to the area of the second hole in the second interface.

A second conductive pattern may be further provided, positioned on the upper portion of the second organic insulating layer, and contacting the upper surface of the first conductive pattern through the first hole and the second hole.

The above second challenge pattern can fill the first hole and the second hole.

A second inorganic insulating layer may be further provided between the second organic insulating layer and the second conductive pattern, the edge of which corresponds to the edge of the second conductive pattern.

The outer surface of the second challenge pattern and the outer surface of the second inorganic insulating layer can form a continuous surface.

When viewed in a direction perpendicular to the substrate, the area of the second conductive pattern and the area of the second inorganic insulating layer may be the same.

The above second inorganic insulating layer may have a third hole corresponding to the second hole.

The above second challenge pattern can contact the upper surface of the first challenge pattern through the first hole, the second hole, and the third hole.

A second transparent conductive layer may further be provided, positioned on the second conductive pattern and having an edge corresponding to an edge of the second conductive pattern.

The outer surface of the second transparent conductive layer and the outer surface of the second conductive pattern can form a continuous surface.

When viewed in a direction perpendicular to the substrate, the area of the second transparent conductive layer and the area of the second conductive pattern may be the same.

Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for practicing the invention.

According to one embodiment of the present invention as described above, a display device with excellent durability can be implemented. Of course, the scope of the present invention is not limited by these effects.

FIG. 1 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.
Figure 2 is an equivalent circuit diagram of one pixel included in the display device of Figure 1.
FIG. 3 is a layout diagram schematically showing the locations of transistors, capacitors, etc. in the pixels included in the display device of FIG. 1.
Figures 4 to 10 are schematic layout diagrams illustrating components such as transistors and capacitors of the display device illustrated in Figure 3, layer by layer.
FIG. 11 is a cross-sectional view schematically illustrating cross sections taken along lines I-I', II-II', and III-III' of the display device illustrated in FIG. 3.
Figure 12 is a cross-sectional view showing an enlarged view of part A of Figure 11.
Figures 13 to 17 are cross-sectional views schematically illustrating the manufacturing process of the part illustrated in Figure 12.
Figure 18 is a cross-sectional view showing an enlarged portion of part B of Figure 11.
Figures 19 to 22 are cross-sectional views schematically illustrating the manufacturing process of the part illustrated in Figure 18.

The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and the methods for achieving them will become clear with reference to the embodiments described in detail below together with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals and redundant descriptions thereof are omitted.

In the following examples, when various components such as layers, films, regions, and plates are said to be "on" other components, this includes not only cases where they are "directly on" other components, but also cases where other components are interposed between them. In addition, for convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to what is shown.

In the following examples, the x-axis, y-axis, and z-axis are not limited to three axes on an orthogonal coordinate system, and may be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

FIG. 1 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention. As illustrated in FIG. 1, the display device according to the present embodiment includes a display panel (10). The display device may be any device that includes a display panel (10). For example, the display device may be a variety of products such as a smartphone, a tablet, a laptop, a television, or a billboard.

The display panel (10) includes a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged in the display area (DA). When viewed from a direction approximately perpendicular to the display panel (10), the display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. FIG. 1 illustrates that the display area (DA) has an approximately rectangular shape with rounded corners.

The peripheral area (PA) may be arranged outside the display area (DA). A width (in the x-axis direction) of a part of the peripheral area (PA) may be narrower than the width (in the x-axis direction) of the display area (DA). Through this structure, at least a part of the peripheral area (PA) may be easily bent, as described below, if necessary.

Of course, since the display panel (10) includes a substrate (100, see FIG. 12), it can be said that the substrate (100) has a display area (DA) and a peripheral area (PA) as described above. Hereinafter, for convenience, the substrate (100) is described as having a display area (DA) and a peripheral area (PA).

The display panel (10) may also be said to have, if necessary, a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) located on the opposite side of the main region (MR) with the bending region (BR) as the center. In the bending region (BR), the display panel (10) is bent so that at least a portion of the sub-region (SR) overlaps the main region (MR) when viewed in the z-axis direction. Of course, the present invention is not limited to a bent display device, and may be applied to a non-bent display device. The sub-region (SR) may be a non-display region. By causing the display panel (10) to be bent in the bending region (BR), the non-display region may not be viewed when the display device is viewed from the front (in the -z direction), or even if it is viewed, the viewable area may be minimized.

A driving chip (20) or the like may be placed in the sub-area (BR) of the display panel (10). The driving chip (20) may include an integrated circuit that drives the display panel (10). This integrated circuit may be a data driving integrated circuit that generates a data signal, but the present invention is not limited thereto.

The driving chip (20) can be mounted in the sub-area (SR) of the display panel (10). The driving chip (20) is mounted on the same surface as the display surface of the display area (DA), but as the display panel (10) is bent in the bending area (BR) as described above, the driving chip (20) can be positioned on the back surface of the main area (MR).

A printed circuit board (30), etc., may be attached to the end of the sub-area (SR) of the display panel (10). This printed circuit board (30), etc., may be electrically connected to a driving chip (20), etc., through pads (not shown) on the board.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described as an example, but the display device of the present invention is not limited thereto. As another embodiment, the display device of the present invention may be an inorganic light emitting display device (Inorganic Light Emitting Display or Inorganic EL Display device) or a display device such as a quantum dot light emitting display device. For example, a light emitting layer of a display element included in the display device may include an organic material or an inorganic material. In addition, the display device may have a light emitting layer and a quantum dot layer positioned on a path of light emitted from the light emitting layer.

As described above, the display panel (10) includes a substrate (100). Various components included in the display panel (10) may be positioned on the substrate (100). The substrate (100) may include glass, metal, or polymer resin. As described above, when the display panel (10) is bent in the bending region (BR), the substrate (100) needs to have flexible or bendable characteristics. In this case, the substrate (100) may include a polymer resin such as, for example, polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, the substrate (100) may be modified in various ways, such as having a multilayer structure including two layers including such polymer resins and a barrier layer including an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) interposed between the layers.

A plurality of pixels are positioned in the display area (DA). Each pixel refers to a sub-pixel and may include a display element such as an organic light-emitting diode (OLED). The pixel may emit light of, for example, red, green, blue or white.

The pixel can be electrically connected to peripheral circuits arranged in the peripheral area (PA). A scan driving circuit, a light emission control driving circuit, a terminal, a driving power supply line, and an electrode power supply line can be arranged in the peripheral area (PA). The scan driving circuit can provide a scan signal to the pixel through a scan line. The light emission control driving circuit can provide a light emission control signal to the pixel through a light emission control line. The terminal arranged in the peripheral area (PA) of the substrate (100) can be exposed without being covered by an insulating layer and can be electrically connected to the printed circuit board (30). The terminal of the printed circuit board (30) can be electrically connected to the terminal of the display panel (10).

The printed circuit board (30) transmits a signal or power of a control unit (not shown) to the display panel (10). A control signal generated by the control unit can be transmitted to each of the driving circuits through the printed circuit board (30). In addition, the control unit can transmit a first power voltage (ELVDD) to a driving power supply line and provide a second power voltage (ELVSS) to an electrode power supply line. The first power voltage (ELVDD or driving voltage) is transmitted to each pixel through a driving power supply line (1730, see FIG. 11) connected to the driving power supply line, and the second power voltage (ELVSS or common voltage) can be transmitted to a counter electrode (230, see FIG. 12) of a pixel connected to the electrode power supply line. The electrode power supply line may have a loop shape with one side open, and may have a shape that partially surrounds the display area (DA).

Meanwhile, the control unit generates a data signal, and the generated data signal can be transmitted to the pixel through the driving chip (20) and the data line (1710, see FIG. 11).

For reference, "line" may mean "wiring." This also applies to the embodiments and variations thereof described below.

FIG. 2 is an equivalent circuit diagram of one pixel (P) included in the display device of FIG. 1. As illustrated in FIG. 2, one pixel (P) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) electrically connected thereto.

The pixel circuit (PC) may include a plurality of thin film transistors (T1 to T7) and a storage capacitor (Cst) as illustrated in FIG. 2. The plurality of thin film transistors (T1 to T7) and the storage capacitor (Cst) may be connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2), and a driving voltage supply line (PL). At least one of these lines, for example, the driving voltage supply line (PL), may be shared by neighboring pixels (P).

The plurality of thin film transistors (T1 to T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), and a second initialization transistor (T7).

An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode, and the pixel electrode of the OLED may be connected to a driving transistor (T1) via a light emission control transistor (T6) to receive a driving current, and the counter electrode may receive a second power supply voltage (ELVSS). The organic light-emitting diode (OLED) may generate light having a brightness corresponding to the driving current.

Some of the plurality of thin film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). For example, among the plurality of thin film transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). Alternatively, among the plurality of thin film transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS and the rest may be PMOS. Alternatively, all of the plurality of thin film transistors (T1 to T7) may be NMOS or all of them may be PMOS. The plurality of thin film transistors (T1 to T7) may include amorphous silicon or polysilicon. If necessary, the thin film transistor that is an NMOS may include an oxide semiconductor. In the following, for convenience, the compensation transistor (T3) and the first initialization transistor (T4) are NMOS (n-channel MOSFETs) including oxide semiconductors, and the rest are PMOS (p-channel MOSFETs).

The signal lines may include a first scan line (SL1) transmitting a first scan signal (Sn), a second scan line (SL2) transmitting a second scan signal (Sn'), a previous scan line (SLp) transmitting a previous scan signal (Sn-1) to a first initialization transistor (T4), a subsequent scan line (SLn) transmitting a subsequent scan signal (Sn+1) to a second initialization transistor (T7), an emission control line (EL) transmitting an emission control signal (En) to an operation control transistor (T5) and an emission control transistor (T6), and a data line (DL) intersecting the first scan line (SL1) and transmitting a data signal (Dm).

The driving voltage supply line (PL) transmits a driving voltage (ELVDD) to the driving transistor (T1), the first initialization voltage line (VL1) transmits a first initialization voltage (Vint1) that initializes the driving transistor (T1), and the second initialization voltage line (VL2) can transmit a second initialization voltage (Vint2) that initializes a pixel electrode of an organic light-emitting diode (OLED).

A driving gate electrode of a driving transistor (T1) is connected to a storage capacitor (Cst) via a second node (N2), one of a source region and a drain region of the driving transistor (T1) is connected to a driving voltage supply line (PL) via an operation control transistor (T5) via a first node (N1), and the other of the source region and the drain region of the driving transistor (T1) can be electrically connected to a pixel electrode of an organic light-emitting diode (OLED) via a light-emitting control transistor (T6) via a third node (N3). The driving transistor (T1) can receive a data signal (Dm) according to a switching operation of the switching transistor (T2) and supply a driving current to the organic light-emitting diode (OLED). That is, the driving transistor (T1) can control the amount of current flowing from the first node (N1) electrically connected to the driving voltage supply line (PL) to the organic light-emitting diode (OLED) in response to the voltage applied to the second node (N2) that changes by the data signal (Dm).

A switching gate electrode of a switching transistor (T2) is connected to a first scan line (SL1) that transmits a first scan signal (Sn), one of a source region and a drain region of the switching transistor (T2) is connected to a data line (DL), and the other of the source region and the drain region of the switching transistor (T2) is connected to a driving transistor (T1) through a first node (N1) and can be connected to a driving voltage supply line (PL) via an operation control transistor (T5). The switching transistor (T2) can transmit a data signal (Dm) from the data line (DL) to the first node (N1) in response to a voltage applied to the first scan line (SL1). That is, the switching transistor (T2) can be turned on according to the first scan signal (Sn) received through the first scan line (SL1) and perform a switching operation of transmitting the data signal (Dm) transmitted through the data line (DL) to the driving transistor (T1) through the first node (N1).

The compensation gate electrode of the compensation transistor (T3) is connected to the second scan line (SL2). Either the source region or the drain region of the compensation transistor (T3) can be connected to a pixel electrode of an organic light-emitting diode (OLED) via a third node (N3) and an emission control transistor (T6). The other of the source region or the drain region of the compensation transistor (T3) can be connected to a first capacitor electrode (CE1) of a storage capacitor (Cst) and a driving gate electrode of a driving transistor (T1) via a second node (N2). The compensation transistor (T3) can be turned on according to a second scan signal (Sn') received through the second scan line (SL2) to diode-connect the driving transistor (T1).

A first initialization gate electrode of a first initialization transistor (T4) may be connected to a previous scan line (SLp). One of a source region and a drain region of the first initialization transistor (T4) may be connected to a first initialization voltage line (VL1). The other of the source region and the drain region of the first initialization transistor (T4) may be connected to a first capacitor electrode (CE1) of a storage capacitor (Cst) and a driving gate electrode of a driving transistor (T1) through a second node (N2). The first initialization transistor (T4) may apply a first initialization voltage (Vint1) from the first initialization voltage line (VL1) to the second node (N2) in response to a voltage applied to the previous scan line (SLp). That is, the first initialization transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) to perform an initialization operation of transmitting the first initialization voltage (Vint1) to the driving gate electrode of the driving transistor (T1) to initialize the voltage of the driving gate electrode of the driving transistor (T1).

The operation control gate electrode of the operation control transistor (T5) is connected to the emission control line (EL), and one of the source region and the drain region of the operation control transistor (T5) is connected to the driving voltage supply line (PL), and the other can be connected to the driving transistor (T1) and the switching transistor (T2) through the first node (N1).

The light emission control gate electrode of the light emission control transistor (T6) is connected to the light emission control line (EL), one of the source region and the drain region of the light emission control transistor (T6) is connected to the driving transistor (T1) and the compensation transistor (T3) via the third node (N3), and the other of the source region and the drain region of the light emission control transistor (T6) can be electrically connected to the pixel electrode of the organic light emitting diode (OLED).

The motion control transistor (T5) and the emission control transistor (T6) are simultaneously turned on according to the emission control signal (En) received through the emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current flows to the organic light-emitting diode (OLED).

The second initialization gate electrode of the second initialization transistor (T7) is connected to the subsequent scan line (SLn), one of the source region and the drain region of the second initialization transistor (T7) is connected to the pixel electrode of the organic light-emitting diode (OLED), and the other of the source region and the drain region of the second initialization transistor (T7) is connected to the second initialization voltage line (VL2) so as to receive the second initialization voltage (Vint2). The second initialization transistor (T7) is turned on according to the scan signal (Sn+1) received through the subsequent scan line (SLn) to initialize the pixel electrode of the organic light-emitting diode (OLED). The subsequent scan line (SLn) may be identical to the first scan line (SL1). In this case, the scan line may transmit the same electrical signal with a time difference, and may function as the first scan line (SL1) or the next scan line (SLn). That is, the next scan line (SLn) may be the first scan line of a pixel adjacent to the pixel (P) illustrated in FIG. 2 and electrically connected to the data line (DL).

The second initialization transistor (T7) may be connected to the first scan line (SL1) as illustrated in Fig. 2. However, the present invention is not limited thereto, and the second initialization transistor (T7) may be connected to the emission control line (EL) and driven according to the emission control signal (En).

The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) of the storage capacitor (Cst) is connected to a driving gate electrode of a driving transistor (T1) through a second node (N2), and the second capacitor electrode (CE2) of the storage capacitor (Cst) is connected to a driving voltage supply line (PL). The storage capacitor (Cst) may store a charge corresponding to a difference between a driving gate electrode voltage of the driving transistor (T1) and a driving voltage (ELVDD).

The specific operation of each pixel (P) according to one embodiment is as follows.

During the initialization period, when the previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

During the data programming period, when the first scan signal (Sn) and the second scan signal (Sn') are supplied through the first scan line (SL1) and the second scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward-biased. Then, the compensation voltage (Dm+Vth, Vth is a (-) value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the driving gate electrode of the driving transistor (T1). A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied to both ends of the storage capacitor (Cst), and a charge corresponding to the voltage difference between the two ends is stored in the storage capacitor (Cst).

During the emission period, the operation control transistor (T5) and the emission control transistor (T6) are turned on by the emission control signal (En) supplied from the emission control line (EL). A driving current is generated according to the voltage difference between the voltage of the driving gate electrode of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current is supplied to the organic light-emitting diode (OLED) through the emission control transistor (T6).

As described above, some of the plurality of thin film transistors (T1 to T7) may include oxide semiconductors. For example, the compensation transistor (T3) and the first initialization transistor (T4) may include oxide semiconductors.

In the case of polysilicon, since it has high reliability, it can be controlled so that the intended current flows accurately. Therefore, in the case of the driving transistor (T1) that directly affects the brightness of the display device, a semiconductor layer made of polysilicon with high reliability is included, so that a high-resolution display device can be implemented. On the other hand, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. That is, in the case of the oxide semiconductor, even when driven at low frequency, the color change of the image due to the voltage drop is not large, so low-frequency driving is possible. Therefore, the compensation transistor (T3) and the first initialization transistor (T4) include oxide semiconductors, so that the occurrence of leakage current can be prevented and a display device with reduced power consumption can be implemented.

Meanwhile, such oxide semiconductors are sensitive to light, and thus, changes in current amount, etc. may occur due to light from the outside. Therefore, a metal layer may be positioned under the oxide semiconductor to absorb or reflect light from the outside. Accordingly, as illustrated in FIG. 2, each of the compensation transistor (T3) and the first initialization transistor (T4) including the oxide semiconductor may have gate electrodes positioned above and below the oxide semiconductor layer, respectively. That is, when viewed in a direction perpendicular to the upper surface of the substrate (100) (z-axis direction), the metal layer positioned under the oxide semiconductor may overlap with the oxide semiconductor.

FIG. 3 is a layout diagram schematically illustrating positions of thin film transistors (T1 to T7) and storage capacitors (Cst), etc., in pixels included in the display device of FIG. 1, FIGS. 4 to 10 are layout diagrams schematically illustrating, layer by layer, components such as thin film transistors (T1 to T7) and storage capacitors (Cst) of the display device illustrated in FIG. 3, and FIG. 11 is a cross-sectional diagram schematically illustrating sections taken along lines I-I', II-II', and III-III' of the display device illustrated in FIG. 3.

As illustrated in these drawings, the display device may include a first pixel (P1) and a second pixel (P2) adjacent to each other. The first pixel (P1) and the second pixel (P2) may be approximately symmetrical with respect to an imaginary line as illustrated in FIG. 3, etc. Of course, the present invention is not limited thereto, and the first pixel (P1) and the second pixel (P2) may not be symmetrical but may have the same configuration, or may have various different configurations.

The first pixel (P1) may include a first pixel circuit (PC1), and the second pixel (P2) may include a second pixel circuit (PC2). Hereinafter, for convenience of explanation, some of the conductive patterns will be described based on the first pixel circuit (PC1), but these conductive patterns may also be arranged approximately symmetrically in the second pixel circuit (PC2).

As sequentially illustrated in FIGS. 4 to 10, the first semiconductor layer (1100) of FIG. 4, the first gate layer (1200) of FIG. 5, the second gate layer (1300) of FIG. 6, the second semiconductor layer (1400) of FIG. 7, the third gate layer (1500) of FIG. 8, the first source/drain layer (1600) of FIG. 9, and the second source/drain layer (1700) illustrated in FIG. 10 are arranged in a direction from near the substrate (100) to away from the substrate (100).

And insulating layers may be interposed between these layers. Specifically, as illustrated in FIG. 11, a first buffer layer (111) is interposed between the substrate (100) and the first semiconductor layer (1100) of FIG. 4, a first gate insulating layer (113) is interposed between the first semiconductor layer (1100) of FIG. 4 and the first gate layer (1200) of FIG. 5, a second gate insulating layer (115) is interposed between the first gate layer (1200) of FIG. 5 and the second gate layer (1300) of FIG. 6, a second buffer layer (not illustrated) is interposed between the second gate layer (1300) of FIG. 6 and the second semiconductor layer (1400) of FIG. 7, and a third gate insulating layer (117) is interposed between the second semiconductor layer (1400) of FIG. 7 and the third gate layer (1500) of FIG. 8. A first source insulating layer (118) may be interposed between the third gate layer (1500) of FIG. 8 and the first source drain layer (1600) of FIG. 9, and a second source insulating layer (119) may be interposed between the first source drain layer (1600) of FIG. 9 and the second source drain layer (1700) of FIG. 10.

These first buffer layer (111), first gate insulating layer (113), second gate insulating layer (115), second buffer layer, third gate insulating layer (117), first source insulating layer (118), and second source insulating layer (119) may include inorganic insulating materials. For example, each of these layers may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and/or zinc oxide.

Of course, the display device may include other layers as well. Specifically, as illustrated in FIG. 11, a first interlayer insulating layer (121) is interposed between the first semiconductor layer (1100) and the first gate insulating layer (113) of FIG. 4, a second interlayer insulating layer (122) is interposed between the first gate layer (1200) and the second gate insulating layer (115) of FIG. 5, a third interlayer insulating layer (123) is interposed between the second gate layer (1300) and the second buffer layer of FIG. 6, a fourth interlayer insulating layer (124) is interposed between the second semiconductor layer (1400) and the third gate insulating layer (117) of FIG. 7, a fifth interlayer insulating layer (125) is interposed between the third gate layer (1500) and the first source insulating layer (118) of FIG. 8, and a fifth interlayer insulating layer (125) is interposed between the third gate layer (1500) and the first source insulating layer (118) of FIG. 9. A sixth interlayer insulating layer (126) may be interposed between the first source-drain layer (1600) and the second source-insulating layer (119). In addition, a planarization layer (128) may be positioned on the second source-drain layer (1700).

These first interlayer insulating layer (121), second interlayer insulating layer (122), third interlayer insulating layer (123), fourth interlayer insulating layer (124), fifth interlayer insulating layer (125), sixth interlayer insulating layer (126), and planarization layer (128) may include organic insulating materials. For example, each of these layers may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. The layer including these organic insulating materials may have a shape in which the upper surface is approximately flat.

Each of the insulating layers described above may have a single-layer structure or a multi-layer structure as needed. Of course, components of different layers may be electrically connected to each other through contact holes formed in these insulating layers.

A first buffer layer (111) as described above may be positioned on the substrate (100). The first buffer layer (111) can prevent metal atoms or impurities from diffusing from the substrate (100) toward the first semiconductor layer (1100) positioned thereon. In addition, the first buffer layer (111) can control the speed at which heat is provided during the crystallization process for forming the first semiconductor layer (1100), thereby allowing the first semiconductor layer (1100) to be uniformly crystallized.

A first semiconductor layer (1100) as illustrated in FIG. 4 may be disposed on a first buffer layer (111). The first semiconductor layer (1100) may include a silicon semiconductor. For example, the first semiconductor layer (1100) may include amorphous silicon or polysilicon. Specifically, the first semiconductor layer (1100) may include polysilicon crystallized at a low temperature. If necessary, ions may be implanted into at least a portion of the first semiconductor layer (1100).

The driving transistor (T1), the switching transistor (T2), the operation control transistor (T5), the light emission control transistor (T6), and the second initialization transistor (T7) may be PMOS as described above, in which case the thin film transistors are positioned along the first semiconductor layer (1100) as illustrated in FIG. 4. And the first semiconductor layer (1100) may have a shape extending overall in the first direction (+y direction).

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the first semiconductor layer (1100) corresponds to the shape of the first buffer layer (111), and the first semiconductor layer (1100) can overlap the first buffer layer (111). For example, an insulating layer is formed on the substrate (100) to correspond to the entire surface of the substrate (100), a semiconductor layer is formed on the insulating layer to correspond to the entire surface of the substrate (100), and then the insulating layer and the semiconductor layer are simultaneously patterned using a photoresist or the like to form the first buffer layer (111) and the first semiconductor layer (1100). Accordingly, as illustrated in FIG. 11, the side surface of the first semiconductor layer (1100) and the side surface of the first buffer layer (111) can form a continuous surface.

As described above, the first interlayer insulating layer (121) can cover the first semiconductor layer (1100). The first gate layer (1200) as illustrated in FIG. 5 can be positioned on the first interlayer insulating layer (121). Of course, the first gate insulating layer (113) can be interposed between the first gate layer (1200) and the first interlayer insulating layer (121) as described above. In FIG. 5, the first gate layer (1200) is illustrated together with the first semiconductor layer (1100) for convenience.

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the first gate layer (1200) corresponds to the shape of the first gate insulating layer (113), and the first gate layer (1200) can overlap the first gate insulating layer (113). As illustrated in FIG. 11, the side surface of the first gate layer (1200) and the side surface of the first gate insulating layer (113) can form a continuous surface. The patterning of the first gate layer (1200) and the first gate insulating layer (113) will be described later.

The first gate layer (1200) may include a first gate line (1210), a first gate electrode (1220), and a second gate line (1230).

The first gate line (1210) may extend in the second direction (+x direction). The first gate line (1210) may be the first scan line (SL1) of FIG. 2 or a subsequent scan line (SLn). That is, for the first pixel (P1) as illustrated in FIG. 5, the first gate line (1210) may correspond to the first scan line (SL1) of FIG. 2, and for a pixel positioned adjacent to the first pixel (P1) in the first direction (+y direction), the first gate line (1210) may correspond to a subsequent scan line (SLn) of FIG. 2. Accordingly, the first scan signal (Sn) and the subsequent scan signal (Sn+1) may be applied to the pixels through the first gate line (1210). The portions overlapping the first semiconductor layer (1100) of the first gate line (1210) may be the switching gate electrode of the switching transistor (T2) and the second initialization gate electrode of the second initialization transistor (T7).

The first gate electrode (1220) may have an isolated shape. The first gate electrode (1220) is a driving gate electrode of a driving transistor (T1). For reference, a portion of the first semiconductor layer (1100) overlapping the first gate electrode (1220) and a portion therearound may be referred to as a driving semiconductor layer.

The second gate line (1230) may extend in the second direction (+x direction). The second gate line (1230) may correspond to the light emission control line (EL) of FIG. 2. The portions of the second gate line (1230) overlapping with the first semiconductor layer (1100) may be the operation control gate electrode of the operation control transistor (T5) and the light emission control gate electrode of the light emission control transistor (T6). The light emission control signal (En) may be applied to the pixels through the second gate line (1230).

The first gate layer (1200) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate layer (1200) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This first gate layer (1200) may have a multilayer structure. For example, the first gate layer (1200) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Mo/Al, or a three-layer structure of Mo/Al/Mo, and a transparent conductive layer including indium tin oxide (ITO) or indium zinc oxide (IZO) positioned thereon. In FIG. 11, the first gate line (1210) is illustrated as having a conductive pattern (1210a) and a transparent conductive layer (1210b) positioned on the conductive pattern (1210a), and the second gate line (1230) is illustrated as including a conductive pattern (1230a) and a transparent conductive layer (1230b) positioned on the conductive pattern (1230a).

As described above, the second interlayer insulating layer (122) can cover the first gate layer (1200). The second gate layer (1300) as illustrated in FIG. 6 can be positioned on the second interlayer insulating layer (122). Of course, as described above, the second gate insulating layer (115) can be interposed between the second gate layer (1300) and the second interlayer insulating layer (122).

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the second gate layer (1300) corresponds to the shape of the second gate insulating layer (115), and the second gate layer (1300) can overlap the second gate insulating layer (115). As illustrated in FIG. 11, the side surface of the second gate layer (1300) and the side surface of the second gate insulating layer (115) can form a continuous surface. The patterning of the first gate layer (1200) and the first gate insulating layer (113) will be described later.

The second gate layer (1300) may include a third gate line (1310), a fourth gate line (1320), a capacitor upper electrode (1330), and a first initialization voltage line (1340) (i.e., the first initialization voltage line (VL1) of FIG. 2).

The third gate line (1310) may extend in the second direction (+x direction). The third gate line (1310) may correspond to the previous scan line (SLp) of FIG. 2. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the third gate line (1310) may be spaced apart from the first gate line (1210). The previous scan signal (Sn-1) may be applied to pixels through the third gate line (1310). A portion of the third gate line (1310) overlapping with the second semiconductor layer (1400) described below may be a first initialization lower gate electrode of the first initialization transistor (T4).

The fourth gate line (1320) may also extend in the second direction (+x direction). The fourth gate line (1320) may correspond to the second scan line (SL2) of FIG. 2. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the fourth gate line (1320) may be spaced apart from the first gate line (1210) and the third gate line (1310). The second scan signal (Sn') may be applied to pixels through the fourth gate line (1320). A portion of the fourth gate line (1320) overlapping with the second semiconductor layer (1400) described below may be a compensation lower gate electrode of the compensation transistor (T3).

The third gate line (1310) and the fourth gate line (1320) are positioned below the second semiconductor layer (1400) described later with reference to FIG. 7, and in addition to serving as gate electrodes, they can also serve as lower protective metals that protect portions of the second semiconductor layer (1400) that overlap with the third gate line (1310) and the fourth gate line (1320).

The capacitor upper electrode (1330) overlaps the first gate electrode (1220) and may extend in the second direction (+x direction). This capacitor upper electrode (1330) may form a storage capacitor (Cst) together with the first gate electrode (1220), corresponding to the second capacitor electrode (CE2) of FIG. 2. A driving voltage (ELVDD) may be applied to the capacitor upper electrode (1330). In addition, a hole penetrating the capacitor upper electrode (1330) may be formed in the capacitor upper electrode (1330), and at least a portion of the first gate electrode (1220) may overlap the hole.

The first initialization voltage line (1340), which is the first initialization voltage line (VL1) of FIG. 2, may extend in the second direction (+x direction). When viewed in the direction perpendicular to the substrate (100) (z-axis direction), the first initialization voltage line (1340) may be spaced apart from the third gate line (1310). The first initialization voltage (Vint1) may be applied to pixels through the first initialization voltage line (1340). The first initialization voltage line (1340) may at least partially overlap with the second semiconductor layer (1400) to be described later, and may transmit the first initialization voltage (Vint1) to the second semiconductor layer (1400). The first initialization voltage line (1340) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT1, 1680CNT2, and 1680CNT3) described later with reference to FIG. 9.

The second gate layer (1300) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second gate layer (1300) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This second gate layer (1300) may have a multilayer structure. For example, the second gate layer (1300) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Mo/Al, or a three-layer structure of Mo/Al/Mo, and a transparent conductive layer located thereon and including indium tin oxide (ITO) or indium zinc oxide (IZO). In FIG. 11, the third gate line (1310) is illustrated as including a conductive pattern (1310a) and a transparent conductive layer (1310b) positioned on the conductive pattern (1310a), the fourth gate line (1320) includes a conductive pattern (1320a) and a transparent conductive layer (1320b) positioned on the conductive pattern (1320a), the capacitor upper electrode (1330) includes a conductive pattern (1330a) and a transparent conductive layer (1330b) positioned on the conductive pattern (1330a), and the first initialization voltage line (1340) includes a conductive pattern (1340a) and a transparent conductive layer (1340b) positioned on the conductive pattern (1340a).

As described above, the third interlayer insulating layer (123) can cover the second gate layer (1300). The second semiconductor layer (1400) as illustrated in Fig. 7 can be positioned on the third interlayer insulating layer (123). Of course, as described above, a second buffer layer (not illustrated) can be interposed between the second semiconductor layer (1400) and the third interlayer insulating layer (123).

The second semiconductor layer (1400) may include an oxide semiconductor. For example, the second semiconductor layer (1400) may include a Zn oxide-based material, specifically, Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. Of course, since various modifications are possible, the second semiconductor layer (1400) may include an oxide semiconductor, such as IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), in which metals such as indium (In), gallium (Ga), and tin (Sn) are contained in ZnO.

The second semiconductor layer (1400) is arranged on a different layer from the first semiconductor layer (1100), and may not overlap with the first semiconductor layer (1100) when viewed in a direction perpendicular to the substrate (100) (z-axis direction).

Similar to the relationship between the first semiconductor layer (1100) and the first buffer layer (111), when viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the second semiconductor layer (1400) corresponds to the shape of the second buffer layer, and the second semiconductor layer (1400) can overlap the second buffer layer. For example, an insulating layer is formed on the third interlayer insulating layer (123) to correspond to the front surface of the substrate (100), a semiconductor layer is formed on the insulating layer to correspond to the front surface of the substrate (100), and then the insulating layer and the semiconductor layer are simultaneously patterned using a photoresist or the like to form the second buffer layer and the second semiconductor layer (1400). Accordingly, the side surface of the second semiconductor layer (1400) and the side surface of the second buffer layer can form a continuous surface.

As described above, the fourth interlayer insulating layer (124) can cover the second semiconductor layer (1400). The third gate layer (1500) as illustrated in FIG. 8 can be positioned on the fourth interlayer insulating layer (124). Of course, the third gate insulating layer (117) can be interposed between the third gate layer (1500) and the fourth interlayer insulating layer (124) as described above. In FIG. 8, the third gate layer (1500) is illustrated together with the second semiconductor layer (1400) for convenience.

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the third gate layer (1500) corresponds to the shape of the third gate insulating layer (117), and the third gate layer (1500) can overlap the third gate insulating layer (117). As illustrated in FIG. 11, the side surface of the third gate layer (1500) and the side surface of the third gate insulating layer (117) can form a continuous surface. The patterning of the third gate layer (1500) and the third gate insulating layer (117) will be described later.

The third gate layer (1500) may include a fifth gate line (1520), a sixth gate line (1530), and an intermediate electrode (1540).

The fifth gate line (1520) may extend in the second direction (+x direction) and may have an isolated shape. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the fifth gate line (1520) may overlap the third gate line (1310). The portion of the fifth gate line (1520) overlapping the second semiconductor layer (1400) may be a first initialization upper gate electrode of the first initialization transistor (T4). The portion of the second semiconductor layer (1400) overlapping the fifth gate line (1520) and the vicinity thereof may be referred to as a first initialization semiconductor layer. The fifth gate line (1520) may be electrically connected to the third gate line (1310). For example, the fifth gate line (1520) may be electrically connected to the third gate line (1310) through a contact hole (1520CNT) formed in an insulating layer between the fifth gate line (1520) and the third gate line (1310). Accordingly, the fifth gate line (1520) may correspond to the previous scan line (SLp) of FIG. 2 together with the third gate line (1310). The previous scan signal (Sn-1) may be applied to the pixels through the fifth gate line (1520) and/or the third gate line (1310).

The sixth gate line (1530) may extend in the second direction (+x direction) and may have an isolated shape. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the sixth gate line (1530) may overlap the fourth gate line (1320). The portion of the sixth gate line (1530) that overlaps the second semiconductor layer (1400) may be a compensation upper gate electrode of the compensation transistor (T3). The sixth gate line (1530) may be electrically connected to the fourth gate line (1320). For example, the sixth gate line (1530) may be electrically connected to the fourth gate line (1320) through a contact hole (1530CNT) formed in an insulating layer between the sixth gate line (1530) and the fourth gate line (1320). Accordingly, the sixth gate line (1530) may correspond to the second scan line (SL2) of FIG. 2 together with the fourth gate line (1320). The second scan signal (Sn') may be applied to the pixels through the sixth gate line (1530) and/or the fourth gate line (1320).

The third gate layer (1500) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the third gate layer (1500) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third gate layer (1500) may have a multilayer structure, for example, the third gate layer (1500) may have a single-layer structure of Al, a two-layer structure of Mo/Al, or a three-layer structure of Mo/Al/Mo.

As described above, the fifth interlayer insulating layer (125) can cover the third gate layer (1500). The first source-drain layer (1600) as illustrated in FIG. 9 can be positioned on the fifth interlayer insulating layer (125). Of course, the first source insulating layer (118) can be interposed between the first source-drain layer (1600) and the fifth interlayer insulating layer (125) as described above.

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the first source-drain layer (1600) corresponds to the shape of the first source insulating layer (118), and the first source-drain layer (1600) can overlap the first source insulating layer (118). As illustrated in FIG. 11, the side surface of the first source-drain layer (1600) and the side surface of the first source insulating layer (118) can form a continuous surface. The patterning of the first source-drain layer (1600) and the first source insulating layer (118) will be described later.

The first source-drain layer (1600) may include a first connection electrode (1620), a second connection electrode (1610), a second initialization voltage line (1630), a third connection electrode (1670), a fourth connection electrode (1640), a fifth connection electrode (1650), and a sixth connection electrode (1680).

The first connection electrode (1620) can be electrically connected to the first semiconductor layer (1100) through a contact hole (1620CNT). With reference to FIG. 10, a data signal (Dm) from a data line (1710) described below can be transmitted to the first semiconductor layer (1100) through the first connection electrode (1620) and applied to the switching transistor (T2).

The second initialization voltage line (1630) can be extended in the second direction (+x direction). The second initialization voltage line (1630), which corresponds to the second initialization voltage line (VL2) of FIG. 2, can apply the second initialization voltage (Vint2) to the pixels. The second initialization voltage line (1630) is electrically connected to the first semiconductor layer (1100) through the contact hole (1630CNT), so that the second initialization voltage (Vint2) can be transmitted to the first semiconductor layer (1100) and applied to the second initialization transistor (T7).

The second connection electrode (1610) is supplied with a driving voltage (ELVDD) from a driving power supply line (1730) described later with reference to FIG. 10. The second connection electrode (1610), which is electrically connected to the first semiconductor layer (1100) through a contact hole (1610CNT1), can supply the driving voltage (ELVDD) to the first semiconductor layer (1100), specifically, to the operation control transistor (T5). In addition, the second connection electrode (1610), which is electrically connected to the capacitor upper electrode (1330) (i.e., the second capacitor electrode (CE2) of FIG. 2) through a contact hole (1610CNT2), which can be referred to as an additional contact hole, can supply the driving voltage (ELVDD) to the capacitor upper electrode (1330). The second connecting electrode (1610) extends in the second direction (+x direction) and can be integral with the first pixel (P1) and the second pixel (P2).

The third connection electrode (1670) can be electrically connected to the first semiconductor layer (1100) through a contact hole (1670CNT). The third connection electrode (1670) can transmit a driving current or a second initialization voltage (Vint2) from the first semiconductor layer (1100) to an organic light-emitting diode (OLED).

The fourth connection electrode (1640) is electrically connected to the second semiconductor layer (1400) through a contact hole (1640CNT1) formed on one side. In addition, the fourth connection electrode (1640) is electrically connected to the first gate electrode (1220), which is a driving gate electrode, through a contact hole (1640CNT2) formed on the other side and passing through an opening (1330-OP) of the capacitor upper electrode (1330). Accordingly, the fourth connection electrode (1640) can electrically connect the first initialization semiconductor layer, which is a part of the second semiconductor layer (1400), to the driving gate electrode. The first initialization voltage (Vint1) can be transmitted to the first gate electrode (1220), which is a driving gate electrode, through the second semiconductor layer (1400) and the fourth connection electrode (1640).

The fifth connection electrode (1650) can electrically connect the second semiconductor layer (1400) and the first semiconductor layer (1100) through contact holes (1650CNT1, 1650CNT2) formed on one side and the other side. That is, the fifth connection electrode (1650) can electrically connect the compensation transistor (T3) and the driving transistor (T1).

The sixth connection electrode (1680) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT2 and 1680CNT3). In addition, the sixth connection electrode (1680) can be electrically connected to the first initialization voltage line (1340) of FIG. 6 through the contact hole (1680CNT1). Through this, the sixth connection electrode (1680) can transfer the first initialization voltage (Vint1) from the first initialization voltage line (1340) to the first initialization transistor (T4).

The first source drain layer (1600) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first source drain layer (1600) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This first source-drain layer (1600) may have a multilayer structure. For example, the first source-drain layer (1600) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Ti/Al, or a three-layer structure of Ti/Al/Ti, and a transparent conductive layer positioned thereon and containing indium tin oxide (ITO) or indium zinc oxide (IZO). In FIG. 11, a first connection electrode (1620) is illustrated as having a conductive pattern (1620a) and a transparent conductive layer (1620b) positioned on the conductive pattern (1620a), a second connection electrode (1610) includes a conductive pattern (1610a) and a transparent conductive layer (1610b) positioned on the conductive pattern (1610a), and a third connection electrode (1670) includes a conductive pattern (1670a) and a transparent conductive layer (1670b) positioned on the conductive pattern (1670a).

As described above, the sixth interlayer insulating layer (126) may cover the first source-drain layer (1600). The second source-drain layer (1700) as illustrated in FIG. 10 may be positioned on the sixth interlayer insulating layer (126). Of course, as described above, the second source insulating layer (119) may be interposed between the second source-drain layer (1700) and the sixth interlayer insulating layer (126).

When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the shape of the second source-drain layer (1700) corresponds to the shape of the second source insulating layer (119), and the second source-drain layer (1700) may overlap the second source insulating layer (119). In this case, as illustrated in FIG. 11, the side surface of the second source-drain layer (1700) and the side surface of the second source insulating layer (119) may form a continuous surface. The patterning of the second source-drain layer (1700) and the second source insulating layer (119) will be described later.

The second source drain layer (1700) may include a data line (1710), a driving power supply line (1730), and an upper connection electrode (1740).

The data line (1710) may extend in the first direction (+y direction). The data line (1710) may correspond to the data line (DL) of FIG. 2. The data line (1710) is electrically connected to the first connection electrode (1620) through the contact hole (1710CNT), so that the data signal (Dm) from the data line (1710) may be transmitted to the first semiconductor layer (1100) through the first connection electrode (1620) and applied to the switching transistor (T2).

The driving power supply line (1730) may extend approximately in the first direction (+y direction). The driving power supply line (1730) may correspond to the driving voltage supply line (PL) of FIG. 2. The driving power supply line (1730) may apply a driving voltage (ELVDD) to pixels. The driving power supply line (1730) may be electrically connected to the second connection electrode (1610) through the contact hole (1730CNT) so that the driving voltage (ELVDD) may be transmitted to the operation control transistor (T5) and the capacitor upper electrode (1330) as described above. The driving power supply line (1730) of the first pixel circuit (PC1) may be integral with the driving power supply line (1730) of the adjacent second pixel circuit (PC2).

The upper connection electrode (1740) is electrically connected to the third connection electrode (1670) through a contact hole (1740CNT1). In addition, the upper connection electrode (1740) is connected to the upper pixel electrode (211) through a contact hole (1740CNT2) formed in an insulating layer located thereon. Accordingly, the driving current or the second initialization voltage (Vint2) from the first semiconductor layer (1100) can be transmitted to the pixel electrode of the organic light-emitting diode (OLED) through the third connection electrode (1670) and the upper connection electrode (1740).

The second source-drain layer (1700) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second source-drain layer (1700) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). This second source/drain layer (1700) may have a multilayer structure. For example, the second source/drain layer (1700) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Ti/Al, or a three-layer structure of Ti/Al/Ti, and a transparent conductive layer including indium tin oxide (ITO) or indium zinc oxide (IZO) positioned thereon. In FIG. 11, the data line (1710) is illustrated as having a conductive pattern (1710a) and a transparent conductive layer (1710b) positioned on the conductive pattern (1710a), and the upper connection electrode (1740) includes a conductive pattern (1740a) and a transparent conductive layer (1740b) positioned on the conductive pattern (1740a).

The planarization layer (128) covers the second source-drain layer (1700) and may be positioned on the sixth interlayer insulating layer (126). The planarization layer (128) may include an organic insulating material as described above and may have a substantially flat upper surface. An organic light-emitting diode (OLED0) may be positioned on the planarization layer (128). In FIG. 11, the organic light-emitting diode (OLED) is illustrated as including a pixel electrode (211), an intermediate layer (221) including a light-emitting layer, and a counter electrode (330).

The pixel electrode (211) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (211) may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof, and a transparent or translucent electrode layer positioned on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ : indium oxide), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (211) may have a three-layer structure of ITO/Ag/ITO.

A pixel definition film (129) may be arranged on the flattening layer (128). The pixel definition film (129) may prevent arcs or the like from occurring at the edge of the pixel electrode by increasing the distance between the edge of the pixel electrode (211) and the counter electrode (230) above the pixel electrode (211). That is, the pixel definition film (129) may have a pixel opening (129OP) to expose the central portion of the pixel electrode (211). The pixel definition film (129) may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by a method such as spin coating.

At least a portion of the intermediate layer (221) including the light-emitting layer of the organic light-emitting diode (OLED) may be positioned within a pixel opening (129OP) formed by the pixel definition film (129). The light-emitting area of the organic light-emitting diode (OLED) may be defined by this pixel opening (129OP).

The intermediate layer (221) may include a light-emitting layer. The light-emitting layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular organic material or a high-molecular organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), or a quantum dot layer may be optionally further disposed below and above the light-emitting layer.

The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes (211). Layers other than the light-emitting layer included in the intermediate layer may be modified in various ways, such as being integrally formed across the pixel electrodes (211).

The counter electrode (230) may be a transparent electrode or a reflective electrode. For example, the counter electrode (230) may be a transparent or semitransparent electrode, and may include a metal thin film having a small work function, such as Li, Ca, LiF, Al, Ag, Mg, In, Yb, or a compound thereof. In addition, the counter electrode (230) may further include a TCO (transparent conductive oxide) film, such as ITO, IZO, ZnO, or In ₂ O ₃ , positioned on the metal thin film. The counter electrode (230) may be formed integrally over the entire display area (DA) and may be disposed on the intermediate layer and the pixel definition film (129).

When an external impact is applied to the display device, a crack may occur in the inorganic insulating layer including the inorganic insulating material inside the display device. Then, such a crack occurring in one pixel area may grow along the inorganic insulating layer including the inorganic insulating material inside the display device and extend to an adjacent pixel area. Accordingly, a defect may occur in a plurality of pixels.

However, in the case of the display device according to the present embodiment, the layers including the inorganic insulating material do not have a shape formed across the entire surface of the substrate (100), but are patterned to have a minimum area when viewed in a direction perpendicular to the substrate (z-axis direction). That is, the first buffer layer (111), the first gate insulating layer (113), the second gate insulating layer (115), the second buffer layer, the third gate insulating layer (117), the first source insulating layer (118), and the second source insulating layer (119) do not have a shape formed across the entire surface of the substrate (100), but are patterned to have the same shape as the conductive layer thereon. Therefore, in the case of the display device according to the present embodiment, even if an impact is applied from the outside, the probability of cracks occurring can be drastically reduced. In addition, even if a crack occurs in the insulating layer including the inorganic insulating material due to an impact from the outside, the probability of such cracks growing can be drastically reduced.

For reference, each of the first interlayer insulating layer (121), the second interlayer insulating layer (122), the third interlayer insulating layer (123), the fourth interlayer insulating layer (124), the fifth interlayer insulating layer (125), the sixth interlayer insulating layer (126), and the planarization layer (128) included in the display device according to the present embodiment may have a shape formed to correspond to the entire surface of the substrate (100). However, these layers include an organic insulating material. Therefore, even if an impact is applied from the outside of the display device, cracks do not occur in the insulating layer including the organic insulating material, or even if cracks do occur, the probability of such occurrence is extremely low.

FIG. 12 is a cross-sectional view showing an enlarged portion A of FIG. 11. As described above, the first gate layer (1200) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Mo/Al, or a three-layer structure of Mo/Al/Mo, and a transparent conductive layer including indium tin oxide (ITO) or indium zinc oxide (IZO) positioned thereon. FIG. 12 illustrates that the second gate line (1230) includes a conductive pattern (1230a) and a transparent conductive layer (1230b) positioned on the conductive pattern (1230a). A first gate insulating layer (113), which is an inorganic insulating layer patterned to correspond to the second gate line (1230), may be positioned below the second gate line (1230). The first gate insulating layer (113) and the second gate line (1230) may be positioned on the first interlayer insulating layer (121), which is an organic insulating layer.

Hereinafter, for convenience, the first interlayer insulating layer (121) is referred to as the first organic insulating layer (121), the first gate insulating layer (113) is referred to as the first inorganic insulating layer, the conductive pattern (1230a) is referred to as the first conductive pattern (1230a), and the transparent conductive layer (1230b) is referred to as the first transparent conductive layer (1230b). As described above and as illustrated in FIG. 12, the first inorganic insulating layer (113) may be patterned to have the same shape as the first conductive pattern (1230a), and the first transparent conductive layer (1230b) may also be patterned to have the same shape as the first conductive pattern (1230a). That is, the outer surface (1230bs) of the first transparent conductive layer (1230b) and the outer surface (1230as) of the first conductive pattern (1230a) form a continuous surface, and further, the outer surface (113s) of the first inorganic insulating layer (113) can also form a continuous surface with the outer surface (1230as) of the first conductive pattern (1230a).

Below, the manufacturing process of the part shown in Fig. 12 will be described with reference to Figs. 13 to 17.

First, as illustrated in FIG. 13, an inorganic insulating material layer (113') for a first inorganic insulating layer (113) is formed on a first organic insulating layer (121), a conductive layer (1230a') for a first conductive pattern (1230a) is formed on the inorganic insulating material layer (113'), and a transparent conductive layer (1230b') for a first transparent conductive layer (1230b) is formed on the conductive layer (1230a'). And as illustrated in FIG. 14, photoresist (PR) is formed on the transparent conductive layer (1230b') to correspond to the portion where the first conductive pattern (1230a) is to be formed, and as illustrated in FIG. 15, the portion of the transparent conductive layer (1230b') that is not covered by the photoresist (PR) and is exposed is removed through wet etching to form the first transparent conductive layer (1230b).

Then, as illustrated in FIG. 16, the portion exposed to the outside of the first transparent conductive layer (1230b) of the conductive layer (1230a') is removed through dry etching to form the first conductive pattern (1230a). The dry etching may be performed while the photoresist (PR) remains, as illustrated in FIG. 16, or may be performed while the photoresist (PR) is removed. During the dry etching process, the first transparent conductive layer (1230b) may function as a mask that shields the portion where the first conductive pattern (1230a) is to be formed. In this way, since the conductive layer (1230a') is patterned through dry etching in a situation where the first transparent conductive layer (1230b) functions as a mask, the outer surface (1230bs) of the first transparent conductive layer (1230b) and the outer surface (1230as) of the first conductive pattern (1230a) can form a continuous surface. Accordingly, when viewed in a direction perpendicular to the substrate (100) (z-axis direction), the area of the first transparent conductive layer (1230b) and the area of the first conductive pattern (1230a) can be substantially the same.

After forming the first conductive pattern (1230a), as illustrated in FIG. 17, the portion exposed to the outside of the first transparent conductive layer (1230b) of the inorganic insulating material layer (113') is removed through dry etching to form the first inorganic insulating layer (113). The dry etching may be performed in a state where the photoresist (PR) remains, as illustrated in FIG. 17, or may be performed in a state where the photoresist (PR) is removed. During the dry etching process, the first transparent conductive layer (1230b) may function as a mask that shields the portion where the first inorganic insulating layer (113) is to be formed. As described above, the first transparent conductive layer (1230b) includes indium tin oxide (ITO) or indium zinc oxide (IZO), and thus, the etching rate of the inorganic insulating layer during the dry etching process may be several tens of times, for example, 30 times, more than the etching rate of the first transparent conductive layer (1230b). Accordingly, the first transparent conductive layer (1230b) can function well as a mask that shields the portion where the first inorganic insulating layer (113) is to be formed.

In this way, in a situation where the first transparent conductive layer (1230b) functions as a mask, since the inorganic insulating material layer (113') is patterned through dry etching, the outer surface (1230bs) of the first transparent conductive layer (1230b), the outer surface (1230as) of the first conductive pattern (1230a), and the outer surface (113s) of the first inorganic insulating layer (113) can form a continuous surface. Accordingly, when viewed in a direction perpendicular to the substrate (100) (z-axis direction), the area of the first transparent conductive layer (1230b), the area of the first conductive pattern (1230a), and the area of the first inorganic insulating layer (113) can be substantially the same.

So far, the process of forming the second gate line (1230) and the first gate insulating layer (113) thereunder has been described with reference to FIGS. 13 to 17. The first gate line (1210), the first gate electrode (1220), and the second gate line (1230) included in the first gate layer (1200) can be formed simultaneously through the same process. In addition, the second gate layer (1300) and the second gate insulating layer (115) thereunder can also be formed through the same process as described above with reference to FIGS. 13 to 17, and the third gate layer (1500) and the third gate insulating layer (117) thereunder can also be formed through the same process as described above with reference to FIGS. 13 to 17.

For example, the fifth gate line (1520) may include a conductive pattern (1520a) and a transparent conductive layer (1520b) positioned on the conductive pattern (1520a), and the sixth gate line (1530) may include a conductive pattern (1530a) and a transparent conductive layer (1530b) positioned on the conductive pattern (1530a). The same applies to the intermediate electrode (1540). A third gate insulating layer (117), which is an inorganic insulating layer, may be positioned below each of the fifth gate line (1520), the sixth gate line (1530), and the intermediate electrode (1540). The relationship between the fifth gate line (1520) and the third gate insulating layer (117) below it, and the relationship between the sixth gate line (1530) and the third gate insulating layer (117) below it may be the same as the relationship between the second gate line (1230) and the first gate insulating layer (113) below it, as described above.

For reference, the process of forming the first semiconductor layer (1100) and the first buffer layer (111) thereunder may also be similar. That is, the inorganic insulating material layer for forming the first buffer layer (111) is formed so as to correspond to the front surface of the substrate (100), and the semiconductor material layer for forming the first semiconductor layer (1100) is formed on the inorganic insulating material layer so as to correspond to the front surface of the substrate (100), and then the semiconductor material layer and the inorganic insulating material layer are simultaneously and identically patterned using a photoresist or the like, so that the first buffer layer (111) and the first semiconductor layer (1100) having the same shape when viewed in a direction perpendicular to the substrate (z-axis direction) can be formed.

FIG. 18 is a cross-sectional view showing an enlarged portion B of FIG. 11. As described above, the second gate layer (1300) may have a conductive pattern having a single-layer structure of Al, a two-layer structure of Mo/Al, or a three-layer structure of Mo/Al/Mo, and a transparent conductive layer including indium tin oxide (ITO) or indium zinc oxide (IZO) positioned thereon. FIG. 18 illustrates that the capacitor upper electrode (1330) includes a conductive pattern (1330a) and a transparent conductive layer (1330b) positioned on the conductive pattern (1330a). A second gate insulating layer (115), which is an inorganic insulating layer patterned to correspond to the capacitor upper electrode (1330), may be positioned below the capacitor upper electrode (1330). The second gate insulating layer (115) and the capacitor upper electrode (1330) may be positioned on the second interlayer insulating layer (122), which is an organic insulating layer covering the first gate layer (1200).

Hereinafter, for convenience, the second interlayer insulating layer (122) is referred to as the first organic insulating layer (121), the second gate insulating layer (115) is referred to as the first inorganic insulating layer, the conductive pattern (1330a) is referred to as the first conductive pattern (1330a), and the transparent conductive layer (1330b) is referred to as the first transparent conductive layer (1330b). As described above and as illustrated in FIG. 18, the first inorganic insulating layer (115) may be patterned to have the same shape as the first conductive pattern (1330a), and the first transparent conductive layer (1330b) may also be patterned to have the same shape as the first conductive pattern (1330a). That is, the outer surface (1330bs) of the first transparent conductive layer (1330b) and the outer surface (1330as) of the first conductive pattern (1330a) form a continuous surface, and further, the outer surface (115s) of the first inorganic insulating layer (115) can also form a continuous surface with the outer surface (1330as) of the first conductive pattern (1330a).

A third interlayer insulating layer (123), which can be called a second organic insulating layer, is positioned on the first organic insulating layer (121), and this second organic insulating layer (123) covers the first transparent conductive layer (1330b). Of course, a fourth interlayer insulating layer (124), which can be called a third organic insulating layer, can be positioned on the second organic insulating layer (123), and a fifth interlayer insulating layer (125), which can be called a fourth organic insulating layer, can be positioned on the third organic insulating layer (124).

The first transparent conductive layer (1330b) may have a first hole to expose a part of the upper surface of the first conductive pattern (1330a). The second organic insulating layer (123) may have a second hole corresponding to the first hole. The third organic insulating layer (124) and the fourth organic insulating layer (125) may have extension holes corresponding to the second holes. When viewed in a direction perpendicular to the substrate (100), the first hole, the second hole, and the extension hole may overlap. Each of the first hole, the second hole, and the extension hole may be a part of a contact hole (1610CNT2), as illustrated in FIG. 11 and/or FIG. 18.

Below, the manufacturing process of the part shown in Fig. 18 is described with reference to Figs. 19 to 22.

First, with reference to FIGS. 13 to 17, through the same process as described above, a laminate of a first inorganic insulating layer (115), a first conductive pattern (1330a), and a first transparent conductive layer (1330b) sequentially laminated on a first organic insulating layer (122) can be formed as illustrated in FIG. 19. A photoresist (PR) may or may not be present on the first transparent conductive layer (1330b). If the photoresist (PR) is present, it can be removed, and then a second organic insulating layer (123) positioned on the first organic insulating layer (122) and a third organic insulating layer (124) positioned on the second organic insulating layer (123) can be formed to cover the laminate as illustrated in FIG. 20.

Of course, before forming the third organic insulating layer (124), a process of forming a second buffer layer and a second semiconductor layer (1400) on the second organic insulating layer (123) may be performed. And, through the same process as described above with reference to FIGS. 13 to 17, a third gate insulating layer (117) and a third gate layer (1500) sequentially laminated on the third organic insulating layer (124) (such as that illustrated in FIG. 11) may be formed. Of course, the third gate layer (1500) may be a laminate of a conductive pattern and a transparent conductive layer. And, a fourth organic insulating layer (125) positioned on the third organic insulating layer (124) may be formed to cover the laminate. In addition, in order to form a first source insulating layer (118), which can be called a second inorganic insulating layer, on the fourth organic insulating layer (125), an inorganic insulating material layer corresponding to the entire surface of the substrate (100) is formed.

Thereafter, as illustrated in Fig. 21, a contact hole (1610CNT2) is formed that penetrates the second organic insulating layer (123), the third organic insulating layer (124), the fourth organic insulating layer (125), and the inorganic insulating material layer, thereby exposing a portion of the upper surface of the first transparent conductive layer (1330b). The contact hole (1610CNT2) that penetrates the second organic insulating layer (123), the third organic insulating layer (124), and the like can be formed through dry etching using a photoresist. In the contact hole (1610CNT2), a portion of the second organic insulating layer (123) may be referred to as a second hole, portions of the third organic insulating layer (124) and the fourth organic insulating layer (125) may be referred to as extension holes, and portions of the inorganic insulating material layer may be referred to as a third hole in the contact hole (1610CNT2). In this sense, the first hole, the second hole, the extension hole, and the third hole may be referred to as corresponding to each other. The first hole, the second hole, the extension hole, and the third hole may be formed simultaneously in the same process.

Next, as illustrated in Fig. 22, a portion of the first transparent conductive layer (1330b) exposed by the contact hole (1610CNT2) may be removed through wet etching to form a first hole in the first transparent conductive layer (1330b). This first hole may be a part of the contact hole (1610CNT2). Thereafter, with reference to FIG. 13, similarly to the above-described method, a conductive layer and a transparent conductive layer are formed on the inorganic insulating material layer to form a first source-drain layer (1600), and with reference to FIGS. 14 to 17, similarly to the above-described method, the inorganic insulating material layer, the conductive layer, and the transparent conductive layer are patterned, so that a first source insulating layer (118), which can be referred to as a second inorganic insulating layer, as illustrated in FIG. 11, and a second connection electrode (1610), which includes a conductive pattern (1610a) positioned on the first source insulating layer (118) and a transparent conductive layer (1610b) positioned on the conductive pattern (1610a), can be formed. Accordingly, the edge of the first source insulating layer (118), which can be referred to as the second inorganic insulating layer, may correspond to the edge of the conductive pattern (1610a), which can be referred to as the second conductive pattern, and the edge of the transparent conductive layer (1610b), which can be referred to as the second transparent conductive layer, may correspond to the edge of the conductive pattern (1610a). Furthermore, the outer surface of the first source insulating layer (118), the outer surface of the conductive pattern (1610a), and the outer surface of the transparent conductive layer (1610b) form a continuous surface, and when viewed in a direction perpendicular to the substrate (100) (z-axis direction), the area of the transparent conductive layer (1610b), the area of the conductive pattern (1610a), and the area of the first source insulating layer (118) underneath may be the same.

In this process, when forming a conductive layer, the conductive layer can be made to fill the contact hole (1610CNT2) and contact the upper surface of the first conductive pattern (1330a). As a result, the conductive pattern (1610a) of the second connection electrode (1610), which can be called the second conductive pattern located on the upper surface of the second organic insulating layer (123) and the third organic insulating layer (124), can fill the contact hole (1610CNT2) and contact the upper surface of the first conductive pattern (1330a). The second challenge pattern can fill the first hole of the first transparent conductive layer (1330b), the second hole of the second organic insulating layer (123), the extension holes of the third organic insulating layer (124) and the fourth organic insulating layer (125), the third hole of the first source insulating layer (118), etc.

As described above with reference to FIG. 22, a portion of the first transparent conductive layer (1330b) exposed by the contact hole (1610CNT2) may be removed through wet etching to form a first hole in the first transparent conductive layer (1330b). Since the first hole is formed through wet etching in this manner, an undercut phenomenon occurs, and the area of the first hole formed in the first transparent conductive layer (1330b) may be larger than the area of the second hole in the second organic insulating layer (123). Specifically, when the interface between the first transparent conductive layer (1330b) and the first conductive pattern (1330a) is referred to as the first interface (1IF), and the interface between the first transparent conductive layer (1330b) and the second organic insulating layer (123) is referred to as the second interface (2IF), the area of the first hole of the first transparent conductive layer (1330b) at the second interface (2IF) may be narrower than the area of the first hole of the first transparent conductive layer (1330b) at the imaginary plane (xy plane) between the first interface (1IF) and the second interface (2IF). At this time, the area of the first hole of the first transparent conductive layer (1330b) at the second interface (2IF) may be equal to the area of the second hole of the second organic insulating layer (123) at the second interface (2IF).

The process of forming the capacitor upper electrode (1330) and the second gate insulating layer (115) thereunder has been described with reference to FIGS. 19 to 22 so far. The third gate line (1310), the fourth gate line (1320), the capacitor upper electrode (1330), and the first initialization voltage line (1340) included in the second gate layer (1300) can be formed simultaneously through the same process.

Meanwhile, when forming the second source-drain layer (1700), the same method as described above with reference to FIGS. 13 to 17 may be applied. Accordingly, as illustrated in FIG. 11, the data line (1710) may include a conductive pattern (1710a) and a transparent conductive layer (1710b) positioned on the conductive pattern (1710a), and the upper connection electrode (1740) may include a conductive pattern (1740a) and a transparent conductive layer (1740b) positioned on the conductive pattern (1740a). The driving power supply line (1730) is also the same. A second source insulating layer (119), which is an inorganic insulating layer, may be positioned below each of the data line (1710), the driving power supply line (1730), and the upper connection electrode (1740). The relationship between the data line (1710) and the second source insulating layer (119) below it, and the relationship between the upper connection electrode (1740) and the second source insulating layer (119) below it may be the same as the relationship between the second gate line (1230) and the first gate insulating layer (113) below it, as described above.

The conductive pattern (1710a) of the data line (1710) is connected to the conductive pattern (1620a) of the first connection electrode (1620) through the contact hole (1710CNT). With respect to this, the description of the conductive pattern (1610a) of the second connection electrode (1610) being connected to the conductive pattern (1330a) of the upper electrode of the capacitor (1330) through the contact hole (1610CNT2) with reference to FIGS. 18 to 22 can be applied as is (except that the number of interlayer insulating layers is different). That is, the description of the first hole, etc. formed in the transparent conductive layer (1330b) of the upper electrode of the capacitor (1330) can be applied as is to the hole, etc. formed in the transparent conductive layer (1620b) of the first connection electrode (1620).

The conductive pattern (1740a) of the upper connection electrode (1740) is connected to the conductive pattern (1670a) of the third connection electrode (1670) through the contact hole (1740CNT1). With respect to this, the description of the conductive pattern (1610a) of the second connection electrode (1610) being connected to the conductive pattern (1330a) of the upper electrode of the capacitor (1330) through the contact hole (1610CNT2) with reference to FIGS. 18 to 22 can be applied as is (except that the number of interlayer insulating layers is different). That is, the description of the first hole, etc. formed in the transparent conductive layer (1330b) of the upper electrode of the capacitor (1330) can be applied as is to the hole, etc. formed in the transparent conductive layer (1670b) of the third connection electrode (1670).

Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

100: substrate 111: buffer layer
113: First gate insulating layer 115: Second gate insulating layer
117: 3rd gate insulation 118: 1st source insulation layer
119: Second source insulation layer 121: First interlayer insulation layer
122: Second layer insulation layer 123: Third layer insulation layer
124: 4th interlayer insulation layer 125: 5th interlayer insulation layer
126: 6th interlayer insulation layer 128: Flattening layer
129: Pixel definition film 211: Pixel electrode
221: Middle layer 230: Counter electrode
1100: 1st semiconductor layer 1200: 1st gate layer
1300: 2nd gate layer 1400: 2nd semiconductor layer
1500: 3rd gate layer 1600: 1st source-drain layer
1700: 2nd source drain layer

Claims (21)

substrate;
A first organic insulating layer positioned on the above substrate;
A first conductive pattern positioned on the first organic insulating layer;
A first inorganic insulating layer interposed between the first organic insulating layer and the first conductive pattern and patterned to have the same shape as the first conductive pattern; and
A first transparent conductive layer positioned on the first conductive pattern and patterned to have the same shape as the first conductive pattern;
A display device having a . In the first paragraph,
A display device, wherein the outer surface of the first transparent conductive layer and the outer surface of the first conductive pattern form a continuous surface. In the first paragraph,
A display device, wherein the outer surface of the first transparent conductive layer, the outer surface of the first conductive pattern, and the outer surface of the first inorganic insulating layer form a continuous surface. In the first paragraph,
A display device, wherein, when viewed in a direction perpendicular to the substrate, the area of the first transparent conductive layer and the area of the first conductive pattern are the same. In the first paragraph,
A display device, wherein when viewed in a direction perpendicular to the substrate, the area of the first transparent conductive layer, the area of the first conductive pattern, and the area of the first inorganic insulating layer are the same. In the first paragraph,
A display device, wherein the first transparent conductive layer has a first hole that exposes a portion of the upper surface of the first conductive pattern. In Article 6,
A second organic insulating layer is further provided on the first organic insulating layer so as to cover the first transparent conductive layer.
A display device, wherein the second organic insulating layer has a second hole corresponding to the first hole. In Article 7,
A display device, wherein when viewed in a direction perpendicular to the substrate, the second hole overlaps the first hole. In Article 8,
A display device, wherein the area of the first hole is larger than the area of the second hole. In Article 8,
A display device, wherein the area of the first hole at the second interface between the first transparent conductive layer and the second organic insulating layer is narrower than the area of the first hole at an imaginary plane between the first interface and the second interface between the first transparent conductive layer and the first conductive pattern. In Article 10,
A display device, wherein the area of the first hole in the second interface is the same as the area of the second hole in the second interface. In Article 7,
A display device further comprising a second conductive pattern positioned on the second organic insulating layer and contacting the upper surface of the first conductive pattern through the first hole and the second hole. In Article 12,
A display device in which the second challenge pattern fills the first hole and the second hole. In Article 12,
A display device further comprising a second inorganic insulating layer interposed between the second organic insulating layer and the second conductive pattern, the edge of which corresponds to the edge of the second conductive pattern. In Article 14,
A display device, wherein the outer surface of the second challenge pattern and the outer surface of the second inorganic insulating layer form a continuous surface. In Article 14,
A display device, wherein when viewed in a direction perpendicular to the substrate, the area of the second conductive pattern and the area of the second inorganic insulating layer are the same. In Article 14,
A display device, wherein the second inorganic insulating layer has a third hole corresponding to the second hole. In Article 17,
A display device in which the second challenge pattern contacts the upper surface of the first challenge pattern through the first hole, the second hole, and the third hole. In Article 14,
A display device further comprising a second transparent conductive layer positioned on the second conductive pattern and having an edge corresponding to an edge of the second conductive pattern. In Article 19,
A display device, wherein the outer surface of the second transparent conductive layer and the outer surface of the second conductive pattern form a continuous surface. In Article 19,
A display device, wherein when viewed in a direction perpendicular to the substrate, the area of the second transparent conductive layer and the area of the second conductive pattern are the same.

Images