KR20240143686A - Integrated circuit devices and manufacturing methods for the same - Google Patents

Abstract

The technical idea of the present invention provides an integrated circuit device including a substrate having a plurality of active regions; a bit line extending horizontally on the substrate; a first direct contact connected to a first active region selected from the plurality of active regions; a second direct contact between the first direct contact and the bit line; an inner nitride film in contact with sidewalls of the first direct contact and the second direct contact; a second active region adjacent to the first active region among the plurality of active regions; an element isolation film interposed between the first active region and the second active region; and an outer oxide film in contact with the second active region at least on one side and interposed between the inner nitride film and the second active region, and a method for manufacturing the same.

Description

INTEGRATED CIRCUIT DEVICES AND MANUFACTURING METHODS FOR THE SAME

The technical idea of the present invention relates to an integrated circuit device and a method for manufacturing the same, and more particularly, to an integrated circuit device including a bit line and a method for manufacturing the same.

As the down-scaling of integrated circuit devices has been rapidly progressing recently, the spacing between each of the plurality of bit lines has become narrower, and accordingly, the separation distance between the plurality of bit lines and other conductive regions interposed between each of the plurality of bit lines has gradually decreased. Accordingly, when forming a bit line, in addition to the conductive region connected to the bit line, other conductive regions adjacent thereto may be etched, resulting in a defect in which the contact plug and the conductive region are not connected. In addition, due to the narrow separation distance between the bit line and the contact plug, a defect in which the contact plug adjacent to the bit line is electrically connected may occur. It is necessary to develop a technology to prevent the defect in which the contact plug and the conductive region are not connected, and to implement an integrated circuit device in which the plurality of bit lines can maintain a stable and reliable structure.

The technical problem to be achieved by the technical idea of the present invention is to provide an integrated circuit device which prevents a defect in which a contact plug and a conductive area are not connected even when the area of a device area is reduced due to downscaling of a semiconductor device, and in which a plurality of bit lines can maintain a stable and reliable structure.

In order to solve the above-described problem, the technical idea of the present invention provides an integrated circuit device including a substrate having a plurality of active regions; a bit line extending in a horizontal direction on the substrate; a first direct contact connected to a first active region selected from the plurality of active regions; a second direct contact between the first direct contact and the bit line; an inner nitride film in contact with sidewalls of the first direct contact and the second direct contact; a second active region adjacent to the first active region among the plurality of active regions; and an outer oxide film in contact with the second active region on at least one side and interposed between the inner nitride film and the second active region.

In order to solve the above-described problem, the technical idea of the present invention provides an integrated circuit device including a substrate having a plurality of active regions, a plurality of bit lines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction intersecting the first horizontal direction; a first direct contact connected to a first active region selected from the plurality of active regions; a second direct contact connected between the first direct contact and a first bit line selected from the plurality of bit lines; a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions and extending in a vertical direction on the substrate; and a spacer structure interposed between the first bit line and the contact plug, wherein the spacer structure includes an inner nitride film contacting a sidewall of the direct contact, and an outer oxide film overlapping the second active region in the vertical direction, contacting the second active region, and interposed between the inner nitride film and the second active region.

In order to solve the above-described problem, the technical idea of the present invention comprises the steps of: forming a plurality of word lines in a plurality of word line trenches extending in a first horizontal direction of a substrate including a plurality of active regions; forming a first direct contact hole by removing a portion of the substrate arranged between the plurality of word lines among the plurality of active regions, and exposing a first active region selected among the plurality of active regions and a second active region adjacent to the first active region through the first direct contact hole; forming an outer oxide film on the first active region and the second active region exposed through the first direct contact hole; removing the outer oxide film on the first active region so that the first direct contact hole and the first active region are connected; forming a first direct contact filling the first direct contact hole; And the present invention provides a method for manufacturing an integrated circuit device, including the steps of stacking a plurality of conductive layers and an insulating capping pattern on the first direct contact, and etching a portion of each of the plurality of conductive layers and the first direct contact using the insulating capping pattern as an etching mask to form a bit line connected to the first direct contact.

The integrated circuit device according to exemplary embodiments of the present invention can secure a sufficient distance between a direct contact and a contact plug, thereby preventing a defect in which the direct contact and the contact plug are electrically connected. In addition, since an oxide film is formed on an active area exposed by a direct contact hole through a selective oxidation process, the exposed active area can be prevented from being etched together during an etching process for forming a bit line, thereby preventing a defect in which the exposed active area and the contact plug are not connected. Accordingly, the reliability of the integrated circuit device can be improved.

FIG. 1 is a schematic planar layout for explaining the main components of a memory cell array area of an integrated circuit device according to embodiments of the technical idea of the present invention.
FIG. 2 is a cross-sectional view illustrating an integrated circuit device according to embodiments of the technical idea of the present invention.
FIGS. 3 to 5 are cross-sectional views illustrating integrated circuit elements according to other embodiments of the technical idea of the present invention.
FIGS. 6A to 6T are cross-sectional views illustrating a manufacturing method of an integrated circuit device according to embodiments of the technical idea of the present invention in accordance with the process sequence.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

FIG. 1 is a schematic planar layout for explaining the main components of a memory cell array area of an integrated circuit device according to embodiments of the technical idea of the present invention.

Referring to FIG. 1, the integrated circuit device (10) may include a plurality of active regions (ACTs). The plurality of active regions (ACTs) may be arranged in a diagonal direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction).

A plurality of word lines (WL) may extend in parallel to each other along a first horizontal direction (X direction) across a plurality of active regions (ACTs). A plurality of bit lines (BL) may extend in parallel to each other along a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) over the plurality of word lines (WLs). The plurality of bit lines (BLs) may be connected to the plurality of active regions (ACTs) via direct contacts (DCs).

A plurality of buried contacts (BC) may be formed between two adjacent bit lines (BL) among a plurality of bit lines (BL). In exemplary embodiments, the plurality of buried contacts (BC) may be arranged in a row along a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of conductive landing pads (LP) may be formed on the plurality of buried contacts (BC). The plurality of buried contacts (BC) and the plurality of conductive landing pads (LP) may serve to connect a lower electrode (not shown) of a capacitor formed on an upper portion of the plurality of bit lines (BL) to an active region (ACT). At least a portion of each of the plurality of conductive landing pads (LP) may vertically overlap the buried contact (BC).

Next, exemplary configurations of integrated circuit elements according to embodiments of the technical idea of the present invention will be described with reference to FIGS. 2 to 5. The integrated circuit elements illustrated in FIGS. 2 and 5 may each have the layout of the integrated circuit element (10) illustrated in FIG. 1.

FIG. 2 is a cross-sectional view for explaining an integrated circuit device (100) according to embodiments of the technical idea of the present invention. In FIG. 2, (a) is a cross-sectional view of some components of a portion corresponding to the A-A' line cross-section of FIG. 1, (b) is a cross-sectional view of some components of a portion corresponding to the B-B' line cross-section of FIG. 1, and (c) is an enlarged cross-sectional view of a portion corresponding to the dotted line area indicated as "AX" in (a).

Referring to FIG. 2, an integrated circuit device (100) includes a substrate (110) in which a plurality of active regions (ACTs) are defined by a device isolation film (112). A device isolation film (112) is formed within a device isolation trench (T1) formed in the substrate (110).

The substrate (110) may include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. In other exemplary embodiments, the substrate (110) may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In exemplary embodiments, the substrate (110) may include conductive regions, for example, doped wells, or doped structures. The device isolation film (112) may be formed of an oxide film, a nitride film, or a combination thereof.

A plurality of word line trenches (T2) extending in a first horizontal direction (X direction) are formed on the substrate (110), and a plurality of gate dielectric films (116), a plurality of word lines (118), and a buried insulating film (120) are formed within the plurality of word line trenches (T2). The plurality of word lines (118) may correspond to the plurality of word lines (WL) illustrated in FIG. 1.

The gate dielectric film (116) may be formed of at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an ONO (oxide/nitride/oxide) film, or a high-k dielectric film having a higher dielectric constant than the silicon oxide film. The high-k dielectric film may be formed of HfO2, Al2O3, HfAlO3, Ta2O3, TiO2, or a combination thereof. The plurality of word lines (118) may be formed of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The plurality of buried insulating films (120) may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

A buffer layer (122) is formed on the substrate (110). The buffer layer (122) may be formed to cover the upper surfaces of a plurality of active regions (ACTs), the upper surfaces of the device isolation films (112), and the upper surfaces of a plurality of buried insulating films (120). The buffer layer (122) may be formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film sequentially formed on the substrate (110), but is not limited thereto.

A plurality of bit lines (BL) extending in parallel to each other in a second horizontal direction (Y direction) are formed on a buffer layer (122). The plurality of bit lines (BL) are spaced apart from each other in a first horizontal direction (X direction). A direct contact (DC) is formed on a portion of each of the plurality of active regions (ACT). Each of the plurality of bit lines (BL) may be connected to an active region (ACT) through the direct contact (DC). The direct contact (DC) may include a first direct contact (DC1) connected to a selected active region (ACT) among the plurality of active regions (ACT) and a second direct contact (DC2) between the first direct contact (DC1) and the bit line (BL). Each of the first direct contact (DC1) and the second direct contact (DC2) may be made of Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. In exemplary embodiments, the first direct contact (DC1) or the second direct contact (DC2) may be formed of a doped polysilicon film.

The plurality of bit lines (BL) may each include a lower conductive layer (130), a middle conductive layer (132), and an upper conductive layer (134) sequentially formed on a substrate (110). The plurality of bit lines (BL) are each covered with an insulating capping pattern (136). The insulating capping pattern (136) may be disposed on the upper conductive layer (134) in the vertical direction (Z direction). The upper surface of the lower conductive layer (130) of the bit line (BL) and the upper surface of the second direct contact (DC2) may be disposed on the same plane. Although the plurality of bit lines (BL) are exemplified as having a triple conductive layer structure including the lower conductive layer (130), the middle conductive layer (132), and the upper conductive layer (134) in FIG. 2, the technical idea of the present invention is not limited thereto. For example, the plurality of bit lines (BL) may be formed as a single conductive layer, a dual conductive layer, or a multiple conductive layer stack structure including four or more conductive layers.

In exemplary embodiments, the lower conductive layer (130) may be formed of a doped polysilicon film. The middle conductive layer (132) and the upper conductive layer (134) may each be formed of a film including Ti, TiN, TiSiN, tungsten (W), tungsten nitride (WN), tungsten silicide (WSix), tungsten silicon nitride (WSixNy), ruthenium (Ru), or a combination thereof. For example, the middle conductive layer (132) may be formed of a TiN film and/or a TiSiN film, and the upper conductive layer (134) may be formed of a film including Ti, TiN, W, WN, WSixNy, Ru, or a combination thereof. The insulating capping pattern (136) may be formed of a silicon nitride film.

A plurality of contact plugs (150) may be arranged on the substrate (110). The plurality of contact plugs (150) may have a pillar shape extending in a vertical direction (Z direction) in a space between each of the plurality of bit lines (BL). The plurality of contact plugs (150) may each be in contact with an active region (ACT). A lower end of each of the plurality of contact plugs (150) may be arranged at a level lower than an upper surface of the substrate (110) so as to be buried within the substrate (110). The plurality of contact plugs (150) may be made of, but are not limited to, a semiconductor material doped with impurities, a metal, a conductive metal nitride, or a combination thereof.

In an integrated circuit device (100), one direct contact (DC) and a pair of contact plugs (150) facing each other with the one direct contact (DC) interposed therebetween may be respectively connected to different active regions (ACTs) among a plurality of active regions (ACTs). In one embodiment, when the direct contact (DC) is connected to a first active region (ACT) selected from a plurality of active regions (ACTs), a pair of contact plugs (150) facing each other with the direct contact (DC) interposed therebetween may be respectively connected to a second active region (ACT) and a third active region (ACT) adjacent to the first active region (ACT).

A plurality of contact plugs (150) may be arranged in a row along a second horizontal direction (Y direction) between a pair of bit lines (BL) selected from a plurality of bit lines (BL) and adjacent to each other. An insulating fence (149) may be arranged between each of the plurality of contact plugs (150) arranged in a row along the second horizontal direction (Y direction). The plurality of contact plugs (150) may be insulated from each other by the plurality of insulating fences (149). The plurality of insulating fences (149) may each have a pillar shape extending in a vertical direction (Z direction) on the substrate (110). In exemplary embodiments, the plurality of insulating fences (149) may be made of a silicon nitride film.

An integrated circuit device (100) may include a plurality of spacer structures (SP1) interposed between a plurality of bit lines (BL) and a plurality of contact plugs (150). One spacer structure (SP1) may be interposed between one bit line (BL) and a plurality of contact plugs (150) arranged in a row along a second horizontal direction (Y direction). Each of the plurality of spacer structures (SP1) may include an outer oxide film (131), an inner nitride film (140), an inner insulating spacer (142), a gapfill insulating pattern (144), and an outer insulating spacer (146).

The inner nitride film (140) may be in contact with the sidewall of the direct contact (DC) and the sidewall of the lower conductive layer (130) of the bit line (BL), respectively. The inner nitride film (140) may be spaced apart from the contact plug (150) with the outer insulating spacer (146) therebetween. The inner nitride film (140) may include a portion in contact with the contact plug (150).

In the vertical direction (Z direction), the inner nitride film (140) may extend along the sidewalls of the middle conductive layer (132) and the upper conductive layer (134) of the bit line (BL). In addition, the inner nitride film (140) may extend along the sidewalls of the middle conductive layer (132) and the upper conductive layer (134) over the direct contact (DC). The inner nitride film (140) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (144). The inner nitride film (140) may cover from the highest level of both sidewalls of the insulating capping pattern (136) over the bit line (BL) to the lowest level of both sidewalls of the lower conductive layer (130) of the bit line (BL) in the vertical direction (Z direction). In addition, the inner nitride film (140) can cover from the highest level of both sidewalls of the insulating capping pattern (136) above the direct contact (DC) in the vertical direction (Z direction) to the lowest level of both sidewalls of the second direct contact (DC2) of the direct contact (DC). The inner nitride film (140) can be made of a nitride film, and can be made of, for example, a silicon nitride film.

The inner insulating spacer (142) may be in contact with the inner nitride film (140). The bottom surface of the inner insulating spacer (142) may be surrounded by the inner nitride film (140). The inner insulating spacer (142) may extend along the vertical direction (Z direction) on the sidewall of the inner nitride film (140). The inner insulating spacer (142) may be interposed between the bit line (BL) and the outer insulating spacer (146). The inner insulating spacer (142) may be spaced apart from the bit line (BL) with the inner nitride film (140) interposed therebetween. The inner insulating spacer (142) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (244). The inner insulating spacer (142) may include a portion that comes into contact with the lower end of the contact plug (150). As an example, the inner insulating spacer (142) may be formed of an oxide film, for example, a silicon oxide film.

A gap-fill insulating pattern (144) may be interposed between a lower portion of a contact plug (150) and a direct contact (DC). A portion of the gap-fill insulating pattern (144) facing the first direct contact (DC1) may have a different thickness from a portion of the gap-fill insulating pattern (144) facing the second direct contact (DC2). In one embodiment, a portion of the gap-fill insulating pattern (144) facing the first direct contact (DC1) may be formed thicker than a portion of the gap-fill insulating pattern (144) facing the second direct contact (DC2). One sidewall of the gap-fill insulating pattern (144) may be covered by the lower portion of the contact plug (150). The other sidewall and bottom surface of the gap-fill insulating pattern (144) may be surrounded by an inner insulating spacer (142). The inner nitride film (140) may surround the lower portion of the inner insulating spacer (142) and the gapfill insulating pattern (144) and may contact the lower portion of the contact plug (150). In addition, the inner insulating spacer (142) may surround the lower portion of the gapfill insulating pattern (144) and may contact the lower portion of the contact plug (150).

The outer insulating spacer (146) may cover a sidewall of an adjacent contact plug (150). The outer insulating spacer (146) may cover the sidewall of the contact plug (150) over the gapfill insulating pattern (144). The outer insulating spacer (146) may be interposed between the contact plug (150) and the inner insulating spacer (142). The outer insulating spacer (146) may extend in a vertical direction (Z direction) along which a sidewall of an adjacent bit line (BL) extends. The outer insulating spacer (146) may be spaced apart from the bit line (BL) with the inner nitride film (140) and the inner insulating spacer (142) interposed therebetween. The inner insulating spacer (142) may be surrounded by the outer insulating spacer (146) and the inner nitride film (140). The outer insulating spacer (146) may be in contact with the lower end of the inner nitride film (140) with the inner insulating spacer (142) therebetween. In addition, the outer insulating spacer (146) may extend in a vertical direction (Z direction) in which a sidewall of the direct contact (DC) extends. The outer insulating spacer (146) may be spaced apart from the direct contact (DC) with the inner nitride film (140) and the inner insulating spacer (142) therebetween. A portion of the inner nitride film (140) that is in contact with the buffer layer (122) may be in contact with the sidewall of the outer insulating spacer (146). The gapfill insulating pattern (144) may include a portion interposed between the outer insulating spacer (146) and the inner insulating spacer (142). In exemplary embodiments, the outer insulating spacer (146) may be made of a silicon nitride film.

The outer oxide film (131) can be in contact with the adjacent active region (ACT) on at least one side. In one embodiment, a sidewall of the outer oxide film (131) can be in contact with the active region (ACT), and in another embodiment, although not shown, a sidewall and a bottom surface of the outer oxide film (131) can be in contact with the active region (ACT). The outer oxide film (131) can be in contact with the adjacent device isolation film (112). The outer oxide film (131) can be interposed between the active region (ACT) and the inner nitride film (140). As a result, the inner nitride film (140) can be spaced apart from the adjacent active region (ACT) with the outer oxide film (131) interposed therebetween. The outer oxide film (131) can be arranged to overlap a portion of the adjacent active region (ACT) in the vertical direction (Z). The outer oxide film (131) may be arranged to be in contact with the lower end of the contact plug (150). The outer oxide film (131) may overlap with the contact plug (150) in the vertical direction and include a portion facing the first direct contact (DC1).

The outer oxide film (131) may be formed of an oxide film, for example, a silicon oxide film. The outer oxide film (131) may be formed through a selective oxidation process for a direct contact hole (DCH). Through the selective oxidation process, a portion of the film exposed by the direct contact hole (DCH) may be replaced with the outer oxide film (131). As an example, a portion of the active region (ACT) exposed by the direct contact hole (DCH) may be replaced with the outer oxide film (131). The outer oxide film (131) in contact with the active region (ACT) may include the same element as the active region (ACT). In an example, when the active region (ACT) is formed of a doped polysilicon film, the outer oxide film (131) may be formed of a silicon oxide film.

For example, when a direct contact hole (DCH) exposes a part of the active region (ACT) but an outer oxide film (131) is not formed on the exposed part of the active region (ACT), when etching a part of each of the upper conductive layer (134), the middle conductive layer (132), the lower conductive layer (130), and the direct contact (DC) using the insulating capping pattern (136) as an etching mask, the exposed active region (ACT) can be etched through the direct contact hole (DCH). Accordingly, since the direct contact hole (DCH) extends toward the active region (ACT), the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144) formed within the direct contact hole (DCH) can be arranged to overlap a part of the active region (ACT). At this time, a defect may occur in which the contact plug (150) does not penetrate the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144), and thus the contact plug (150) is not connected to the active area (ACT).

According to the technical idea of the present invention, by means of an outer oxide film (131) formed through a selective oxidation process for a direct contact hole (DCH), an active region (ACT) exposed by the direct contact hole (DCH) is covered by the outer oxide film (131), so that when a portion of each of the upper conductive layer (134), the middle conductive layer (132), the lower conductive layer (130), and the direct contact (DC) is etched using an insulating capping pattern (136) as an etching mask, the active region (ACT) exposed through the direct contact hole (DCH) may not be etched. Accordingly, since the direct contact hole (which does not extend toward the active area (ACT) side) can penetrate the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144), a defect in which the contact plug (150) is not connected to the active area (ACT) can be prevented. In addition, the width of the conventional direct contact hole (DCH) in the first horizontal direction (X) has been limited so as not to expose the active area (ACT) due to a problem in which a defect in which the contact plug (150) is not connected to the active area (ACT) may occur, as described above. However, according to the technical idea of the present invention, even if the direct contact hole (DCH) partially exposes the active area (ACT), the contact plug (150) can be connected to the active area (ACT), so that the process margin of the first direct contact hole (DCH1) can be increased regardless of the location of the active area (ACT). can be secured. In addition, since the width of the direct contact hole (DCH) in the first horizontal direction (X) can be secured sufficiently, a separation distance between the direct contact (DC) and the contact plug (150) can be secured, so that a defect in electrical connection between the direct contact (DC) and the contact plug (150) can be prevented.

In exemplary embodiments, a portion of the inner insulating spacer (142) above the gapfill insulating pattern (144) may be formed with a different thickness from a portion of the inner insulating spacer (142) that is in contact with the gapfill insulating pattern (144). In one embodiment, the portion of the inner insulating spacer (142) above the gapfill insulating pattern (144) may be formed thicker than other portions of the inner insulating spacer (142). The portion of the inner insulating spacer (142) above the gapfill insulating pattern (144) may have a thickness that is approximately constant along the vertical direction (Z direction). In one embodiment, the portion of the inner insulating spacer (142) above the gapfill insulating pattern (144) may have a thickness of about 1 nanometer to about 3 nanometers in the first horizontal direction (X direction).

The inner nitride film (140), the inner insulating spacer (142), and the outer insulating spacer (146) may each extend parallel to the bit line (BL) along the second horizontal direction (Y direction).

A metal silicide film (172) and a plurality of conductive landing pads (LP) may be sequentially formed on each of the plurality of contact plugs (150). The plurality of conductive landing pads (LP) may be connected to the plurality of contact plugs (150) through the metal silicide film (172). The plurality of conductive landing pads (LP) may extend from a space between each of the plurality of insulating capping patterns (136) to the upper portion of each of the plurality of insulating capping patterns (136) so as to vertically overlap a portion of the plurality of bit lines (BL). Each of the plurality of conductive landing pads (LP) may include a conductive barrier film (174) and a conductive layer (176).

In exemplary embodiments, the metal silicide film (172) may be formed of, but is not limited to, cobalt silicide, nickel silicide, or manganese silicide. In exemplary embodiments, the metal silicide film (172) may be omitted. The conductive barrier film (174) may be formed of a Ti/TiN stacked structure. The conductive layer (176) may be formed of doped polysilicon, a metal, a metal silicide, a conductive metal nitride, or a combination thereof. For example, the conductive layer (176) may include tungsten (W). The plurality of conductive landing pads (LP) may have a plurality of island-like pattern shapes when viewed from a planar view. The plurality of conductive landing pads (LP) may be electrically insulated from each other by an insulating film (180) filling a space therebetween. FIG. 2 illustrates a metal silicide film (172) formed on each of the plurality of contact plugs (150). Although the triple conductive layer structure including a conductive barrier film (174) and a conductive layer (176) is exemplified, the technical idea of the present invention is not limited thereto. For example, only a single conductive layer may be placed on each of the plurality of contact plugs (150).

FIG. 3 is a cross-sectional view for explaining an integrated circuit device (200) according to other embodiments according to the technical idea of the present invention. FIG. 3 shows an enlarged view of some configurations of a portion corresponding to the dotted line area indicated by “AX” in (a) of FIG. 3 among the integrated circuit devices (200).

Referring to FIG. 3, the integrated circuit device (200) has substantially the same configuration as the integrated circuit device (100) illustrated in FIG. 2. However, the integrated circuit device (200) may include a plurality of spacer structures (SP2) instead of a plurality of spacer structures (SP1). The width of the plurality of spacer structures (SP2) in the first horizontal direction (X) may be smaller than the width of the plurality of spacer structures (SP1) in the first horizontal direction (X).

Each of the plurality of spacer structures (SP2) may include an inner nitride film (240), an inner insulating spacer (242), a gapfill insulating pattern (244), and an outer insulating spacer (246).

The inner nitride film (240) may contact a sidewall of the direct contact (DC) and a sidewall of the lower conductive layer (130) of the bit line (BL), respectively. The inner nitride film (240) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (244). The inner nitride film (240) may include a portion contacting a lower end of the contact plug (150). In the vertical direction (Z direction), the inner nitride film (240) may extend along the sidewalls of the middle conductive layer (132) and the upper conductive layer (134) of the bit line (BL). In addition, the inner nitride film (240) may extend along the sidewalls of the middle conductive layer (132) and the upper conductive layer (134) above the direct contact (DC). The inner nitride film (240) may be formed of a nitride film, for example, a silicon nitride film.

The inner insulating spacer (242) may be in contact with a sidewall of the inner nitride film (240). The bottom surface of the inner insulating spacer (242) may be surrounded by the inner nitride film (240). The inner insulating spacer (242) may extend along a vertical direction (Z direction) on the sidewall of the inner nitride film (240). The inner insulating spacer (242) may be interposed between the bit line (BL) and the outer insulating spacer (246). The inner insulating spacer (242) may be surrounded by the inner nitride film (240) covering the bit line (BL) and the outer insulating spacer (246). The inner insulating spacer (242) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (244). The inner insulating spacer (242) may include a portion that contacts the lower end of the contact plug (150).

A gapfill insulating pattern (244) may be interposed between a lower end of a contact plug (150) and a direct contact (DC). One sidewall of the gapfill insulating pattern may be covered by the lower end of the contact plug (150). The other sidewall and bottom surface of the gapfill insulating pattern (244) may be surrounded by an inner insulating spacer (242). In the first horizontal direction (X direction), the gapfill insulating pattern (244) may face the direct contact (DC) with the inner nitride film (240) and the inner insulating spacer (242) interposed therebetween.

The inner nitride film (240) may surround the lower portion of the inner insulating spacer (242) and the gapfill insulating pattern (244) and may contact the bottom surface of the contact plug (150). In addition, the inner insulating spacer (242) may surround the lower portion of the gapfill insulating pattern (244) and may contact the bottom surface of the contact plug (150).

The inner nitride film (240) may be in contact with the sidewalls of each of the middle conductive layer (132) and the upper conductive layer (134) of the bit line (BL) and the sidewall of the insulating capping pattern (136). The inner insulating spacer (242) may extend along the sidewall of the inner nitride film (240). A portion of the inner insulating spacer (242) above the gapfill insulating pattern (244) may be formed with a different thickness from the other portions of the inner insulating spacer (242). In one embodiment, the portion of the inner insulating spacer (242) above the gapfill insulating pattern (244) may be formed thicker than the other portions of the inner insulating spacer (242).

The outer insulating spacer (246) may cover a sidewall of an adjacent contact plug (150). The outer insulating spacer (246) may be interposed between the inner insulating spacer (242) and the contact plug (150). The outer insulating spacer (246) may be spaced apart from the bit line (BL) with the inner nitride film (240) and the inner insulating spacer (242) interposed therebetween. The outer insulating spacer (246) may be spaced apart from the direct contact (DC) with the inner nitride film (240) and the inner insulating spacer (242) interposed therebetween. A portion of the inner nitride film (240) that is in contact with the buffer layer (122) may be in contact with a sidewall of the outer insulating spacer (246). The inner insulating spacer (242) may be surrounded by an outer insulating spacer (246) and an inner nitride film (240). In exemplary embodiments, the outer insulating spacer (246) may be made of a silicon nitride film.

The outer oxide film (131) may cover a portion of a sidewall of an adjacent active region (ACT). The outer oxide film (131) may be disposed on one sidewall of a direct contact hole (DCH). The outer oxide film (131) may be surrounded by the active region (ACT) and the inner nitride film (240). The outer oxide film (131) may be disposed to overlap a portion of the adjacent active region (ACT). The outer oxide film (131) may be disposed to contact a lower end of the contact plug (150).

The direct contact hole (DCH) may include one sidewall in contact with the outer oxide film (131) and may include the other sidewall not in contact with the outer oxide film (131). The one sidewall of the direct contact hole may penetrate an adjacent active region (ACT). The other sidewall of the direct contact hole (DCH) may not penetrate the adjacent active region (ACT). For example, the other sidewall of the direct contact hole (DCH) may be arranged to be spaced apart from the adjacent active region.

The plurality of spacer structures (SP2) may include an inner nitride film (240), an inner insulating spacer (242), and a gapfill insulating pattern (244) spaced apart from adjacent active regions (ACTs) with an outer oxide film (131) therebetween. In addition, the plurality of spacer structures (SP2) may include an inner nitride film (240), an inner insulating spacer (242), and a gapfill insulating pattern (244) spaced apart from adjacent active regions (ACTs) with an element isolation film (112) therebetween. As an example, when a second active region (ACT) and a third active region (ACT) are defined that are spaced apart from a first active region (ACT) to which a first direct contact (DC1) is connected among the plurality of active regions (ACT), the outer oxide film (131) may be in contact with the second active region (ACT) and the inner nitride film (240) may be spaced apart from the second active region (ACT) with the outer oxide film (131) interposed therebetween and with the third active region (ACT) with the device isolation film (112) interposed therebetween. This is because the direct contact hole (DCH) is formed to be biased to one side during the etching of the direct contact hole (DCH). For example, this may be the case where, among a plurality of active regions (ACTs) adjacent to a sidewall of a direct contact hole (DCH), the direct contact hole (DCH) exposes only one active region (ACT) and does not expose the other active region (ACT).

The outer oxide film (131) may be formed of an oxide film, and may be formed of, for example, a silicon oxide film. The outer oxide film (131) may be formed through a selective oxidation process for the direct contact hole (DCH). Through the selective oxidation process, a portion of the film exposed by the direct contact hole (DCH) may be replaced with the outer oxide film (131). As an example, a portion of the active region (ACT) exposed by the direct contact hole (DCH) may be replaced with the outer oxide film (131). For example, when the direct contact hole (DCH) exposes a portion of the active region (ACT) and the outer oxide film (131) is not formed on a portion of the active region (ACT) exposed by the direct contact hole (DCH), the exposed active region (ACT) may be etched during a subsequent etching process. Accordingly, since the direct contact hole (DCH) is extended toward the active region (ACT) due to the subsequent etching process, the inner nitride film (240), the inner insulating spacer (242), and the gapfill insulating pattern (244) may be arranged to overlap a part of the active region (ACT). At this time, the contact plug (150) may not penetrate the inner nitride film (240), the inner insulating spacer (242), and the gapfill insulating pattern (244), and thus a defect may occur in which the contact plug (150) is not connected to the active region (ACT). According to the technical idea of the present invention, since the active region (ACT) exposed by the direct contact hole (DCH) is covered by the outer oxide film (131), the exposed active region (ACT) may not be etched during the subsequent etching process. Accordingly, since the direct contact hole (DCH) does not extend toward the active area (ACT) due to the subsequent etching process, the contact plug (150) can be connected to the active area (ACT) by penetrating the inner insulating spacer (242) and the gapfill insulating pattern (244). Accordingly, a defect in which the contact plug (150) is not connected to the active area (ACT), which may occur when the direct contact hole (DCH) exposes a part of the active area (ACT), can be prevented.

More detailed configurations of the inner nitride film (240), the inner insulating spacer (242), the gapfill insulating pattern (244), and the outer insulating spacer (246) are substantially the same as those described with respect to the inner nitride film (140), the inner insulating spacer (142), the gapfill insulating pattern (144), and the outer insulating spacer (146) with reference to FIG. 2.

FIG. 4 is a cross-sectional view for explaining an integrated circuit element (300) according to other embodiments according to the technical idea of the present invention. FIG. 4 shows an enlarged view of some configurations of a portion corresponding to the dotted line area indicated by “AX” in (a) of FIG. 4 among the integrated circuit elements (300).

Referring to FIG. 4, the integrated circuit device (300) has substantially the same configuration as the integrated circuit device (100) illustrated in FIG. 2. However, the integrated circuit device (200) may include a plurality of spacer structures (SP1A) instead of a plurality of spacer structures (SP1). Hereinafter, descriptions of overlapping configurations between the integrated circuit device (300) and the integrated circuit device (100) illustrated in FIG. 2 will be simplified or omitted, and configurations that are different between the integrated circuit device (300) and the integrated circuit device (100) will be specifically described.

Each of the plurality of spacer structures (SP1A) may include an outer oxide film (131), an inner nitride film (140), a first inner insulating spacer (142A), a second inner insulating spacer (142B), a gapfill insulating pattern (144), and an outer insulating spacer (146).

The inner insulating spacers (142A, 142B) may extend along the vertical direction (Z direction) on the sidewall of the inner nitride film (140). The inner insulating spacers (142A, 142B) may be spaced apart from the bit line (BL) with the inner nitride film (140) therebetween. The inner insulating spacers (142A, 142B) may include a first inner insulating spacer (142A) interposed between the gapfill insulating pattern and the first direct contact, and a second inner insulating spacer (142B) interposed between the outer insulating spacer and the second direct contact. A bottom surface of the first inner insulating spacer (142A) may be surrounded by the inner nitride film (140). The first inner insulating spacer (142A) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (244). The first inner insulating spacer (142A) may include a portion contacting the lower end of the contact plug (150). The second inner insulating spacer (142B) may be interposed between the bit line (BL) and the outer insulating spacer (146). The first inner insulating spacer (142A) may be formed of a silicon oxide film, and the second inner insulating spacer (142B) may be formed of a silicon oxide film, an air spacer, or a combination thereof.

FIG. 5 is a cross-sectional view for explaining an integrated circuit device (400) according to other embodiments according to the technical idea of the present invention. FIG. 5 shows an enlarged view of some configurations of a portion corresponding to the dotted line area indicated by “AX” in (a) of FIG. 5 among the integrated circuit devices (400).

Referring to FIG. 5, the integrated circuit device (400) has substantially the same configuration as the integrated circuit device (200) illustrated in FIG. 3. However, the integrated circuit device (400) may include a plurality of spacer structures (SP2A) instead of a plurality of spacer structures (SP2). Hereinafter, descriptions of overlapping configurations between the integrated circuit device (400) and the integrated circuit device (200) illustrated in FIG. 3 will be simplified or omitted, and configurations that are different between the integrated circuit device (400) and the integrated circuit device (200) will be specifically described.

The plurality of spacer structures (SP2A) may include an inner nitride film (240), a first inner insulating spacer (242A), a second inner insulating spacer (242B), a gapfill insulating pattern (244), and an outer insulating spacer (246).

The inner insulating spacers (242A, 242B) may extend along the vertical direction (Z direction) on the sidewall of the inner nitride film (240). The inner insulating spacers (242A, 242B) may be spaced apart from the bit line (BL) with the inner nitride film (240) therebetween. The inner insulating spacers (242A, 242B) may include a first inner insulating spacer (242A) interposed between the gapfill insulating pattern and the first direct contact, and a second inner insulating spacer (242B) interposed between the outer insulating spacer and the second direct contact. A bottom surface of the first inner insulating spacer (242A) may be surrounded by the inner nitride film (240). The first inner insulating spacer (242A) may include a portion interposed between the direct contact (DC) and the gapfill insulating pattern (244). The first inner insulating spacer (242A) may include a portion contacting a lower end of the contact plug (250). The second inner insulating spacer (242B) may be interposed between the bit line (BL) and the outer insulating spacer (246). The first inner insulating spacer (242A) may be formed of a silicon oxide film, and the second inner insulating spacer (242B) may be formed of a silicon oxide film, an air spacer, or a combination thereof.

FIGS. 6A to 6T are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to embodiments of the technical idea of the present invention according to a process sequence. In FIGS. 6A to 6T, (a) is a cross-sectional view of some components according to a process sequence of a portion corresponding to a cross-section taken along line A - A' of FIG. 1, and (b) is a cross-sectional view of some components according to a process sequence of a portion corresponding to a cross-section taken along line B - B' of FIG. 1. A method for manufacturing an integrated circuit device (100) illustrated in FIG. 2 will be described with reference to FIGS. 6A to 6T.

Referring to FIG. 6a, a trench (T1) for device isolation is formed on a substrate (110), and a device isolation film (112) is formed within the trench (T1) for device isolation. A plurality of active regions (ACTs) can be defined on the substrate (110) by the device isolation film (112).

A plurality of word line trenches (T2) can be formed in the substrate (110). The plurality of word line trenches (T2) can extend in parallel to each other in the first horizontal direction (X direction) and have a line shape crossing the active area (ACT). In order to form a plurality of word line trenches (T2) having a step formed on the bottom surface, the device isolation film (112) and the substrate (110) can be etched by separate etching processes so that the etching depth of the device isolation film (112) and the etching depth of the substrate (110) are different from each other. After cleaning the resultant product in which the plurality of word line trenches (T2) are formed, a gate dielectric film (116), a word line (118), and a buried insulating film (120) can be sequentially formed inside each of the plurality of word line trenches (T2). Before or after forming the plurality of word lines (118), an ion implantation process may be performed to form a plurality of source/drain regions on top of the plurality of active regions (ACTs).

A buffer layer (122) can be formed on a substrate (110). The buffer layer (122) can be formed to cover the upper surfaces of a plurality of active regions (ACTs), the upper surfaces of the device isolation films (112), and the upper surfaces of a plurality of buried insulating films (120). The buffer layer (122) can be formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film sequentially formed on the substrate (110), but is not limited thereto.

Referring to Fig. 6b, a lower conductive layer (130) is formed on the buffer layer (122). The lower conductive layer (130) may be formed of a doped polysilicon film.

Referring to FIG. 6c, after forming a mask pattern (MP1) on a lower conductive layer (130), the lower conductive layer (130) exposed through the opening (MH) of the mask pattern (MP1), and a portion of each of the buffer layer (122), the substrate (110), and the device isolation film (112) thereunder are etched to form a first direct contact hole (DCH1) exposing an active region (ACT) of the substrate (110). At this time, a portion of the active region (ACT) may also be exposed on a sidewall of the first direct contact hole (DCH1). The mask pattern (MP1) may be formed of, but is not limited to, an oxide film, a nitride film, or a combination thereof.

Referring to FIG. 6d, a selective oxidation process is performed in the first direct contact hole (DCH1) to form an outer oxide film (131). The outer oxide film (131) may be formed on a sidewall of the lower conductive layer (130) and the active region (ACT) exposed by the first direct contact hole (DCH1). The outer oxide film (131) has etching selectivity with respect to the lower conductive layer (130) and the active region (ACT). As an example, the selective oxidation process may be an isotropic oxidation process that does not have a specific oxidation direction. During the isotropic oxidation process, a portion of the lower conductive layer (130) and the active region (ACT) exposed by the first direct contact hole (DCH1) may be oxidized to form the outer oxide film (131). Accordingly, the outer oxide film (131) in contact with the lower conductive layer (130) can include the same element as the lower conductive layer (130). In one embodiment, when the lower conductive layer (130) is formed of a doped polysilicon film, the outer oxide film (131) can be formed of a silicon oxide film. In addition, the outer oxide film (131) in contact with the active region (ACT) can include the same element as the active region (ACT). In one embodiment, when the active region (ACT) is formed of a doped polysilicon film, the outer oxide film (131) can be formed of a silicon oxide film. The outer oxide film (131) is formed thinly so that a sufficient thickness of the lower conductive layer (130) and the active region (ACT) can remain.

Referring to FIG. 6e, a sacrificial film (SF) is formed within the first direct contact hole (DCH1). Specifically, the sacrificial film (SF) may be formed to cover the outer oxide film (131) along the inner wall of the first direct contact hole (DCH1).

Referring to FIG. 6f, in the resultant result in which the sacrificial film (SF) of FIG. 6e is formed, a portion of the outer oxide film (131) and the sacrificial film (SF) that overlap with the bottom surface of the first direct contact hole (DCH1) in the vertical direction (Z) can be etched so that the active region (ACT) can be exposed through the bottom surface of the first direct contact hole (DCH1). As a result, the sacrificial film (SF) can remain on the sidewall of the first direct contact hole (DCH1).

Referring to FIG. 6g, a first direct contact (DC1) may be formed within the first direct contact hole (DCH1). In order to form the first direct contact (DC1), a doped polysilicon film having a thickness sufficient to fill the first direct contact hole (DCH1) may be formed within the first direct contact hole (DCH1) and on top of the lower conductive layer (130), and an unnecessary portion of the doped polysilicon film may be removed so that the doped polysilicon film remains only within the first direct contact hole (DCH1).

Referring to FIG. 6h, a second direct contact hole (DCH2) may be formed by etching a portion of each of the lower conductive layer (130), the buffer layer (122) thereunder, the first direct contact (DC1), the sacrificial film (SF), and the outer oxide film (131) from the resultant structure of FIG. 6g. The second direct contact hole (DCH2) may have a sufficient width in the first horizontal direction (X) and a sufficient length in the vertical direction (Z) so that the outer oxide film (131) formed on the sidewall of the lower conductive layer (130) may be removed. The sidewall of the lower conductive layer (130) may be exposed through the second direct contact hole (DCH).

Referring to FIG. 6i, a second direct contact (DC2) is formed within the second direct contact hole (DCH2). In order to form the second direct contact (DC2), a doped polysilicon film having a thickness sufficient to fill the second direct contact hole (DCH2) is formed within the second direct contact hole (DCH2) and on top of the lower conductive layer (130), and an unnecessary portion of the doped polysilicon film can be removed so that the doped polysilicon film remains only within the second direct contact hole (DCH2).

Referring to FIGS. 6j and 6k, a portion of the second direct contact (DC2) overlapping the mask pattern (MP1) can be removed, and the mask pattern (MP1) can be removed.

Referring to FIG. 6l, an intermediate conductive layer (132), an upper conductive layer (134), and a plurality of insulating capping patterns (136) are sequentially formed on a lower conductive layer (130) and a direct contact (DC). Each of the plurality of insulating capping patterns (136) may be formed as a line pattern that extends long along the second horizontal direction (Y direction).

Referring to FIG. 6m, a portion of each of the upper conductive layer (134), the middle conductive layer (132), the lower conductive layer (130), and the direct contact (DC) is etched using the insulating capping pattern (136) as an etching mask to form a plurality of bit lines (BL) on the substrate (110). The plurality of bit lines (BL) may be formed of the remaining portions of each of the lower conductive layer (130), the middle conductive layer (132), and the upper conductive layer (134). After the plurality of bit lines (BL) are formed, a portion of the first direct contact hole (DCH1) may be re-exposed around the first direct contact (DC1), and a portion of the second direct contact hole (DCH2) may be re-exposed around the second direct contact (DC2). A line space (LS) extending along a second horizontal direction (Y direction) may be defined between each of a plurality of bit line structures, each of which includes a bit line (BL) and an insulating capping pattern (136).

Referring to FIG. 6n, an inner nitride film (140) is formed to conformally cover the exposed surface in the result of FIG. 6m. The inner nitride film (140) may be formed to contact each of the buffer layer (122), the lower conductive layer (130), the middle conductive layer (132), the upper conductive layer (134), the plurality of insulating capping patterns (136), the first direct contact (DC1) and the second direct contact (DC2).

In order to form the inner nitride film (140), a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process may be used. The inner nitride film (140) may be formed to have a substantially constant thickness along the vertical direction (Z direction) on the sidewall of the bit line (BL) and the sidewall of the insulating capping pattern (136). In exemplary embodiments, the inner nitride film (140) may be formed to be in contact with the outer oxide film (131). In other exemplary embodiments, when the direct contact hole (DCH) is formed to be biased in one direction during the etching of the direct contact hole (DCH), the inner nitride film (240) as illustrated in FIG. 3 may be formed instead of the inner nitride film (140). For example, when only one active region (ACT) is exposed among a plurality of active regions (ACT) adjacent to the sidewall of the first direct contact hole (DCH1) and the other active region (ACT) is not exposed, an outer oxide film (131) is not formed on the other active region (ACT) and it can directly contact the inner nitride film (240).

Referring to FIG. 6o, in the result of FIG. 6n, an inner insulating spacer (142) is formed along the inner wall of the first direct contact hole (DCH) in which an inner nitride film (140) is formed, covering the sidewalls of the first and second direct contacts (DC1, DC2), and a gapfill insulating pattern (144) is formed to fill the remaining space of the first direct contact hole (DCH1) in which the inner insulating spacer (142) is formed.

In order to form the inner insulating spacer (142) and the gapfill insulating pattern (144), a silicon oxide film may be formed on the inner nitride film (140) in the result of FIG. 6n, and a silicon nitride film may be formed on the silicon oxide film. Unnecessary portions of the silicon oxide film and the silicon nitride film may be removed so that the silicon oxide film and the silicon nitride film remain in the first direct contact hole (DCH1). A CVD or ALD process may be used to form the silicon oxide film and the silicon nitride film.

Referring to FIG. 6p, an inner insulating spacer film is formed to conformally cover the exposed surfaces in the result of FIG. 11j using a CVD or ALD process, and then the inner insulating spacer film is anisotropically etched to form a plurality of inner insulating spacers (142) from the inner insulating spacer film. During the anisotropic etching of the inner insulating spacer film to form a plurality of inner insulating spacers (142), a portion of the buffer layer (122) and a portion of the inner nitride film (140) covering the buffer layer (122) may be removed. As a result, a portion of the substrate (110), a portion of the inner nitride film (140), a portion of the inner insulating spacer (142) in the first direct contact hole (DCH), and a portion of the gapfill insulating pattern (144) may be exposed at the bottoms of the plurality of line spaces (LS). A plurality of inner insulating spacers (142) can cover the sidewalls of the bit line (BL) and the sidewalls of the insulating capping pattern (136) on the inner nitride film (140).

The plurality of inner insulating spacers (142) may be formed of a material different from the constituent material of the inner nitride film (140) and the constituent material of the gapfill insulating pattern (144). The plurality of inner insulating spacers (142) may be formed of a material having an etching selectivity with respect to each of the inner nitride film (140) and the gapfill insulating pattern (144). For example, the plurality of inner insulating spacers (142) may be formed of a silicon oxide film.

Referring to FIG. 6q, an outer insulating spacer (146) is formed to conformally cover the result of FIG. 6p. The outer insulating spacer (146) may be formed of a material having an etching selectivity with respect to a plurality of inner insulating spacers (142). For example, the outer insulating spacer (146) may be formed of a silicon nitride film. A CVD or ALD process may be used to form the outer insulating spacer (146).

Referring to FIG. 6r, in the result of FIG. 6q, a plurality of insulating fences (149) spaced apart from each other are formed in a line space (LS) defined by an outer insulating spacer (146) between each of a plurality of bit lines (BL), thereby dividing the line space (LS) into a plurality of contact spaces (CS).

A plurality of insulating fences (149) may be formed to vertically overlap the word line (118) on each word line (118). The plurality of insulating fences (149) may be formed of a silicon nitride film. In exemplary embodiments, while forming the plurality of insulating fences (149), a portion of the plurality of insulating capping patterns (136) may be consumed, thereby reducing the height of the plurality of insulating capping patterns (136).

Thereafter, a portion of the structures exposed through the plurality of contact spaces (CS) are removed to form a plurality of recess spaces (R1) exposing the active region (ACT) of the substrate (110) between each of the plurality of bit lines (BL). An anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process may be used to form the plurality of recess spaces (R1). For example, the outer insulating spacer (146) exposed through the plurality of contact spaces (CS) between each of the plurality of bit lines (BL) and a portion of the substrate (110) thereunder may be anisotropically etched, and a portion of the active region (ACT) of the substrate (110) exposed as a result may be isotropically etched to form the plurality of recess spaces (R1). Each of the plurality of recess spaces (R1) may be in communication with the contact space (CS). During the etching process to form the contact space (CS), a portion of each of the outer oxide film (131), the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144) may be consumed in an area adjacent to the upper surface of the substrate (110).

A portion of the active region (ACT) of the substrate (110), a portion of each of the outer oxide film (131), the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144) may be exposed through a plurality of recessed spaces (R1).

Referring to FIG. 6s, a plurality of contact plugs (150) are formed that fill a portion of a contact space (CS) between each of a plurality of bit lines (BL) while filling a plurality of recess spaces (R1) between each of a plurality of bit lines (BL).

When etching a portion of each of the upper conductive layer (134), the middle conductive layer (132), the lower conductive layer (130), and the direct contact (DC) using the insulating capping pattern (136) of FIG. 6m as an etching mask, if the outer oxide film (131) is not formed, the active region (ACT) exposed through the first direct contact hole (DCH1) may be etched together. The first direct contact hole (DCH) becomes enlarged due to the etching of the active region (ACT), so that the plurality of recessed spaces (R1) may not expose the active region (ACT) of the substrate (110) due to the inner nitride film (140), the inner insulating spacer (142), and the gapfill insulating pattern (144). This may cause a defect in which the plurality of contact plugs (150) are not connected to the active region (ACT) of the substrate (110). According to the technical idea of the present invention, since the active region (ACT) is not exposed through the first direct contact hole (DCH1) by the outer oxide film (131), the first direct contact hole (DCH1) is prevented from becoming enlarged, thereby preventing a defect in which a plurality of contact plugs (150) are not connected to the active region (ACT) of the substrate (110). Even when the first direct contact hole (DCH1) is etched and the active region (ACT) is exposed by the outer oxide film (131), a plurality of contact plugs (150) can be connected to the active region (ACT) of the substrate (110), so that the process margin of the first direct contact hole (DCH1) can be secured regardless of the position of the active region (ACT). In addition, since the width of the first direct contact hole (DCH1) in the first horizontal direction (X) can be secured sufficiently, a separation distance between the direct contact (DC) and the contact plug (150) can be secured, thereby preventing a defect in electrical connection between the direct contact (DC) and the contact plug (150).

Referring to FIG. 6t, a metal silicide film (172) and a plurality of conductive landing pads (LP) are sequentially formed on a plurality of contact plugs (150) exposed through a plurality of contact spaces (CS) (see FIG. 6s).

The contact plug (150) and the metal silicide film (172) may form at least a portion of the buried contact (BC) illustrated in FIG. 1. The plurality of conductive landing pads (LP) may extend to an upper portion of the insulating capping pattern (136) so as to vertically overlap portions of the plurality of bit lines (BL) while filling the plurality of contact spaces (CS) on the metal silicide film (172). The plurality of conductive landing pads (LP) may include a conductive barrier film (174) and a conductive layer (176).

In order to form a plurality of conductive landing pads (LP), a conductive barrier film (174) and a conductive layer (176) are formed on the entire surface of the resultant metal silicide film (172), and then a mask pattern (not shown) exposing a portion of the conductive layer (176) is formed on the conductive layer (176), and the conductive layer (176), the conductive barrier film (174), and the insulating films around them are etched using the mask pattern as an etching mask to form an upper recess space (R2). The mask pattern may be formed of a silicon nitride film, but is not limited thereto.

The plurality of conductive landing pads (LP) may have a plurality of island pattern shapes. The portions of the plurality of conductive landing pads (LP) extending horizontally outside the contact space (CS) may form the plurality of conductive landing pads (LP) as exemplified in Fig. 1.

The upper recessed space (R2) around the plurality of conductive landing pads (LP) can be filled with an insulating film (180) to electrically insulate the plurality of conductive landing pads (LP) from each other. Thereafter, a plurality of capacitor lower electrodes electrically connectable to the plurality of conductive landing pads (LP) can be formed on the insulating film (180).

In exemplary embodiments, after forming the upper recessed space (R2) around the plurality of conductive landing pads (LP) in the process described with reference to FIG. 6s, before filling the upper recessed space (R2) with the insulating film (180), at least a portion of the silicon oxide film forming the plurality of inner insulating spacers (142) through the upper recessed space (R2) can be removed.

In one example, the silicon oxide film forming the plurality of inner insulating spacers (142) can be completely removed through the upper recessed space (R2) so that the inner insulating spacers (142) are formed as air spacers.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present disclosure and have not been used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

110: Substrate
118: Word line
130: Lower challenge layer
131: Outer oxide film
132: Mid-challenge layer
134: Upper challenge layer
140: Inner nitride film
142: Inner insulation spacer
144: Gapfill insulation pattern
146: Outer insulation spacer
150: Contact plug
BL: Beat Line

Claims (20)

A substrate having multiple active regions;
A bit line extending horizontally on the substrate;
A first direct contact connected to a first active region selected from the plurality of active regions;
A second direct contact between the first direct contact and the bit line;
An inner nitride film in contact with the side walls of the first direct contact and the second direct contact;
A second active region adjacent to the first active region among the plurality of active regions;
A device isolation film interposed between the first active region and the second active region; and
An integrated circuit device comprising an outer oxide film that is in contact with the second active region on at least one side and interposed between the inner nitride film and the second active region. In the first paragraph,
A contact plug connected to the second active region and extending vertically to the upper surface of the substrate,
A gap-fill insulating pattern interposed between the lower portion of the contact plug and the first direct contact,
Further comprising an inner insulating spacer in contact with the inner nitride film,
An integrated circuit element, wherein the inner nitride film and the inner insulating spacer include a portion interposed between the first direct contact and the gapfill insulating pattern. In the second paragraph,
An integrated circuit element wherein a portion of the inner insulating spacer above the gapfill insulating pattern has a different thickness from a portion of the inner insulating spacer that comes into contact with the gapfill insulating pattern. In the second paragraph,
The above gapfill insulating pattern includes a portion interposed between the lower portion of the contact plug and the second direct contact,
An integrated circuit element, wherein a portion of the gapfill insulating pattern facing the first direct contact has a different thickness from a portion of the gapfill insulating pattern facing the second direct contact. In the first paragraph,
A contact plug connected to the second active region and extending vertically to the upper surface of the substrate;
A gap-fill insulating pattern interposed between the lower portion of the contact plug and the first direct contact; and
Further comprising an inner insulating spacer in contact with the inner nitride film,
The inner nitride film includes a portion interposed between the first direct contact and the gapfill insulating pattern and a portion in contact with the lower end of the contact plug,
An integrated circuit element, wherein the inner insulating spacer includes a portion interposed between the inner nitride film and the gapfill insulating pattern and a portion in contact with the lower end of the contact plug. In paragraph 5,
An integrated circuit element in which the outer oxide film includes a portion that comes into contact with the lower end of the contact plug. In the first paragraph,
A contact plug connected to the second active region and extending vertically to the upper surface of the substrate;
A gap-fill insulating pattern interposed between the lower portion of the contact plug and the first direct contact;
An outer insulating spacer covering the sidewall of the contact plug over the gapfill insulating pattern; and
Further comprising an inner insulating spacer in contact with the inner nitride film,
An integrated circuit element wherein the outer insulating spacer is spaced apart from the second direct contact with the inner nitride film and the inner insulating spacer interposed therebetween. In the first paragraph,
an inner insulating spacer spaced apart from the bit line with the inner nitride film interposed therebetween; and
Further comprising an outer insulating spacer in contact with the lower portion of the inner nitride film with the inner insulating spacer interposed therebetween,
An integrated circuit element in which the inner nitride film surrounds the bottom surface of the inner insulating spacer. In the first paragraph,
An integrated circuit element in which the outer oxide film is made of a silicon oxide film. In the first paragraph,
A contact plug connected to the second active region and extending vertically to the upper surface of the substrate;
A gap-fill insulating pattern interposed between the lower portion of the contact plug and the first direct contact;
An outer insulating spacer covering the sidewall of the contact plug over the gapfill insulating pattern; and
The above gapfill insulating pattern is made of a silicon nitride film,
An integrated circuit element in which the above outer insulating spacer is made of a silicon nitride film. In Article 10,
Further comprising an inner insulating spacer in contact with the inner nitride film,
The above inner insulating spacer is an integrated circuit element made of a silicon oxide film. In Article 10,
a first inner insulating spacer interposed between the gapfill insulating pattern and the first direct contact; and
A second inner insulating spacer interposed between the outer insulating spacer and the second direct contact,
The above first inner insulating spacer is made of a silicon oxide film,
An integrated circuit element in which the second inner insulating spacer is formed of a silicon oxide film, an air spacer, or a combination thereof. A substrate having multiple active regions,
A plurality of bit lines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction intersecting the first horizontal direction;
A first direct contact connected to a first active region selected from the plurality of active regions;
A second direct contact connected between the first direct contact and a first bit line selected from the plurality of bit lines;
a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions and extending vertically on the substrate; and
A spacer structure interposed between the first bit line and the contact plug,
The above spacer structure,
An inner nitride film in contact with the side wall of the above direct contact,
Including an outer oxide film that overlaps the second active region in the vertical direction and contacts the second active region on at least one side;
An integrated circuit element in which the inner nitride film is spaced apart from the second active region with the outer oxide film therebetween. In Article 13,
An integrated circuit element wherein each of the above plurality of bit lines includes a lower conductive layer formed of a doped polysilicon film and an upper conductive layer including a metal. In Article 13,
The above spacer structure further includes a gapfill insulating pattern interposed between the lower portion of the contact plug and the first direct contact,
The inner nitride film includes a portion interposed between the first direct contact and the gapfill insulating pattern,
An integrated circuit element wherein the outer oxide film overlaps the contact plug in the vertical direction and includes a portion facing the first direct contact. In Article 13,
a third active region spaced apart from the second active region with the first active region interposed between the plurality of active regions; and
Further comprising a device isolation film interposed between the first active region and the second active region and between the second active region and the third active region,
An integrated circuit element in which the inner nitride film is separated from the third active region by the element isolation film. A step of forming a plurality of word lines within a plurality of word line trenches extending in a first horizontal direction of a substrate including a plurality of active regions;
A step of forming a first direct contact hole by removing a portion of the substrate disposed between the plurality of word lines among the plurality of active regions, and exposing a first active region selected from the plurality of active regions and a second active region adjacent to the first active region through the first direct contact hole;
A step of forming an outer oxide film on the first active region and the second active region exposed through the first direct contact hole;
A step of removing the outer oxide film on the first active region so that the first direct contact hole and the first active region are connected;
A step of forming a first direct contact filling the first direct contact hole; and
A method for manufacturing an integrated circuit device, comprising the steps of: depositing a plurality of conductive layers and an insulating capping pattern on the first direct contact, and etching a portion of each of the plurality of conductive layers and the first direct contact using the insulating capping pattern as an etching mask to form a bit line connected to the first direct contact. In Article 17,
In the step of forming the outer oxide film,
A method for manufacturing an integrated circuit device, wherein the outer oxide film is formed by a selective oxidation process for the first active region and the second active region. In Article 17,
After the step of forming the first direct contact,
A step of forming a second direct contact hole by removing an outer oxide film formed on an upper portion of the first direct contact and a portion of the conductive layer; and
A method for manufacturing an integrated circuit device, further comprising: forming a second direct contact filling the second direct contact hole. In Article 17,
After the step of forming the outer oxide film,
A method for manufacturing an integrated circuit device, further comprising the step of forming a sacrificial film covering the outer oxide film along the inner wall of the first direct contact hole.

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