KR20240126387A - A semiconductor device and training method - Google Patents

Abstract

A semiconductor device of the present invention may include an input circuit having a buffer for buffering an external signal received from a pad, a variable delay circuit for delaying a signal output from the buffer based on a plurality of delay setting signals, a latch for latching an output of the variable delay circuit based on a clock signal and outputting it as an internal signal, and a setting circuit for storing the plurality of delay setting signals.

Description

{A SEMICONDUCTOR DEVICE AND TRAINING METHOD}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device and a training method.

Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, semiconductor devices that can store information are being demanded in various electronic devices such as computers and portable communication devices. In addition, semiconductor devices have been continuously developed to increase integration and improve operating speed.

To improve the operating speed, synchronous memory devices that operate in synchronization with the clock signal have been developed, and the frequency of the clock signal is increasing for faster operating speed.

However, as the frequency of the clock signal increases, the signal integrity may deteriorate due to noise and skew. Therefore, it is necessary to find the optimal signal window or compensate for the signal skew through a training operation.

Embodiments of the present invention provide a semiconductor device and a training method capable of performing a training operation for each semiconductor device in a semiconductor integrated circuit having a plurality of semiconductor devices mounted thereon. In addition, a semiconductor device and a training method capable of performing a training operation for each pad of each semiconductor device are provided.

A semiconductor device according to an embodiment of the present invention may include an input circuit having a buffer for buffering an external signal received from a pad, a variable delay circuit for delaying a signal output from the buffer based on a plurality of delay setting signals, a latch for latching an output of the variable delay circuit based on a clock signal and outputting it as an internal signal, and a setting circuit for storing the plurality of delay setting signals.

A training method for a semiconductor device according to an embodiment of the present invention may include a step of performing a course training operation for each of a plurality of memory devices and a step of performing a fine training operation for each of pads provided in each of the plurality of memory devices.

It can improve the operational reliability of semiconductor devices.

FIG. 1 is a drawing for explaining a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 2 is a drawing for explaining a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining an input circuit according to an embodiment of the present invention.
FIG. 4 is a graph for explaining the operation of an input circuit according to an embodiment of the present invention.
FIG. 5 is a diagram for explaining an input circuit according to another embodiment of the present invention.
FIG. 6 is a diagram for explaining a reference voltage generation circuit according to another embodiment of the present invention.
FIG. 7 is a flowchart for explaining a training operation of a semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

FIG. 1 is a drawing for explaining a semiconductor integrated circuit according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor integrated circuit (1000) may include a plurality of semiconductor devices, for example, a memory device (100) and a memory buffer (200).

A plurality of memory devices (100) can be electrically connected to a memory buffer (200) through a line (L).

The memory buffer (200) can receive external signals (CS_e, CA_e, CLK_te, CLK_ce) from an external device, for example, a memory controller, and transmit the received external signals to a plurality of memory devices (100) through a line (L).

A semiconductor integrated circuit (1000) according to an embodiment of the present invention configured as described above can operate as follows.

A plurality of memory devices (100) may operate based on external signals (CS_e, CA_e, CLK_te, CLK_ce) provided from a memory buffer (200). At this time, the external signals (CS_e, CA_e, CLK_te, CLK_ce) may include an external chip select signal (CS_e), an external operation control signal (CA_e), and a pair of external clock signals (CLK_te, CLK_ce) having opposite phases. The external chip select signal (CS_e) may be a signal used to select one of the plurality of memory devices (100). The external operation control signal (CA_e) may include a command and an address, and may be a signal used to perform operations such as a write operation and a read operation of the selected memory device. The pair of external clock signals (CLK_te, CLK_ce) may be clock signals synchronized with the external chip select signal (CS_e) and the external operation control signal (CA_e).

A plurality of memory devices (100) may be configured to determine an external chip select signal (CS_e) and an external operation control signal (CA_e) based on a pair of external clock signals (CLK_te, CLK_ce).

As illustrated in FIG. 1, a semiconductor integrated circuit (1000) may be configured to transmit external signals (CS_e, CA_e, CLK_te, CLK_ce) to a plurality of memory devices (100) using a single memory buffer (200). Accordingly, depending on the distance and position between the memory buffer (200) and the memory device (100), the arrival times of the external signals (CS_e, CA_e, CLK_te, CLK_ce) reaching each memory device from the memory buffer (200) may be different, and the arrival times between the external signals (CS_e, CA_e, CLK_te, CLK_ce) may also be different.

Therefore, the semiconductor integrated circuit (1000) can perform a training operation so that the arrival times of the external signals (CS_e, CA_e, CLK_te, CLK_ce) from the memory buffer (200) to each of the plurality of memory devices (100) become the same. For example, each of the plurality of memory devices (100) can set an internal delay time through the training operation. In addition, each of the plurality of memory devices (100) can set a level of a reference voltage for determining the external signals (CS_e, CA_e, CLK_te, CLK_ce), particularly, an external chip selection signal (CS_e) and an external operation control signal (CA_e), through the training operation.

FIG. 2 is a drawing for explaining a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, each of a plurality of semiconductor devices (100), for example, a memory device, may include a setting circuit (110), an input circuit (120), and an internal circuit (130).

The setting circuit (110) can store the setting values of the internal delay time and the reference voltage level through a training operation. In addition, the setting circuit (110) can provide the stored setting values through the training operation to the input circuit (120) as a setting signal (M_set). For example, the setting circuit (110) can include a mode register set.

The input circuit (120) can set an internal delay time and a reference voltage level based on a setting signal (M_set). In addition, the input circuit (120) can determine an external chip selection signal (CS_e) and an external operation control signal (CA_e) based on a pair of external clocks (CLK_te, CLK_ce), a set internal delay time, and a set reference voltage level, and can transmit the determined external chip selection signal (CS_e) and the external operation control signal (CA_e) to the internal circuit (130) as an internal chip selection signal (CS_i) and an internal operation control signal (CA_i).

The internal circuit (130) can operate based on the internal chip selection signal (CS_i) and the internal operation control signal (CA_i) transmitted from the input circuit (120). For example, the internal circuit (130) can be activated or deactivated based on the internal chip selection signal (CS_i). In addition, the internal circuit (130) activated based on the internal operation control signal (CA_i) can perform a write operation or a read operation.

FIG. 3 is a diagram for explaining an input circuit according to an embodiment of the present invention.

Referring to FIG. 3, the input circuit (120-1) may include a reference voltage generation circuit (121), a plurality of buffers (122, 123, 124-0 to 124-13), a delay circuit (125), a plurality of variable delay circuits (126, 127-0 to 127-13), and a plurality of latches (128, 129-0 to 129-13).

The reference voltage generation circuit (121) can generate a reference voltage (VREFCA) for determining an operation control signal based on a reference voltage setting signal (M_VREFCA[6:0]). For example, the reference voltage generation circuit (121) can adjust the voltage level of the reference voltage (VREFCA) for determining an operation control signal based on the reference voltage setting signal (M_VREFCA[6:0]).

The plurality of buffers (122, 123, 124-0 to 124-13) may include a buffer for a clock (122), a buffer for a chip select signal (123), and a plurality of buffers for operation control (124-0 to 124-13).

A clock buffer (122) can buffer a pair of external clock signals (CLK_te, CLK_ce) transmitted from a pad (PAD) and transmit them to a delay circuit (125).

The buffer (123) for the chip select signal can buffer an external chip select signal (CS_e) transmitted from a pad (PAD) and transmit it to a variable delay circuit (126). At this time, the buffer (123) for the chip select signal can buffer the external chip select signal (CS_e) based on the level of the reference voltage (VREFCS) for determining the chip select signal. For example, the buffer (123) for the chip select signal can compare the level of the reference voltage (VREFCS) for determining the chip select signal with the level of the external chip select signal (CS_e) and output the comparison result to the variable delay circuit (126).

A plurality of operation control buffers (124-0 to 124-13) can buffer external operation control signals (CA_e[0] to CA_e[13]) transmitted from pads (PAD) and transmit them to variable delay circuits (127-0 to 127-13). At this time, the plurality of operation control buffers (124-0 to 124-13) can buffer the external operation control signals (CA_e[0] to CA_e[13]) based on the level of the operation control signal discrimination reference voltage (VREFCA). For example, the plurality of operation control buffers (124-0 to 124-13) can compare the level of the operation control signal discrimination reference voltage (VREFCA) with the level of the external operation control signals (CA_e[0] to CA_e[13]) and output the comparison result to the variable delay circuits (127-0 to 127-13). Here, the external operation control signals (CA_e[0] to CA_e[13]) may include the first to fourteenth external operation control signals (CA_e[0] to CA_e[13]). Therefore, the plurality of operation control buffers (124_0 to 124-13) may include the first to fourteenth operation control buffers (124_0 to 124_13). The first to fourteenth, i.e., 14 external operation control signals (CA_e[0] to CA_e[13]) are only described as examples, and the number of external operation control signals is not limited.

The delay circuit (125) can delay the output of the clock buffer (122) by a set delay time to generate a clock signal (CLK_ca) for operation control and a clock signal (CLK_cs) for chip selection.

A plurality of variable delay circuits (126, 127_0 to 127_13) may include a variable delay circuit (126) for a chip select signal and a plurality of variable delay circuits (127-0 to 127-13) for operation control signals.

A variable delay circuit (126) for a chip select signal has a delay time set based on a chip select delay setting signal (M_CS_DLY[3:0]) and can delay the output of a buffer (123) for chip select by the set delay time.

The variable delay circuits (127-0 to 127-13) for multiple motion control signals may include variable delay circuits (127-0 to 127-13) for the first to fourteenth motion control signals.

Each of the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals has a delay time set based on each of the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]), and can delay the output of each of the first to fourteenth operation control buffers (124-0 to 124-13) by the set delay time.

Each of the plurality of latches (128, 129-0 to 129-13) may include a flip-flop. For example, the plurality of flip-flops (128, 129-0 to 129-13) may include a flip-flop (128) for a chip select signal and a plurality of flip-flops (129-0 to 129-13) for operation control signals.

The flip-flop (128) for the chip select signal can latch the output of the variable delay circuit (126) for the chip select signal based on the clock signal (CLK_cs) for the chip select and output it as the internal chip select signal (CS_i). For example, the flip-flop (128) for the chip select signal can latch the output of the variable delay circuit (126) for the chip select signal at the edge of the clock signal (CLK_cs) for the chip select. In addition, the flip-flop (128) for the chip select signal can output the latched output as the internal chip select signal (CS_i). In more detail, for example, the flip-flop (128) for the chip select signal can latch the output level of the variable delay circuit (126) for the chip select signal at the rising timing or falling timing of the clock signal (CLK_cs) for the chip select and output the latched output level as the level of the internal chip select signal (CLK_cs).

The flip-flops (129-0 to 129-13) for a plurality of operation control signals may include flip-flops (129-0 to 129-13) for first to fourteenth operation control signals. The flip-flops (129-0 to 129-13) for the first to fourteenth operation control signals may latch the outputs of the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals based on the clock signal (CLK_ca) for operation control and output them as internal operation control signals (CA_i[0] to CA_i[13]). At this time, the internal operation control signals (CA_i[0] to CA_i[13]) may include the first to fourteenth internal operation control signals (CA_i[0] to CA_i[13]). Accordingly, each of the flip-flops (129-0 to 129-13) for the first to fourteenth operation control signals can latch each of the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals based on the clock signal (CLK_ca) for operation control, and output the latched outputs as the first to fourteenth internal operation control signals (CA_i[0] to CA_i[13]), respectively. At this time, the first to fourteenth operation control flip-flops (129-0 to 129-13) can latch the output of the first to fourteenth operation control signal variable delay circuits (127-0 to 127-13) at the edge of the operation control clock signal (CLK_ca), for example, the rising timing or the falling timing, and output the latched output as the first to fourteenth internal operation control signals (CA_i[0] to CA_i[13]).

The reference voltage setting signal (M_VREFCA[6:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) described in Fig. 3 may be the setting signal (M_set) stored in the setting circuit (110) described in the description of Fig. 2. That is, the setting signal (M_set) may include the reference voltage setting signal (M_VREFCA[6:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]). Here, the reference voltage setting signal (M_VREFCA[6:0]) for adjusting the level of the reference voltage (VREFCA) for determining the operation control signal that is commonly provided to the first to fourteenth operation control buffers (124-0 to 124-13) may be stored in the setting circuit (110) as a result of the coarse training operation described later. In addition, the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) for setting the delay time of each of the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals and the chip select delay setting signal (M_CS_DLY[3:0]) for setting the delay time of the variable delay circuit (126) for the chip select signal may be stored in the setting circuit (110) as a result of the fine training operation described later.

FIG. 4 is a graph for explaining the operation of an input circuit according to an embodiment of the present invention.

FIG. 4 is a graph for explaining the delay time adjustment of the variable delay circuit (126) for the chip selection signal and the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals illustrated in FIG. 3.

Each of the chip select delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) may include first to fourth bit signals ([3:0]). Here, the first to fourth bit signals ([3:0]) may have values of (0,0,0,0) to (1,1,1,1) when each bit signal is listed in sequence. The minimum value (Min) of the first to fourth bit signals ([3:0]) may be (0,0,0,0), and the maximum value (Max) may be (1,1,1,1).

Referring to FIG. 4, each of the chip select delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) can adjust the delay time of the variable delay circuit (126) for the chip select signal and the variable delay circuit (127-0 to 127-13) for the first to fourteenth operation control signals to a minimum when the first to fourth bit signals ([3:0]) are at a minimum value (Min). In addition, the chip select delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) can adjust the delay time of the variable delay circuit (126) for the chip select signal and the variable delay circuit (127-0 to 127-13) for the first to fourteenth operation control signals to the maximum when the first to fourth bit signals ([3:0]) are at the maximum value (Max). In addition, the chip select delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) can adjust the delay time of the variable delay circuit (126) for the chip select signal and the variable delay circuit (127-0 to 127-13) for the first to fourteenth operation control signals to the maximum when the value of the first to fourth bit signals ([3:0]) increases. The delay time of the variable delay circuit (127-0 to 127-13) for the 14th operation control signals can be increased. Each of the chip select delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) can reduce the delay time of the variable delay circuit (126) for the chip select signal and the variable delay circuit (127-0 to 127-13) for the first to fourteenth operation control signals as the value of the first to fourth bit signals ([3:0]) decreases. When applying the course training result, each of the chip selection delay setting signal (M_CS_DLY[3:0]) and the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) can be set to the center value of the first to fourth bit signals ([3:0]), and when applying the fine training result, can be increased or decreased from the center value.

Each of the plurality of memory devices according to an embodiment of the present invention can set the level of the operation control signal determination reference voltage (VREFCA) for determining the plurality of external operation control signals (CA_e[0] to CA_e[13]) through a course training operation.

In addition, each memory device according to an embodiment of the present invention can set a delay time for each of a plurality of external operation control signals (CA_e[0] to CA_e[13]) and an external chip selection signal (CS_e) through a fine training operation. That is, each memory device according to an embodiment of the present invention can set a delay time for each signal input to each pad (PAD).

FIG. 5 is a diagram for explaining an input circuit according to another embodiment of the present invention.

Referring to FIG. 5, the input circuit (120-2) may include a reference voltage generation circuit (1211), a plurality of buffers (1221, 1231, 1241-0 to 1241-13), a delay circuit (1251), a plurality of variable delay circuits (1261, 1271-0 to 1271-13), a plurality of latches (1281, 1291-0 to 1291-13), and a plurality of multiplexers (M_0 to M_13).

The reference voltage generation circuit (1211) can generate a plurality of reference voltages (VREFCA_B-4 to VREFCA_B+3) for determining a plurality of operation control signals based on the reference voltage setting signal (M_VREFCA[6:0]). For example, the reference voltage generation circuit (1211) can adjust the voltage level of the plurality of reference voltages (VREFCA_B-4 to VREFCA_B+3) for determining a plurality of operation control signals based on the reference voltage setting signal (M_VREFCA[6:0]).

The plurality of buffers (1221, 1231, 1241-0 to 1241-13) may include a buffer for a clock (1221), a buffer for a chip select signal (1231), and a plurality of buffers for operation control (1241-0 to 1241-13).

A clock buffer (1221) can buffer a pair of external clock signals (CLK_te, CLK_ce) transmitted from a pad (PAD) and transmit them to a delay circuit (1251).

The buffer (1231) for the chip select signal can buffer an external chip select signal (CS_e) transmitted from a pad (PAD) and transmit it to a variable delay circuit (1261). At this time, the buffer (1231) for the chip select signal can buffer the external chip select signal (CS_e) based on the level of the reference voltage (VREFCS) for determining the chip select signal. For example, the buffer (1231) for the chip select signal can compare the level of the reference voltage (VREFCS) for determining the chip select signal with the level of the external chip select signal (CS_e) and output the comparison result to the variable delay circuit (1261).

A plurality of motion control buffers (1241-0 to 1241-13) can buffer external motion control signals (CA_e[0] to CA_e[13]) transmitted from pads (PAD) and transmit them to variable delay circuits (1271-0 to 1271-13). At this time, each of the plurality of motion control buffers (1241-0 to 1241-13) can buffer a corresponding signal among the external motion control signals (CA_e[0] to CA_e[13]) based on a level of one selected among the plurality of motion control signal determination reference voltages (VREFCA_B-4 to VREFCA_B+3). For example, the plurality of operation control buffers (1241-0 to 1241-13) can compare the level of the reference voltage for determining the selected operation control signal with the level of the corresponding external operation control signal (CA_e[0] to CA_e[13]), and output the comparison result to the variable delay circuit (1271-0 to 1271-13). Here, the external operation control signals (CA_e[0] to CA_e[13]) can include the first to fourteenth external operation control signals (CA_e[0] to CA_e[13]). Therefore, the plurality of operation control buffers (1241_0 to 1241-13) can include the first to fourteenth operation control buffers (1241-0 to 1241-13).

The plurality of multiplexers (M_0 to M_13) may include first to fourteenth multiplexers (M_0 to M_13). Each of the first to fourteenth multiplexers (M_0 to M_13) may select one of the plurality of operation control signal discrimination reference voltages (VREFCA_B-4 to VREFCA_B+3) based on each of the first to fourteenth reference voltage level selection signals (M_CA0_VREF[2:0] to M_CA13_VREF[2:0]), and provide the selected operation control signal discrimination reference voltage to each of the first to fourteenth operation control buffers (1241-0 to 1241-13). For example, the first multiplexer (M_0) may select one of a plurality of operation control signal discrimination reference voltages (VREFCA_B-4 to VREFCA_B+3) based on the first reference voltage level selection signal (M_CA0_VREF[2:0]) and provide the selected operation control signal discrimination reference voltage to the first operation control buffer (1241-0).

The delay circuit (1251) can delay the output of the clock buffer (1221) by a set delay time to generate a clock signal (CLK_ca) for operation control and a clock signal (CLK_cs) for chip selection.

A plurality of variable delay circuits (1261, 1271_0 to 1271_13) may include a variable delay circuit (1261) for a chip select signal and a plurality of variable delay circuits (1271-0 to 1271-13) for operation control signals.

A variable delay circuit (1261) for a chip select signal has a delay time set based on a chip select delay setting signal (M_CS_DLY[3:0]) and can delay the output of a buffer (123) for chip select by the set delay time.

The variable delay circuits (1271-0 to 1271-13) for multiple motion control signals may include variable delay circuits (1271-0 to 1271-13) for the first to fourteenth motion control signals.

Each of the variable delay circuits (1271-0 to 1271-13) for the first to fourteenth operation control signals has a delay time set based on each of the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]), and can delay the output of each of the first to fourteenth operation control buffers (1241-0 to 1241-13) by the set delay time.

Each of the plurality of latches (1281, 1291-0 to 1291-13) may include a flip-flop. For example, the plurality of flip-flops (1281, 1291-0 to 1291-13) may include a flip-flop (1281) for a chip select signal and a plurality of flip-flops (1291-0 to 1291-13) for operation control signals.

A flip-flop (1281) for a chip select signal can latch the output of a variable delay circuit (1261) for a chip select signal based on a clock signal (CLK_cs) for a chip select and output it as an internal chip select signal (CS_i).

The flip-flops (1291-0 to 1291-13) for multiple operation control signals may include flip-flops (1291-0 to 1291-13) for first to fourteenth operation control signals. The flip-flops (1291-0 to 1291-13) for the first to fourteenth operation control signals may latch the outputs of the variable delay circuits (1271-0 to 1271-13) for the first to fourteenth operation control signals based on the clock signal (CLK_ca) for operation control and output them as internal operation control signals (CA_i[0] to CA_i[13]). At this time, the internal operation control signals (CA_i[0] to CA_i[13]) may include the first to fourteenth internal operation control signals (CA_i[0] to CA_i[13]). Accordingly, each of the flip-flops (1291-0 to 1291-13) for the first to fourteenth operation control signals can latch each of the variable delay circuits (1271-0 to 1271-13) for the first to fourteenth operation control signals based on the clock signal (CLK_ca) for operation control, and output the latched outputs as the first to fourteenth internal operation control signals (CA_i[0] to CA_i[13]), respectively.

The reference voltage setting signal (M_VREFCA[6:0]), the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]), and the first to fourteenth reference voltage level selection signals (M_CA0_VREF[2:0] to M_CA13_VREF[2:0]) described in FIG. 5 may be the setting signal (M_set) stored in the setting circuit (110) described in the description of FIG. 2. That is, the setting signal (M_set) may include a reference voltage setting signal (M_VREFCA[6:0]), a first to fourteenth operation control delay setting signal (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]), and a first to fourteenth reference voltage level selection signal (M_CA0_VREF[2:0] to M_CA13_VREF[2:0]). Here, the reference voltage setting signal (M_VREFCA[6:0]) for adjusting the level of a plurality of operation control signal determination reference voltages (VREFCA_B-4 to VREFCA_B+3) commonly provided to the first to fourteenth operation control buffers (1241-0 to 1241-13) may be stored in the setting circuit (110) as a result of a coarse training operation. In addition, the first to fourteenth operation control delay setting signals (M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) that set the delay time of each of the variable delay circuits (127-0 to 127-13) for the first to fourteenth operation control signals and the chip select delay setting signal (M_CS_DLY[3:0]) that sets the delay time of the variable delay circuit (126) for the chip select signal can be stored in the setting circuit (110) as a result of the fine training operation. In addition, the first to fourteenth reference voltage level selection signals (M_CA0_VREF[2:0] to M_CA13_VREF[2:0]) for selecting and providing one of a plurality of reference voltages (VREFCA_B-4 to VREFCA_B+3) for determining a plurality of operation control signals to each of the first to fourteenth operation control buffers (1241-0 to 1241-13) may also be stored in the setting circuit (110) as a result of the fine training operation.

FIG. 6 is a diagram for explaining a reference voltage generation circuit according to another embodiment of the present invention.

Referring to FIG. 6, the reference voltage generation circuit (1211) may include a voltage divider circuit (Voltage Divider, 1211-1), a plurality of decoding circuits (Decoders, 1211-2-1 to 1211-2-8), and a plurality of selection circuits (1211-3-1 to 1211-3-8). For example, the plurality of decoding circuits (1211-2-1 to 1211-2-8) may include first to eighth decoding circuits (1211-2-1 to 1211-2-8), and the plurality of selection circuits (1211-3-1 to 1211-3-8) may include first to eighth selection circuits (1211-3-1 to 1211-3-8).

The voltage distribution circuit (1211-1) can generate a plurality of distribution voltages (V_dv[127:0]) having different voltage levels. At this time, the plurality of distribution voltages (V_dv[127:0]) can include the first to 128th distribution voltages (V_dv[0] to V_dv[127]).

Each of the first to eighth decoding circuits (1211-2-1 to 1211-2-8) can decode the reference voltage setting signal (M_VREFCA[6:0]) to generate the first to eighth decoding signals (Dec-4[127:0], Dec-3[127:0], Dec-2[127:0], Dec-1[127:0], Dec-0[127:0], Dec+1[127:0], Dec+2[127:0], Dec+3[127:0]), respectively. At this time, the decoding values of the first to eighth decoding signals (Dec-4[127:0], Dec-3[127:0], Dec-2[127:0], Dec-1[127:0], Dec-0[127:0], Dec+1[127:0], Dec+2[127:0], Dec+3[127:0]) may be different from each other. For example, based on the decoding value of the fifth decoding signal (Dec-0[127:0]) which is the output of the fifth decoding circuit (1211-2-5), the decoding values of the outputs (Dec-1[127:0], Dec-2[127:0], Dec-3[127:0], Dec-4[127:0]) of the fourth decoding circuit (1211-2-4), the third decoding circuit (1211-2-3), the second decoding circuit (1211-2-2) and the first decoding circuit (1211-2-1) are sequentially lowered, and the decoding values of the sixth decoding circuit (1211-2-6), the seventh decoding circuit (1211-2-7) and the eighth decoding circuit (1211-2-8) are sequentially lowered. The first to eighth decoding circuits (1211-2-1 to 1211-2-8) can be configured so that the decoding values of the outputs (Dec+1[127:0], Dec+2[127:0], Dec+3[127:0]) sequentially increase.

Each of the first to eighth selection circuits (1211-3-1 to 1211-3-8) may be configured to select one of the first to 128th division voltages (V_dv[0] to V_dv[127]) based on each of the first to eighth decoding signals (Dec-4[127:0], Dec-3[127:0], Dec-2[127:0], Dec-1[127:0], Dec-0[127:0], Dec+1[127:0], Dec+2[127:0], Dec+3[127:0]), and output the selected division voltage as the first to eighth operation control signal determination reference voltage (VREFCA_B-4 to VREFCA_B+3). For example, the first selection circuit (1211-3-1) may select one of the first to 128th division voltages (V_dv[127:0]) based on the first decoding signal (Dec-4[127:0]) and output the selected division voltage as the first operation control signal discrimination reference voltage (VREFCA_B-4). Here, the plurality of operation control signal discrimination reference voltages (VREFCA_B-4 to VREFCA_B+3) may include the first to eighth operation control signal discrimination reference voltages (VREFCA_B-4 to VREFCA_B+3).

Each of the first to eighth selection circuits (1211-3-1 to 1211-3-8) can be configured to select a division voltage corresponding to each decoding value of the first to eighth decoding signals (Dec-4[127:0], Dec-3[127:0], Dec-2[127:0], Dec-1[127:0], Dec-0[127:0], Dec+1[127:0], Dec+2[127:0], Dec+3[127:0]). Accordingly, the output levels (VREFCA_B-1, VREFCA_B-2, VREFCA_B-3, VREFCA_B-4) of the fourth selection circuit (1211-3-4), the third selection circuit (1211-3-3), the second selection circuit (1211-3-2), and the first selection circuit (1211-3-1) can be sequentially lowered based on the output of the fifth selection circuit (1211-3-5), i.e., the reference voltage (VREFCA_BASE) for determining the fifth operation control signal. In addition, the levels of the outputs (VREFCA_B+1, VREFCA_B+2, VREFCA_B+3) of the sixth selection circuit (1211-3-6), the seventh selection circuit (1211-3-7), and the eighth selection circuit (1211-3-8) can sequentially increase based on the output of the fifth selection circuit (1211-3-5), that is, the reference voltage (VREFCA_BASE) for determining the fifth operation control signal.

FIG. 7 is a flowchart for explaining a training operation of a semiconductor integrated circuit according to an embodiment of the present invention.

Referring to FIG. 7, a training operation method of a semiconductor integrated circuit including a plurality of memory devices may include an activation step (S10), a coarse training step (S20), and a fine training step (S30).

The activation step (S10) is a step of activating a plurality of memory devices, and may include a power up operation (Power Up) and an initialization operation (Initialization). At this time, the power up operation (Power Up) may include an operation of waiting until a specific node voltage level inside the memory device increases above a set voltage level after a power voltage is first applied to the memory device. The initialization operation (Initialization) may include an operation of forming outputs of specific circuits inside the memory device or specific nodes to a set level. That is, the activation step (S10) may include operations of applying a power voltage to the memory device and preparing the memory device to perform normal operations.

The course training step (S20) may include a step of performing a training operation for each of a plurality of memory devices. For example, the course training step (S20) may include a step (S21) of training a reference voltage (VREFCS) for determining a chip selection signal based on a window (CS Eye) of an internal chip selection signal (CS_i) for each of a plurality of memory devices, and a step (S22) of training a reference voltage (VREFCA) for determining an operation control signal based on a window (CA Eye) of an internal operation control signal (CA_i) for each of a plurality of memory devices.

The fine training step (S30) may include a step of performing a training operation per pin or per pad provided in each of the plurality of memory devices. For example, the fine training step (S30) may include a step (S31) of training for each of the reference voltages (VREFCS, VREFCA_B-4 to VREFCA_B+3) for determining signals (e.g., multiple external operation control signals (CA_e[0] to CA_e[13] or external chip selection signals (CS_e))) received through each pin or each pad provided in one memory device. In addition, the fine training step (S30) may include an operation (S32) of training for a delay time of signals (e.g., multiple external operation control signals (CA_e[0] to CA_e[13] or external chip selection signals (CS_e)) received through each pin or each pad provided in one memory device.

For example, in more detail, the course training operation (S20) may include an operation of storing a reference voltage setting signal (M_VREFCA[6:0]) in the setting circuit (110), and the fine training operation (S30) may include an operation of storing a reference voltage level selection signal (M_CA0_VREF[2:0] to M_CA13_VREF[2:0]) for selecting one of a plurality of operation control signal determination reference voltages (VREFCA_B-4 to VREFCA_B+3) generated according to the reference voltage setting signal (M_VREFCA[6:0]) in the setting circuit (110) (S31). In addition, the fine training operation (S30) may include an operation of storing a delay time setting signal (M_CS_DLY[3:0], M_CA0_DLY[3:0] to M_CA13_DLY[3:0]) for determining a delay time of signals received for each pin in the setting circuit (110).

Accordingly, the semiconductor integrated circuit according to the embodiment of the present invention can perform a coarse training operation for each memory device and a fine training operation for each pin of each memory device, thereby setting a reference voltage and a delay time according to each training result.

Although the embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, this is only for explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the embodiments. Various forms of substitution, modification, and change of the embodiments may be made by those skilled in the art without departing from the technical idea of the present invention described in the claims, and this will also be considered to fall within the scope of the present invention.

1000: Semiconductor integrated circuits 100: Memory devices
110: Setting circuit 120: Input circuit
130: Internal circuit

Claims (11)

An input circuit having a buffer for buffering an external signal received from a pad, a variable delay circuit for delaying a signal output from the buffer based on a plurality of delay setting signals, and a latch for latching an output of the variable delay circuit based on a clock signal and outputting it as an internal signal; and
A setting circuit including a setting circuit storing the plurality of delay setting signals.
Semiconductor devices.
In the first paragraph,
The above variable delay circuit,
Adjusting the delay time based on the above plurality of delay setting signals and delaying the signal output from the buffer with the adjusted delay time.
Semiconductor devices.
In the first paragraph,
The above buffer is,
Buffering the external signal based on the level of the reference voltage.
Semiconductor devices.
In the third paragraph,
Further comprising a reference voltage generation circuit for adjusting the level of the reference voltage based on a reference voltage setting signal.
Semiconductor devices.
In paragraph 4,
The above setting circuit is,
Additional storage of the above reference voltage setting signal
Semiconductor devices.
In the third paragraph,
A reference voltage generation circuit that generates a plurality of reference voltages based on a reference voltage setting signal, and
Further comprising a multiplexer providing one of the plurality of reference voltages to the buffer based on a reference voltage selection signal.
Semiconductor devices.
In Article 6,
The above setting circuit is,
Additional storage of the above reference voltage setting signal and the above reference voltage selection signal.
Semiconductor devices.
A step of performing a course training operation for each of a plurality of memory devices; and
A step of performing a fine training operation for each pad provided in each of the plurality of memory devices
Training methods.
In Article 8,
The above plurality of memory devices,
Receiving external signals through a memory buffer
Training methods.
In Article 9,
The steps for performing the above course training movements are:
A step of adjusting a reference voltage level for determining the external signals based on a window of the external signals received by each of the plurality of memory devices.
Training methods.
In Article 10,
The steps for performing the above fine training movements are:
A step of selecting the level of the reference voltage based on the window of external signals received for each of the above pads, and
A step of adjusting the delay time of the external signals based on the window of the external signals received for each pad is included.
Training methods.

Images