KR20240119595A - Gate driver and electroluminescent display device including the same - Google Patents

Abstract

The gate driver according to this embodiment includes a first circuit unit that outputs a scan clock that periodically swings between a gate-off voltage and a gate-on voltage; a second circuit unit outputting a first high-potential power supply voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage, and a second high-potential power supply voltage fixed to the gate-on voltage; and a gate stage including an input unit that activates the Q node with the second high-potential power supply voltage in a first period, and an inverter unit that activates the QB node with the first high-potential power supply voltage in a second period following the first period. It includes, and the first high-potential power supply voltage is overshooted from the gate-on voltage to the boosting-on voltage in synchronization with rising edges of the scan clock.

Description

Gate driver and electroluminescent display device including the same {GATE DRIVER AND ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING THE SAME}

This specification relates to a gate driver and an electroluminescence display device including the same.

An electroluminescent display device includes pixels arranged in a matrix form and supplies image data to the pixels in synchronization with a scan signal to adjust the luminance of the pixels. An electroluminescent display device generates a scan signal using a gate driver including a plurality of gate stages. Each gate stage receives a scan clock and outputs a scan signal synchronized with it to the gate line of the display panel.

The scan clock is shifted by periodically swinging between the gate-on and gate-off voltages. In each gate stage, the Q node and the input terminal of the scan clock are coupled to each other through parasitic capacitance, so a ripple voltage is generated at the Q node in synchronization with the periodic swing of the voltage at the input terminal of the scan clock. The voltage of the QB node becomes unstable due to the ripple voltage of the Q node. In other words, if the ripple voltage of the Q node is large, the voltage of the QB node cannot sufficiently rise to the gate-on voltage after the scan signal is output, and an unwanted multi-scan output may occur.

Therefore, this specification was designed to solve the problems mentioned above, and is designed to strengthen the rising characteristics of the QB node voltage by overshooting the voltage of the QB node according to the timing of the ripple voltage at the Q node. Provides a gate driver and an electroluminescent display device including the same.

The gate driver according to this embodiment includes a first circuit unit that outputs a scan clock that periodically swings between a gate-off voltage and a gate-on voltage; a second circuit unit outputting a first high-potential power supply voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage, and a second high-potential power supply voltage fixed to the gate-on voltage; and a gate stage including an input unit that activates the Q node with the second high-potential power supply voltage in a first period, and an inverter unit that activates the QB node with the first high-potential power supply voltage in a second period following the first period. It includes, and the first high-potential power supply voltage is overshooted from the gate-on voltage to the boosting-on voltage in synchronization with rising edges of the scan clock.

An electroluminescent display device according to this embodiment includes a display panel including a plurality of pixels and a plurality of gate lines connected to the pixels; and a gate driver connected to the gate lines. The gate driver includes a first circuit unit that outputs a scan clock that periodically swings between a gate-off voltage and a gate-on voltage; a second circuit unit outputting a first high-potential power supply voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage, and a second high-potential power supply voltage fixed to the gate-on voltage; and a gate stage including an input unit that activates the Q node with the second high-potential power supply voltage in a first period, and an inverter unit that activates the QB node with the first high-potential power supply voltage in a second period following the first period. It includes, and the first high-potential power supply voltage is overshooted from the gate-on voltage to the boosting-on voltage in synchronization with rising edges of the scan clock.

In this embodiment, the high-potential power supply voltage to be applied to the QB node is boosted in AC form according to the swing period of the scan clock. In this embodiment, the rising characteristic of the QB node voltage is strengthened by overshooting the voltage of the QB node from the gate-on voltage according to the generation timing of the Q node ripple voltage due to the swing of the scan clock, resulting in abnormal multi-output. It can be prevented in advance.

The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a diagram showing an electroluminescent display device according to an embodiment of the present specification.
Figure 2 is a diagram schematically showing the configuration of one pixel formed in a display panel.
Figure 3 is a diagram schematically showing the configuration of a gate stage included in the gate driver.
Figure 4 is a diagram specifically showing the configuration of a gate stage included in the gate driver.
FIG. 5 is a comparative example of the present specification and is a diagram showing that the voltage of the QB node does not sufficiently rise to the gate-on voltage due to the ripple voltage of the Q node, resulting in an unwanted multi-scan output.
FIG. 6 is a diagram illustrating, as an embodiment of the present specification, the rising characteristics of the QB node voltage are strengthened by overshooting the voltage of the QB node according to the timing of the ripple voltage occurring at the Q node.
FIG. 7 is a diagram illustrating a first circuit portion of a level shifter that generates a scan clock swinging between a gate-off voltage and a gate-on voltage.
FIG. 8 is a diagram illustrating a second circuit portion of a level shifter that generates a first high-potential power supply voltage that swings between a gate-on voltage and a boosting-on voltage in synchronization with the rising edge of a scan clock.
FIG. 9 is a diagram showing driving timing for the level shifter of FIGS. 7 and 8.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the technical idea of the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present specification is complete, and that the technical idea of the present specification is not limited to the embodiments disclosed below. It is provided to fully inform those skilled in the art of the scope of the invention. The technical idea of this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative. Like reference numerals refer to like elements throughout the specification. Additionally, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

In this specification, the pixel circuit and gate driver formed on the substrate of the display panel may be implemented with an N MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type transistor, but are not limited thereto.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

1 is a diagram showing an electroluminescent display device according to an embodiment of the present specification. FIG. 2 is a diagram schematically showing the configuration of one pixel formed in the display panel of FIG. 1.

Referring to FIG. 1, the electroluminescent display device according to this embodiment may include a display panel 100, a timing controller 110, a data driver 120, and gate drivers 130 and 150.

In the display panel 100, as shown in FIG. 2, pixels (PXL) connected to the data line 14 and the gate line 15 are arranged in a matrix form to form a pixel array. The pixel array includes a plurality of horizontal pixel lines, and on each horizontal pixel line, a plurality of pixels (PXL) that are horizontally adjacent and are commonly connected to the gate line 15 are disposed. Here, the horizontal pixel line is not a physical signal line, but rather a 1-line pixel aggregate implemented by horizontally neighboring pixels (PXL). The pixel array may include a power line that supplies a high-potential pixel voltage (EVDD) to the pixels (PXL). Additionally, the pixels PXL may be supplied with an additional low-potential pixel voltage EVSS.

Each of the pixels PXL includes a light emitting device (OLED) and a pixel driving circuit (PCC) for driving the light emitting device, as shown in FIG. 2 . The pixel driving circuit (PCC) may include a driving element that generates a driving current to be applied to the light emitting element (OLED), a switch circuit connected to the driving element, etc. The switch circuit serves to set and maintain the voltage between the gate and source of the driving element. For this purpose, the switch circuit receives the data voltage (Vdata) through the data line 14, the scan signal (SCAN) through the gate line 15, and supplies the high-potential pixel voltage (EVDD) through the power line. Receives supply and sets the voltage between the gate and source of the driving element. The gate electrode of one switch element included in the switch circuit may be connected to the gate line 15, and the drain electrode of one switch element included in the switch circuit may be connected to the data line.

Pixels PXL may include red pixels, green pixels, blue pixels, and white pixels. Red pixels, green pixels, blue pixels, and white pixels constitute one unit pixel and can implement various colors. The color implemented in a unit pixel may be determined according to the emission ratio of the red pixel, green pixel, blue pixel, and white pixel. Meanwhile, the white pixel may be omitted, and in this case, the unit pixel may be composed of a red pixel, a green pixel, and a blue pixel. Meanwhile, the number of gate lines 15 connected to the pixel PXL may be single or plural.

Referring to FIG. 1, the data driver 120 receives image data (DATA) and a source timing control signal (DDC) from the timing controller 110. The data driver 120 converts the image data (DATA) into a gamma compensation voltage in response to the source timing control signal (DDC) from the timing controller 110 to generate a data voltage (Vdata), and the data voltage (Vdata) is supplied to the data lines 14 of the display panel 100 in accordance with the supply timing of the scan signal SCAN. The data driver 120 may be connected to the data lines 14 of the display panel 100 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process. The data driver 120 may be divided into multiple pieces and integrated.

Referring to FIG. 1, gate drivers 130 and 150 include a level shifter 150 and a gate shift register 130.

The level shifter 150 levels shifts the voltage level of control clocks input from the timing controller 110 and generates a gate timing control signal (GDC) that swings between the gate-on voltage and gate-off voltage based on the level-shifted control clocks. can be created. The gate timing control signal (GDC) can be a start signal and a scan clock. The gate timing control signal (GDC) may further include a carry clock.

The level shifter 150 may generate a first high-potential power supply voltage (GVDD1) that swings between a gate-on voltage and a boosting-on voltage based on level-shifted control clocks. The level shifter 150 may generate a second high potential power supply voltage (GVDD2) fixed to the gate-on voltage.

The level shifter 150 supplies the gate timing control signal (GDC), the first high potential power supply voltage (GVDD1), and the second high potential power supply voltage (GVDD2) to the gate shift register 130.

Referring to Figures 1 and 2, the gate shift register 130 is a gate timing control signal (GDC) input from the level shifter 150, a first high potential power supply voltage (GVDD1), and a second high potential power supply voltage ( It operates according to GVDD2) and generates a scan signal (SCAN) needed to drive the pixel (PXL). Then, the gate shift register 130 supplies the scan signal SCAN to the gate lines 15.

The gate shift register 130 may be formed directly on the substrate of the display panel 100 using a gate driver in panel (GIP) method. The gate shift register 130 may be formed in a non-display area (i.e., bezel area BZ) outside the screen of the display panel 100. In the GIP method, the level shifter 150 may be mounted on a printed circuit board (Printed Circuit Board) 140 together with the timing controller 110.

The gate shift register 130 may be composed of a plurality of gate stages connected to each other in a cascading manner. Among the plurality of gate stages, the first gate stage may start operating according to a start signal. In addition, each of the remaining gate stages other than the first gate stage may start operating according to the output of the preceding gate stage that was operated before it, that is, a carry signal.

The gate shift register 130 is located in the bezel area (BZ) on both opposing sides of the display panel 100, and supplies a scan signal (SCAN) to each gate line in a double feeding method to load each gate line. Signal distortion due to deviation can be minimized.

Referring to FIG. 1, the timing controller 110 can be connected to an external host system through various known interface methods. The timing controller 110 receives image data (DATA) from the host system, corrects the image data (DATA) to compensate for the luminance deviation due to differences in device characteristics of the pixels (PXL), and then transmits the image data (DATA) to the data driver 120. You can.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) from the host system, and receives these timing signals. In addition to generating the source timing control signal (DDC) based on , a plurality of control clocks that are the basis of the gate timing control signal (GDC) can be generated.

Figure 3 is a diagram schematically showing the configuration of a gate stage included in the gate driver.

Referring to FIG. 3, one gate stage (STG) of this embodiment may include a node control unit (NCC) and output units (TU, TD).

The node control unit (NCC) activates the Q node with the second high-potential power supply voltage (GVDD2) in the first period and activates the QB node with the first high-potential power supply voltage (GVDD1) in the second period following the first period. . The node control unit (NCC) deactivates the QB node with the second low-potential power supply voltage (GVSS2) in the first period and deactivates the Q node with the second low-potential power supply voltage (GVSS2) in the second period.

The output units (TU, TD) include a pull-up transistor (TU) and a pull-down transistor (TD). The pull-up transistor TU is turned on according to the voltage of the Q node activated by the second high potential power supply voltage GVDD2 in the first period to apply the scan clock SCCLK of the gate-on voltage to the output node NO. The pull-down transistor TD is turned on according to the voltage of the QB node activated by the first high-potential power supply voltage GVDD1 in the second period to apply the first low-potential power supply voltage GVSS1 to the output node NO.

The pull-up transistor (TU) is turned on in the first period and turned off in the second period. In contrast, the pull-down transistor TD is turned off in the first period and turned on in the second period.

In order to prevent off current flowing in the pull-up transistor (TU) in the second period, it is preferable that a reverse bias is applied between the gate and source of the pull-up transistor (TU). To this end, the first low-potential power supply voltage GVSS1 applied to the source electrode of the pull-up transistor (TU) in the second period is the second low-potential power supply voltage applied to the gate electrode of the pull-up transistor (TU) in the second period. It may be higher than (GVSS2).

Since the input terminal of the scan clock (SCCLK) is coupled to the Q node through the parasitic capacitance (Cx), a ripple voltage is applied to the Q node in synchronization with the periodic swing of the scan clock (SCCLK) between the gate-off voltage and the gate-on voltage. This happens. Due to the ripple voltage of the Q node, the voltage of the QB node does not sufficiently rise to the gate-on voltage in the second period, so an unwanted multi-scan output may occur.

To solve this problem, the first high-potential power supply voltage GVDD1 may be set not to the DC voltage of the gate-on voltage, but to an AC voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage. In other words, the first high-potential power supply voltage GVDD1 is overshooted from the gate-on voltage to the boosting-on voltage in synchronization with the rising edges of the scan clock, so that the QB node voltage can easily rise in the second period.

Figure 4 is a diagram specifically showing the configuration of a gate stage included in the gate driver. FIG. 5 is a comparative example of the present specification and is a diagram showing that the voltage of the QB node does not sufficiently rise to the gate-on voltage due to the ripple voltage of the Q node, resulting in an unwanted multi-scan output. FIG. 6 is a diagram illustrating, as an embodiment of the present specification, the rising characteristics of the QB node voltage are strengthened by overshooting the voltage of the QB node according to the timing of the ripple voltage occurring at the Q node.

Referring to FIGS. 4 to 6 , one gate stage (STG) of this embodiment includes an input unit (BK1), an inverter unit (BK2), and an output unit (BK3).

The input unit BK1 activates the Q node with the second high potential power supply voltage GVDD2 in the first period PED1 and deactivates the Q node with the second low potential power supply voltage GVSS2 in the second period PED2. . The second high-potential power supply voltage (GVDD2) is the DC voltage of the gate-on voltage (Vgh), and the second low-potential power supply voltage (GVSS2) is the DC voltage of the gate-off voltage (Vgl).

The input unit BK1 includes a plurality of transistors T1, T2A, T2B, T3, T4A, and T4B. In the first period (PED1), transistor T1 is turned on by the front-end carry signal (CRY1) to apply the second high potential power supply voltage (GVDD2) to the Q node. Transistors T2A and T2B are connected in series to the Nx node. In the second period (PED2), transistors T2A and T2B are simultaneously turned on by the rear carry signal (CRY2) to apply the second low-potential power supply voltage (GVSS2) to the Q node. Transistors T4A and T4B are connected in series to the Nx node. In the second period (PED2), transistors T4A and T4B are simultaneously turned on by the voltage of the QB node to apply the second low-potential power supply voltage (GVSS2) to the Q node. In the first period (PED1), transistor T3 is turned on by the voltage of the Q node and applies the second high potential power supply voltage (GVDD2) to the Nx node, thereby applying a reverse bias between the gate and source of each of the transistors T2A and T4A. . As a result, the off current generated in each of the transistors T2A and T4A in the first period (PED1) is blocked, and the Q node voltage can stably maintain the second high potential power supply voltage (GVDD2).

The inverter unit (BK2) deactivates the QB node with the second low-potential power supply voltage (GVSS2) in the first period (PED1) and activates the Q node with the first high-potential power supply voltage (GVDD1) in the second period (PED2). I order it. The first high-potential power supply voltage (GVDD1) is an AC voltage that periodically swings between the gate-on voltage (Vgh) and the higher boosting-on voltage (Vgh-B).

The inverter unit BK2 includes a plurality of transistors T5 to T9. In the first period (PED1), transistor T7 is turned on by the voltage of the Q node and connects the Ny node to the third low-potential power supply voltage (GVSS3). In the first period (PED1), the first high-potential power supply voltage (GVDD1) applied to the Ny node through the transistor T6 is discharged to the third low-potential power supply voltage (GVSS3). In the first period (PED1), transistor T5 is turned off by the third low-potential power supply voltage (GVSS3) of the Ny node. In the first period (PED1), transistor T8 is turned on by the Q node voltage and deactivates the QB node by the second low-potential power supply voltage (GVSS1). In the first period (PED1), transistor T9 is turned on by the front-end carry signal (CRY1) and deactivates the QB node with the second low-potential power supply voltage (GVSS1).

In the second period (PED2), transistor T7 is turned off by the Q node voltage of the second low-potential power supply voltage (GVSS2) to break the electrical connection between the Ny node and the third low-potential power supply voltage (GVSS3). In order to block the off-current flowing in the transistor T7 in the second period (PED2), the third low-potential power supply voltage (GVSS3) is preferably set higher than the second low-potential power supply voltage (GVSS2). In this case, a reverse bias is applied between the gate and source of transistor T7 in the second period (PED2), and the first high potential power supply voltage (GVDD1) can be stably maintained at the Ny node. In the second period (PED2), transistor T5 is turned on by the Ny node voltage of the first high-potential power supply voltage (GVDD1) to activate the QB node with the first high-potential power supply voltage (GVDD1).

The output unit (BK3) includes scan output units (TU, TD) that output a scan signal (SCAN), and carry output units (TU1, TD1) that output a carry signal (CRY). By separating the scan output units (TU, TD) and the carry output units (TU1, TD1), the carry signal (CRY) can be prevented from being distorted by the panel load. If the panel load is small, the carry output units (TU1 and TD1) can be omitted. If there is no carry output unit (TU1, TD1), the scan signal (SCAN) can even perform the carry role.

The scan output units (TU, TD) and carry output units (TU1, TD1) share the Q node and QB node.

The scan output units (TU, TD) include a pull-up transistor (TU), a pull-down transistor (TD), and a capacitor (C). The pull-up transistor (TU) is turned on according to the voltage of the Q node activated by the second high potential power supply voltage (GVDD2) in the first period (PED1) and outputs the scan clock (SCCLK) of the gate-on voltage (Vgh) to the scan output node ( NO) is approved. The pull-down transistor (TD) is turned on according to the voltage of the QB node activated by the first high-potential power supply voltage (GVDD1) in the second period (PED2) and supplies the first low-potential power supply voltage (GVSS1) to the scan output node (NO). Authorize. The capacitor (C) is connected between the Q node and the scan output node (NO), so that the Q while the scan clock (SCCLK) of the gate-on voltage (Vgh) is applied to the scan output node (NO) in the first period (PED1) The voltage of the node is bootstrapped from the second high potential power supply voltage (GVDD2) to a higher BST level. As a result, the time for charging the scan output node NO with the scan clock SCCLK of the gate-on voltage Vgh in the first period PED1 can be shortened.

The pull-up transistor (TU) is turned on in the first period (PED1) and turned off in the second period (PED2). In contrast, the pull-down transistor TD is turned off in the first period PED1 and turned on in the second period PED2.

In order to prevent off current flowing through the pull-up transistor TU in the second period PED2, it is preferable that a reverse bias is applied between the gate and source of the pull-up transistor TU. To this end, the first low potential power supply voltage GVSS1 applied to the source electrode of the pull-up transistor TU in the second period PED2 is the second low potential power supply voltage GVSS1 applied to the gate electrode of the pull-up transistor TU in the second period. It may be higher than the potential power supply voltage (GVSS2). As a result, the low output level of the scan signal SCAN may be stabilized in the second period PED2.

The carry output units TU1 and TD1 include a first pull-up transistor TU1, a first pull-down transistor TD1, and a first capacitor C1. The first pull-up transistor (TU1) is turned on according to the voltage of the Q node activated by the second high potential power supply voltage (GVDD2) in the first period (PED1) and outputs a carry clock (CRCLK) of the gate-on voltage (Vgh). Applies to node (NO1). The first pull-down transistor (TD1) is turned on according to the voltage of the QB node activated by the first high-potential power supply voltage (GVDD1) in the second period (PED2) to supply the second low-potential power supply voltage (GVSS2) to the carry output node (NO1). ) is approved.

The first pull-up transistor TU1 is turned on in the first period PED1 and turned off in the second period PED2. In contrast, the first pull-down transistor TD1 is turned off in the first period PED1 and turned on in the second period PED2.

As explained in Figure 3, the input terminal of the scan clock (SCCLK) is coupled to the Q node through a parasitic capacitance, so the scan clock (SCCLK) swings periodically between the gate-off voltage (Vgl) and the gate-on voltage (Vgh). In synchronization with this, a ripple voltage may occur at the Q node. As shown in FIG. 5, when the ripple voltage of the Q node is large, the voltage of the QB node does not rise sufficiently to the gate-on voltage (Vgh) in the second period, so an unwanted multi-scan output may occur.

The above problem occurs when the first high potential power supply voltage (GVDD1) to be charged at the QB node is set to the DC voltage of the gate-on voltage. When the first high-potential power supply voltage (GVDD1) to be charged in the QB node is set to an AC voltage that swings periodically between the gate-on voltage (Vgh) and the higher boosting-on voltage (Vgh-B), the above problem occurs. It can be resolved. When the first high potential power supply voltage (GVDD1) is overshooted from the gate-on voltage (Vgh) to the boosting-on voltage (Vgh-B) in synchronization with the rising edges (RE) of the scan clock (SCCLK), QB in the second period The rising characteristics of the node voltage can be improved.

FIG. 7 is a diagram illustrating the first circuit unit 150A of the level shifter 150 that generates a scan clock (SCCLK) swinging between the gate-off voltage (Vgl) and the gate-on voltage (Vgh). 8 shows a level shifter that generates a first high-potential power supply voltage (GVDD1) swinging between the gate-on voltage (Vgh) and the boosting-on voltage (Vgh-B) in synchronization with the rising edge (RE) of the scan clock (SCCLK). This is a diagram showing the second circuit portion 150B of 150. FIG. 9 is a diagram showing the driving timing for the level shifter 150 of FIGS. 7 and 8.

Referring to FIGS. 7 and 9, the first circuit unit 150A of the level shifter 150 generates a gate-off voltage (Vgl) and a gate-on voltage based on the first control clock (GCLK) and the second control clock (MCLK). Generates a scan clock (SCCLK) that swings periodically between (Vgh).

The first circuit unit 150A synchronizes the rising edge (RE) of the scan clock (SCCLK), which rises from the gate-off voltage (Vgl) to the gate-on voltage (Vgh), with the rising edge (RE) of the first control clock (GCLK). And, the falling edge FE of the scan clock SCCLK, which falls from the gate-on voltage Vgh to the gate-off voltage Vgh, is synchronized with the falling edge FE of the second control clock MCLK.

Referring to FIGS. 8 and 9, the second circuit unit 150B of the level shifter 150 generates a gate-on voltage (Vgh) and a boosting-on voltage based on the first control clock (GCLK) and the third control clock (MCLK2). A first high-potential power supply voltage (GVDD1) that swings periodically between (Vgh-B) is generated.

The second circuit unit 150B uses the rising edge (RE) of the first high-potential power supply voltage (GVDD1), which rises from the gate-on voltage (Vgh) to the boosting-on voltage (Vgh-B), to the rising edge (RE) of the first control clock (GCLK). The falling edge (FE) of the first high-potential power supply voltage (GVDD1), which is synchronized to the edge (RE) and falls from the boosting-on voltage (Vgh-B) to the gate-on voltage (Vgh), is connected to the third control clock (MCLK2). Synchronize to falling edge (FE).

To this end, the falling edge (FE) of the third control clock (MCLK2) lags behind the rising edge (RE) of the first control clock (GCLK) in time, and the falling edge (FE) of the second control clock (MCLK) It is ahead in time compared to .

Referring to FIG. 9, the length of time for which the first high-potential power supply voltage (GVDD1) is maintained at the boosting-on voltage (Vgh-B) is the rising edge (RE) of the first control clock (GCLK) and the third control clock. It is determined by the time interval between the falling edges (FE) of (MCLK2).

In addition, the width (PW1) of the first pulse at which the first high-potential power supply voltage (GVDD1) is maintained at the boosting-on voltage (Vgh-B) is the second pulse at which the scan clock (SCCLK) is maintained at the gate-on voltage (Vgh-B). It is preferable that it is narrower than the pulse width (PW2). In particular, the width (PW1) of the first pulse may be designed to be within the width (PW2) of the second pulse, but may be designed to increase in proportion to the average size of the Q node ripple voltage. For example, the width (PW1) of the first pulse may be designed to be a first value when the average magnitude of the Q node ripple voltage is small, and a second value greater than the first value when the average magnitude of the Q node ripple voltage is large. It can be designed with 2 values. In this way, the rising characteristics of the QB node voltage can be improved regardless of the average size of the Q node ripple voltage in the second period.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 110: timing controller
120: data driver 130: gate shift register
150: Level Shifter

Claims (16)

a first circuit unit outputting a scan clock that periodically swings between a gate-off voltage and a gate-on voltage;
a second circuit unit outputting a first high-potential power supply voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage, and a second high-potential power supply voltage fixed to the gate-on voltage; and
A gate stage having an input unit that activates the Q node with the second high potential power supply voltage in a first period and an inverter unit that activates the QB node with the first high potential power supply voltage in a second period following the first period. Contains,
The gate driver wherein the first high-potential power supply voltage overshoots from the gate-on voltage to the boosting-on voltage in synchronization with rising edges of the scan clock. According to claim 1,
In the second period, a ripple voltage occurs at the Q node due to a swing of the scan clock,
In the second period, the voltage of the QB node is overshooted from the gate-on voltage to the boosting-on voltage according to the timing at which the ripple voltage of the Q node occurs. According to claim 1,
The first circuit unit synchronizes the rising edge of the scan clock rising from the gate-off voltage to the gate-on voltage with the rising edge of the first control clock, and the scan clock falling from the gate-on voltage to the gate-off voltage synchronize the falling edge of the clock to the falling edge of the second control clock;
The second circuit unit synchronizes the rising edge of the first high-potential power supply voltage, which rises from the gate-on voltage to the boosting-on voltage, with the rising edge of the first control clock, and increases the gate-on voltage from the boosting-on voltage to the rising edge of the first control clock. A gate driver that synchronizes the falling edge of the first high potential power supply voltage falling to the falling edge of the third control clock. According to claim 3,
The gate driver wherein the falling edge of the third control clock is temporally behind the rising edge of the first control clock and is temporally ahead of the falling edge of the second control clock. According to claim 3,
The length of time for which the first high-potential power supply voltage is maintained at the boosting-on voltage is determined by the interval between the rising edge of the first control clock and the falling edge of the third control clock. According to claim 3,
The width of the first pulse in which the first high-potential power supply voltage is maintained at the boosting-on voltage is narrower than the width of the second pulse in which the scan clock is maintained at the gate-on voltage. According to claim 1,
The gate stage is,
a pull-up transistor that applies a scan clock of the gate-on voltage to an output node according to the voltage of the Q node activated by the second high-potential power supply voltage in the first period, and the first high-potential power supply in the second period; A gate driver further comprising an output unit having a pull-down transistor that applies a first low-potential power supply voltage higher than the gate-off voltage to the output node according to the voltage of the QB node activated with voltage. According to claim 7,
In the first period, the QB node is deactivated by a second low-potential power supply voltage equal to the gate-off voltage,
In the second period, the Q node is deactivated by the second low-potential power supply voltage,
In the second period, the second low-potential power supply voltage is applied to the gate electrode of the pull-up transistor, and the first low-potential power supply voltage higher than the second low-potential power supply voltage is applied to the source electrode of the pull-up transistor. gate driver. A display panel including a plurality of pixels and a plurality of gate lines connected to the pixels; and
Includes a gate driver connected to the gate lines,
The gate driver is,
a first circuit unit outputting a scan clock that periodically swings between a gate-off voltage and a gate-on voltage;
a second circuit unit outputting a first high-potential power supply voltage that periodically swings between the gate-on voltage and a higher boosting-on voltage, and a second high-potential power supply voltage fixed to the gate-on voltage; and
A gate stage having an input unit that activates the Q node with the second high potential power supply voltage in a first period and an inverter unit that activates the QB node with the first high potential power supply voltage in a second period following the first period. Contains,
The first high-potential power supply voltage is overshooted from the gate-on voltage to the boosting-on voltage in synchronization with rising edges of the scan clock. According to clause 9,
In the second period, a ripple voltage occurs at the Q node due to a swing of the scan clock,
In the second period, the voltage of the QB node is overshooted from the gate-on voltage to the boosting-on voltage according to the timing at which the ripple voltage of the Q node occurs. According to clause 9,
The first circuit unit synchronizes the rising edge of the scan clock rising from the gate-off voltage to the gate-on voltage with the rising edge of the first control clock, and the scan clock falling from the gate-on voltage to the gate-off voltage synchronize the falling edge of the clock to the falling edge of the second control clock;
The second circuit unit synchronizes the rising edge of the first high-potential power supply voltage, which rises from the gate-on voltage to the boosting-on voltage, with the rising edge of the first control clock, and increases the gate-on voltage from the boosting-on voltage to the rising edge of the first control clock. An electroluminescent display device that synchronizes the falling edge of the first high potential power supply voltage falling to the falling edge of the third control clock. According to claim 11,
The falling edge of the third control clock is temporally behind the rising edge of the first control clock and is temporally ahead of the falling edge of the second control clock. According to claim 11,
The length of time for which the first high-potential power supply voltage is maintained at the boosting-on voltage is determined by the interval between the rising edge of the first control clock and the falling edge of the third control clock. According to claim 11,
The width of the first pulse in which the first high-potential power supply voltage is maintained at the boosting-on voltage is narrower than the width of the second pulse in which the scan clock is maintained at the gate-on voltage. According to claim 10,
The gate stage is,
a pull-up transistor that applies a scan clock of the gate-on voltage to an output node according to the voltage of the Q node activated by the second high-potential power supply voltage in the first period, and the first high-potential power supply in the second period; The electroluminescent display device further includes an output unit having a pull-down transistor that applies a first low-potential power supply voltage higher than the gate-off voltage to the output node according to the voltage of the QB node activated with voltage. According to claim 15,
In the first period, the QB node is deactivated by a second low-potential power supply voltage equal to the gate-off voltage,
In the second period, the Q node is inactivated by the second low-potential power supply voltage,
In the second period, the second low-potential power supply voltage is applied to the gate electrode of the pull-up transistor, and the first low-potential power supply voltage higher than the second low-potential power supply voltage is applied to the source electrode of the pull-up transistor. Electroluminescent display.