KR20240104212A - Plasma processing apparatus and plasma processing method - Google Patents

Abstract

A plasma processing device includes a sample stand having a mounting surface on which a semiconductor wafer is placed, a dielectric ring having a ring-shaped thin film electrode disposed surrounding the sample stand, and a dielectric ring covering the thin film electrode. Equipped with a susceptor ring, the thin film electrode includes a first part positioned lower than the back surface of the semiconductor wafer, a second part positioned higher than the main surface of the semiconductor wafer, and a third part connecting the first part and the second part. Including, when viewed in plan view, the first portion of the thin film electrode has an overlap region that overlaps the semiconductor wafer.

Description

Plasma processing device and plasma processing method {PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD}

The present invention relates to a plasma processing device and a plasma processing method, and particularly to a plasma processing device and a plasma processing method suitable for processing workpieces such as semiconductor wafers.

In the semiconductor manufacturing process, dry etching using plasma is generally performed. Various types of plasma processing devices for dry etching are used.

Generally, a plasma processing device includes a vacuum processing chamber, a gas supply device connected to the vacuum processing chamber, a vacuum exhaust system that maintains the pressure in the vacuum processing chamber at a desired value, an electrode for placing a semiconductor wafer as a processing material, and a plasma in the vacuum processing chamber. It consists of a plasma generating means to generate . An etching process is performed on the semiconductor wafer held on the wafer placement electrode by converting the processing gas supplied into the vacuum processing chamber from the shower plate or the like by the plasma generating means into a plasma state.

Recently, with the improvement of the degree of integration of semiconductor devices, circuit structures are becoming more refined, and therefore, there is a demand for microfabrication, that is, improvement in processing precision. Additionally, in order to improve the acquisition rate of non-defective semiconductor devices per sheet of semiconductor wafer, there is a demand for a plasma processing device capable of manufacturing non-defective semiconductor devices even to the peripheral portion of the semiconductor wafer.

In order to suppress deterioration of performance at the peripheral portion of the semiconductor wafer, it is important to reduce the concentration of the electric field in the outer peripheral region of the semiconductor wafer placed on the sample stand. For example, in the case of etching processing, it is necessary to suppress the processing speed (etching rate) from rapidly increasing at the periphery of the semiconductor wafer. To achieve this, it is necessary to make the thickness of the sheath formed on the top of the semiconductor wafer during processing of the semiconductor wafer uniform from the center of the semiconductor wafer to the outer peripheral region.

In Japanese Patent Application Laid-Open No. 2020-43100 (Patent Document 1), a conductive thin film electrode is provided on a part of an insulating ring arranged around the outer periphery of a sample stand on which a semiconductor wafer is placed, and a first high-frequency power is applied to the sample stand. , a technology for improving the uniformity of plasma processing up to the periphery of a semiconductor wafer is disclosed by applying a second high-frequency power to a thin film electrode.

In Japanese Patent Application Laid-Open No. 2010-283028 (Patent Document 2), a sample stand on which a semiconductor wafer is placed is provided with a dielectric ring arranged around the outer periphery and a conductive ring provided thereon, and the conductive ring is an outer ring having an upper surface higher than the wafer. A technology is disclosed that integrates an inner ring with a lower upper surface and controls the ion incidence angle by applying a direct current voltage to the conductive ring, thereby improving the balance of reduction of deposits and treatment results.

Japanese Patent Laid-Open No. 2020-43100 Japanese Patent Laid-Open No. 2010-283028

Patent Document 1 states that an insulating ring formed with a thin film electrode for applying high-frequency power is a susceptor ring of a dielectric system in order to suppress electrical interference with high-frequency power of other systems applied to the sample stand. It has a structure in which everything other than the tooth surface is covered. Therefore, the inner circumferential edge of the thin film electrode cannot be brought close to the edge of the wafer, and additional studies are required to achieve desirable electric field control around the edge of the wafer.

Additionally, in Patent Document 2, since there is no protective ring covering the periphery of the conductive ring, the temperature of the conductive ring increases when the conductive ring comes into contact with plasma. It is necessary to examine the fact that the reliability of the device is impaired due to this effect, and the unevenness of the processing shape occurs as a result of uneven temperature of the wafer to be processed due to the influence of heat generation.

In other words, there is a need for a plasma processing method that improves the reliability of plasma processing devices or improves the yield of semiconductor wafers to be processed.

Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

The plasma processing device in one embodiment is a sample table disposed in a processing chamber in which plasma is formed inside the vacuum processing device and having a placement surface on which a wafer to be processed is placed, in the central portion of the upper portion. A sample having a cylindrical convex portion disposed and having the mounting surface on the upper surface, a concave portion disposed to surround the convex portion in a ring shape and constituting an outer peripheral portion of the upper portion, and a high-frequency electrode to which high-frequency power is supplied during processing of the wafer. A ring-shaped thin film electrode arranged in the concave part surrounding the convex part and supplied with a high frequency power of a different magnitude than that supplied to the high frequency electrode during processing of the wafer, and covering the thin film electrode above the base. A susceptor ring having a portion of the dielectric material disposed, the thin film electrode comprising: a first portion constituting an inner peripheral end and having a flat portion positioned lower than the mounting surface; the first portion and an outer peripheral side of the wafer; It includes a flat second part disposed in and positioned higher than the upper surface of the wafer, and a third part forming a step-shaped part by connecting an outer periphery of the first part and an inner periphery of the second part, The susceptoring includes an inner peripheral end that covers the first part of the thin film electrode and is located below the outer peripheral end of the wafer when viewed from the top with the wafer placed on the mounting surface, and an upper surface that covers the second part. It is provided with a flat outer peripheral portion and a portion that integrally connects the inner peripheral portion and the outer peripheral portion and has an inclined upper surface that increases toward the outer periphery and covers the second portion.

In addition, the plasma processing method in one embodiment involves placing a wafer to be treated on a placement surface of the upper part of a sample table disposed in a processing chamber inside a vacuum vessel, and processing the wafer using plasma formed in the processing chamber. A plasma processing method, wherein the sample stage includes a cylindrical convex portion disposed in the central portion of the upper surface and having the mounting surface on the upper surface, a concave portion arranged to surround the convex portion in a ring shape and constitute an outer peripheral portion of the upper portion, and the wafer. a high-frequency electrode to which high-frequency power is supplied during processing, a ring-shaped thin film electrode disposed in the concave portion surrounding the convex portion, and a susceptor ring having a portion of a dielectric material disposed above the thin film electrode to cover it. And, the thin film electrode includes a first part that constitutes an inner peripheral end and is located lower than the placing surface and has a flat portion, and this first portion and a flat second portion disposed on the outer peripheral side of the wafer and located higher than the upper surface of the wafer. It includes two parts and a third part connecting the outer peripheral part of the first part and the inner peripheral part of the second part to form a step-shaped part, wherein the susceptor ring connects the first part of the thin film electrode. An inner peripheral end located below the outer peripheral end of the wafer in a planar view with the wafer placed on the placing surface, an outer peripheral portion with a flat upper surface covering the second portion, and a space between these inner peripheral ends and the outer peripheral portion. is integrally connected, has an inclined upper surface that increases toward the outer periphery, and has a part covering the second part, and a high frequency power of a different magnitude from that supplied to the high frequency electrode is supplied during processing of the wafer.

According to one embodiment, the reliability of the plasma processing device can be improved. Additionally, the yield of the object to be treated in plasma treatment can be improved.

1 is a cross-sectional view schematically showing the outline of the configuration of a plasma processing device of one embodiment.
FIG. 2 is a cross-sectional view showing a peripheral portion of an electrode for wafer placement in a plasma processing apparatus of one embodiment.
Fig. 3 is a plan view showing electrodes for placing wafers in a plasma processing device of one embodiment.
Figure 4 is a cross-sectional view taken along line XX in Figure 3.
Fig. 5 is a cross-sectional view showing the peripheral portion of the wafer placement electrode of the plasma processing apparatus of Modification Example 1.
Figure 6 is a cross-sectional view schematically showing the outline of the configuration of the plasma processing device of Modification Example 2.

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all drawings for explaining the embodiment, members having the same function are assigned the same reference numerals, and descriptions of repetition thereof are omitted. In addition, in the following embodiments, explanation of the same or similar parts will not be repeated in principle, unless particularly necessary.

(Embodiment)

<Plasma processing device>

Hereinafter, the plasma processing device of this embodiment will be described using FIGS. 1 to 4. 1 is a cross-sectional view schematically showing the outline of the configuration of the plasma processing apparatus of the present embodiment, FIG. 2 is a cross-sectional view showing the peripheral portion of the wafer placement electrode of the plasma processing apparatus of the present embodiment, and FIG. 3 is a plasma processing apparatus of the present embodiment. FIG. 4 is a plan view showing electrodes for placing wafers in a processing device, and FIG. 4 is a cross-sectional view taken along line X-X in FIG. 3 .

FIG. 1 shows a plasma etching device 100, which is an example of a plasma processing device. This plasma etching device 100 uses the electric field of a microwave as an electric field to form plasma, generates ECR (Electron Cyclotron Resonance) of the electric field and magnetic field of the microwave to form plasma, and uses the plasma to form a semiconductor wafer. A sample of the shape of the substrate is subjected to an etching treatment.

The plasma etching device 100 has a vacuum vessel 101 equipped therein with a processing chamber 104 in which plasma is formed. In the processing chamber 104, the top of which has a cylindrical shape, a disc-shaped dielectric window 103 (for example, made of quartz) is placed as a cover member and forms a part of the vacuum container 101. A sealing member such as an O-ring is disposed between the cylindrical vacuum container 101 and the dielectric window 103 to ensure airtightness inside the vacuum container 101 or the processing chamber 104.

In addition, a vacuum exhaust port 110 leading to the processing chamber 104 is disposed at the bottom of the vacuum container 101, and is in communication with a vacuum exhaust device (not shown) disposed and connected to the bottom of the vacuum container 101. there is. Additionally, below the dielectric window 103, a shower plate 102 forming the circular ceiling surface of the processing chamber 104 is provided. The shower plate 102 has a disk shape with a plurality of gas introduction holes 102a disposed through the central portion, and gas for etching treatment is introduced into the processing chamber 104 through the gas introduction holes 102a. . The shower plate 102 is made of a dielectric material such as quartz.

Above the vacuum container 101, an electric field/magnetic field forming unit 160 is disposed to form an electric field and a magnetic field for generating the plasma 116. The electric field/magnetic field forming unit 160 includes a waveguide 105 and an electric field generation power source 106, and the high-frequency electric field oscillated from the electric field generation power source 106 is transmitted to the inside of the waveguide 105. It is introduced into the processing chamber 104. As the frequency of the electric field, for example, a microwave of 2.45 GHz is used.

Magnetic field generating coils 107 are disposed around the lower end of the waveguide 105 and around the vacuum container 101. The magnetic field generating coil 107 is composed of an electromagnet and a yoke that form a magnetic field by supplying direct current.

With the gas for processing introduced into the processing chamber 104 through the gas introduction hole 102a of the shower plate 102, the electric field of the microwave oscillated from the electric field generation power source 106 passes through the inside of the waveguide 105. It propagates, passes through the dielectric window 103 and the shower plate 102, and is supplied to the processing chamber 104 from top to bottom. In addition, the magnetic field generated by the direct current supplied to the magnetic field generating coil 107 is supplied into the processing chamber 104 and interacts with the electric field of microwaves, generating ECR (Electron Cyclotron Resonance). By ECR, atoms or molecules of the processing gas are excited, dissociated, or ionized, and a high-density plasma 116 is generated in the processing chamber 104.

An electrode 120 for wafer placement is disposed below the space where the plasma 116 is formed. The wafer placement electrode 120 has a cylindrical protrusion (convex shape) portion whose upper central portion is higher than the outer peripheral side, and a semiconductor wafer (hereinafter referred to as a sample (processing target)) on the upper surface of the convex portion. It is provided with a placement surface 120a on which 109 (simply referred to as a wafer) is placed. The mounting surface 120a is arranged to face the shower plate 102 or the dielectric window 103.

As shown in FIG. 2, the wafer placement electrode 120 includes an electrode base 108, a dielectric film 140 provided on the electrode base 108, and an insulating plate 150 provided below the electrode base 108. and a ground plate 151, a dielectric ring 139, and a susceptor ring 113.

The electrode base material 108 is provided with a convex portion (protrusion) 108p and a concave portion (depressed portion) 108d. In plan view, the circular convex portion 108p is located in the central portion of the electrode base 108, and a ring-shaped concave portion 108d is located around it. The convex portion 108p has an upper surface 108a that is circular in plan view, and the upper surface 108a is covered with a dielectric film 140. Then, the dielectric film 140 has a placement surface 120a, and the semiconductor wafer 109 is placed on the placement surface 120a. The placement surface 120a has a circular shape in plan view, its radius is the same as the radius of the upper surface 108a, and the centers of both circular shapes overlap each other.

Inside the dielectric film 140, a conductor film 111, which is a film of a plurality of conductive systems, is disposed. As shown in FIG. 1 , the conductor film 111 is connected to a direct current power source 126 through a high-frequency filter 125 . When direct current power is supplied to the conductor film 111, the semiconductor wafer 109 is adsorbed to the placement surface 120a through the dielectric film 140 on the conductor film 111. The conductor film 111 is an electrode for electrostatic adsorption. For convenience, the convex portion (protrusion) 108p of the electrode base 108 and the dielectric film 140 including the conductive film 111 are called a sample stage ST.

The electrode base material 108 is connected to the high-frequency power source 124 through the branch box 127 and the matching device 129. These high-frequency power sources 124 and matching devices 129 are arranged closer than the distance between the high-frequency filter 125 and the conductive film 111. Additionally, the high-frequency power supply 124 is connected to ground 112.

During processing of the semiconductor wafer 109, high-frequency power of a predetermined frequency is supplied from the high-frequency power source 124 to the electrode base material 108 (i.e., sample stand ST). A bias potential having a distribution depending on the difference between the potential of the plasma 116 and the potential of the electrode base 108 is formed above the semiconductor wafer 109 adsorbed and held on the mounting surface 120a through the dielectric film 140. do.

Inside the electrode base 108, in order to cool the wafer placement electrode 120, multiple coolant passages are arranged in a spiral or concentric shape around the central axis in the vertical direction of the electrode base 108 ( 152) is provided. The inlet and outlet of the wafer placement electrode 120 are connected by a pipe to a temperature controller that has a refrigeration cycle (not shown) and adjusts the coolant to a temperature within a predetermined range by heat transfer, and has a coolant flow path 152. The refrigerant whose temperature has changed due to heat exchange flows out of the outlet, passes through the pipe inside the temperature controller, reaches a predetermined temperature range, and is then supplied to the refrigerant passage 152 in the electrode base 108 for circulation.

A ring-shaped dielectric ring 139 surrounding the convex portion 108p is placed in the concave portion 108d of the electrode base 108, and a susceptor ring 113 is placed on the dielectric ring 139. The dielectric ring 139 and the susceptor ring 113 are made of a dielectric material such as ceramics such as quartz or alumina. Since the side surface of the electrode base 108 and the bottom of the concave portion 108b are covered with at least the dielectric ring 139 or the susceptor ring 113, the electrode base 108 is prevented from being damaged by plasma. can do. In addition, the surface of the dielectric ring 139 in contact with the susceptor ring 113 is made of a rough surface with a surface roughness Ra of 1.0 or more, for example. In this way, heat transfer from the susceptor ring 113, which becomes high temperature due to contact with plasma, to the dielectric ring 139 is suppressed.

The dielectric ring 139 is composed of a dielectric ring 139a and a thin film electrode 139b, and the thin film electrode 139b is formed on the step-shaped upper surface of the dielectric ring 139a. The thin film electrode 139b is connected to the branch box 127 through the load impedance variable box 130. That is, the electrode base 108 of the sample stand ST on which the semiconductor wafer 109 is placed and the thin film electrode 139b of the dielectric ring 139 are connected to the high frequency power supply 124, which is a single power supply, and the high frequency power supply 124 is connected to the high frequency power supply 124. High-frequency power is supplied from the power source 124 to the electrode base 108 and the thin film electrode 139b.

The wafer placement electrode 120 includes a disk-shaped insulating plate 150 disposed in contact with the lower surface of the electrode base 108, and a disk-shaped conductive material disposed in contact with the lower surface of the insulating plate 150. It is a member of and also has a ground plate 151 at ground potential.

As shown in FIG. 1, a power source 106 for electric field generation, a magnetic field generation coil 107, a high frequency power source 124, a high frequency filter 125, a direct current power source 126, a branch box 127, and a matching device 129. ), the load impedance variable box 130 is communicatively connected to the controller 170 by wire or wirelessly.

Using the top view of FIG. 3 and the cross-sectional view of FIG. 4, the placement surface 120a of the sample stage ST, the semiconductor wafer 109, and the thin film electrode 139b will be explained. In addition, as shown in FIG. 4, the semiconductor wafer 109 has a main surface 109a on which plasma processing is performed, a back surface 109b in contact with the placement surface 120a, and an end portion that is an arc of the main surface 109a ( 109e).

As shown in FIG. 3, the placement surface 120a has a circular shape with a radius R1 from the center OS. The ring-shaped thin film electrode 139b has an inner peripheral end 139bie of a circular shape with a radius R3 from the center OS and an outer peripheral end 139boe of a circular shape with a radius R4 from the center OS. Additionally, the main surface 109a (in other words, the end portion 109e) of the semiconductor wafer 109 has a circular shape with a radius R2 from the center OU. In addition, the center OU may deviate from the center OS due to “alignment misalignment” when the semiconductor wafer 109 is mounted on the placement surface 120a, but FIG. 3 shows a case where it coincides. Even if there is “misalignment”, plasma treatment is performed if it is within the allowable range. The radius R2 of the main surface 109a of the semiconductor wafer 109 is larger than the radius R1 of the placement surface 120a (R2>R1). Additionally, the radius R4 of the outer peripheral end 139boe of the thin film electrode 139b is larger than the radius R3 of the inner peripheral end 139bie (R4>R3). A characteristic point of this embodiment is that the radius R3 of the inner peripheral edge 139bie of the thin film electrode 139b is smaller than the radius R2 of the edge 109e of the semiconductor wafer 109 (R3<R2). That is, in plan view, the thin film electrode 139b and the semiconductor wafer 109 have an “overlapping area (hatched area in FIG. 3).” And, this “overlapping area” extends over the entire arc-shaped end portion 109e of the semiconductor wafer 109. For example, even when the above-mentioned “misalignment” occurs and the center OU deviates from the center OS, the “overlapping area” is secured over the entire arc-shaped end 109e of the semiconductor wafer 109.

As shown in Fig. 4, the upper surface of the dielectric ring 139a has a first surface 139a1, a third surface 139a3, and a second surface 139a2 arranged in a step shape. The first surface 139a1 and the second surface 139a2 are horizontal surfaces parallel to the main surface 109a or the placement surface 120a of the semiconductor wafer 109, and the third surface 139a3 is the first surface 139a1. ) and the second surface 139a2, and is a surface perpendicular to the main surface 109a or the placement surface 120a of the semiconductor wafer 109. Additionally, a thin film electrode 139b is provided on the upper surface of the dielectric ring 139a. Additionally, an insulating film may be provided on the upper surface of the dielectric ring 139a, and a thin film electrode 139b may be formed thereon.

The thin film electrode 139b is made of a conductive film such as a tungsten thermal spray film. The ring-shaped thin film electrode 139b has a ring width extending from the inner peripheral end 139bie to the outer peripheral end 139boe, and has a first part 139b1, a third part 139b3, and a second part 139b2 in the width direction. has The first part 139b1, the third part 139b3, and the second part 139b2 are the first surface 139a1, the third surface 139a3, and the second surface of the upper surface of the dielectric ring 139a, respectively. It is formed corresponding to (139a2). Accordingly, the first portion 139b1 and the second portion 139b2 are horizontal surfaces parallel to the main surface 109a or the placement surface 120a of the semiconductor wafer 109, and the third portion 139b3 is the first portion. It is a vertical plane connecting (139b1) and the second part (139b2). In addition, the entire first portion 139b1 is located lower than the back surface 109b of the semiconductor wafer 109 in the vertical direction, and the inner circumferential edge 139bie is located below the semiconductor wafer 109 and is positioned below the semiconductor wafer 109. It overlaps with the wafer 109. The first portion 139b1 is disposed at a distance A in the vertical direction from the back surface 109b of the semiconductor wafer 109, and has an “overlapping area” between it and the semiconductor wafer 109 when viewed from the top. . The entire second portion 139b2 is located higher than the main surface 109a of the semiconductor wafer 109. Additionally, the third portion 139b3 is spaced apart from the end portion 109e of the semiconductor wafer 109 by a distance B in the horizontal direction. A characteristic of this embodiment is that distance A is smaller than distance B. The horizontal direction is a direction perpendicular to the vertical direction and is parallel to the placement surface 120a or the main surface 109a of the semiconductor wafer 109.

In addition, as shown in FIG. 2, the first part 139b1, the third part 139b3, and the second part 139b2 of the thin film electrode 139b have their surfaces (upper surfaces) on the susceptor ring 113. covered by And, the susceptor ring 113 has a horizontal surface higher than the main surface 109a of the semiconductor wafer 109 above the second portion 139b2.

<Plasma processing method>

Next, a plasma processing method using the above-described plasma etching device 100 will be described.

First, prepare the plasma etching device 100 described above.

Next is the loading process of the semiconductor wafer 109. A vacuum transfer chamber decompressed to the same pressure as the processing chamber 104 is connected to the side wall of the vacuum vessel 101. The semiconductor wafer 109 is placed on the tip of an arm of a wafer transfer robot disposed in the vacuum transfer chamber and brought into the processing chamber 104. Next, the semiconductor wafer 109 is placed on the placement surface 120a and held by electrostatic adsorption on the sample stage ST.

Next is the etching gas introduction process. After the transfer robot leaves the vacuum transfer chamber, the inside of the processing chamber 104 is sealed. In this state, gas for etching processing is supplied into the processing chamber 104. The introduced gas is introduced into the processing chamber 104 through the gas introduction hole 102a of the shower plate 102. Inside the processing chamber 104 , internal gases or particles are exhausted through the vacuum exhaust port 110 by the operation of a vacuum exhaust device connected to the vacuum exhaust port 110 . According to the balance of the amount of gas supplied from the gas introduction hole 102a of the shower plate 102 and the amount of gas discharged from the vacuum exhaust port 110, the pressure in the processing chamber 104 is adjusted to a predetermined pressure suitable for processing the semiconductor wafer 109. do.

Next is the plasma etching (plasma treatment) process. Although the details are omitted, after adjusting the temperature of the semiconductor wafer 109 as necessary, microwave electric and magnetic fields are supplied into the processing chamber 104 to generate plasma 116 using gas. When the plasma 116 is formed, high frequency (RF) power is supplied to the electrode base 108 from the high frequency power source 124, and a bias potential is formed above the main surface 109a of the semiconductor wafer 109 to generate plasma 116. ), charged particles such as ions in the plasma 116 are attracted to the main surface 109a of the semiconductor wafer 109 according to the potential difference between the potential and the potential of ). Additionally, charged particles collide with the surface of the film layer to be processed previously disposed on the main surface 109a of the semiconductor wafer 109, and etching is performed. In addition, as explained in FIGS. 2 to 4, the thin film electrode 139b provided on the dielectric ring 139 includes a matching circuit 129, a branch box 127, and a load impedance variable box 130 from the high frequency power source 124. Radio frequency (RF) power is supplied via ). Additionally, during the etching process, processing gas introduced into the processing chamber 104 and particles of reaction products generated during processing are exhausted from the vacuum exhaust port 110.

Next is the unloading process of the semiconductor wafer 109. The semiconductor wafer 109 on which the etching process has been completed is carried out of the processing chamber 104 while being supported by the tip of the arm of the above-described transport robot.

<Features of this embodiment>

The plasma processing device of this embodiment uses a single high-frequency power source 124 to connect the electrode base 108 of the sample stage ST and the thin film electrode 139b provided on the dielectric ring 139 during processing of the semiconductor wafer 109. ) supplies high-frequency power from The high-frequency power output from the high-frequency power source 124 is transmitted through the load impedance variable box 130 disposed thereon on the power supply path electrically connecting the branch box 127 and the thin film electrode 139b to the susceptor ring ( It is supplied to the thin film electrode 139b disposed inside 113). At this time, the impedance on the power supply path in the load impedance variable box 130 is adjusted to a value within a desirable range, so that the branch box ( The impedance value for high-frequency power from 127) to the periphery of the semiconductor wafer 109 through the electrode base 108 becomes relatively low. As a result, high-frequency power is effectively supplied to the peripheral and outer regions of the semiconductor wafer 109, the concentration of electric fields in the peripheral and outer regions of the semiconductor wafer 109 is alleviated, and the bias potential above these regions is reduced. The height distribution of the equipotential surface can be made uniform. Therefore, the reliability of the plasma processing device can be improved and the yield of plasma processing of the semiconductor wafer 109 can be improved.

In addition, the thin film electrode 139b has a first part 139b1 positioned lower than the back surface 109b of the semiconductor wafer 109, and a second part 139b2 positioned higher than the main surface 109a of the semiconductor wafer 109. ) and a third part 139b3 connecting the first part 139b1 and the second part 139b2. And, in plan view, the first portion 139b1 has an “overlapping area” that overlaps the semiconductor wafer 109. In addition, the first part 139b1 is arranged at a distance A in the vertical direction from the back surface 109b, and the third part 139b3 is arranged at a distance B in the horizontal direction from the end 109e of the semiconductor wafer 109. They are placed as far apart as possible, and distance A is smaller than distance B.

The cis potential distribution in the outer peripheral region of the semiconductor wafer 109 obtained by supplying high-frequency power to the thin film electrode 139b is mainly formed by the first portion 139b1 and the second portion 139b2. This potential distribution can increase the electric field strength by bringing the first part 139b1 and the second part 139b2 closer to the semiconductor wafer 109, making it possible to expand the control area of the cis potential. However, if the third portion 139b3 is brought too close to the semiconductor wafer 109, a sharp cis potential distribution follows the shape of the susceptor ring 113 near the end 109e of the semiconductor wafer 109, It is unsuitable as a control station. On the other hand, when the first portion 139b1 is brought close to the back surface 109b of the semiconductor wafer 109, the cis potential distribution only in the vicinity of the end portion 109e of the semiconductor wafer 109 is affected, and the controllability is improved by the third portion. The result is better compared to the case where the portion 139b3 is brought too close to each other. From the above, in order to provide a desirable cis potential control region, it is preferable that the distance A is smaller than the distance B (A<B).

In addition, the upper surface of the dielectric ring 139 including the thin film electrode 139b is covered by the dielectric susceptor ring 113 and does not contact the plasma 116, so excessive temperature rise can be suppressed. there is. In addition, since the surface of the dielectric ring 139 in contact with the susceptor ring 113 is composed of a rough surface (for example, surface roughness Ra is 1.0 or more), the susceptor ring 113 becomes high temperature when in contact with plasma. ) to the dielectric ring 139 can be suppressed. Therefore, the reliability of the plasma processing device can be improved, and the occurrence of uneven processing shape can be suppressed, thereby improving the manufacturing yield of the semiconductor wafer 109.

In addition, high-frequency power is supplied from the single high-frequency power source 124 to the electrode base 108 of the sample stand ST and the thin film electrode 139b provided on the dielectric ring 139, thereby applying it to the electrode base 108. Electrical mutual interference between the high-frequency power and the high-frequency power applied to the thin film electrode 139b can be suppressed. Below the back surface 109b of the semiconductor wafer 109, the inner peripheral end 139bie of the thin film electrode 139b can be brought close to the sample stand ST, and the first portion 139b1 of the thin film electrode 139b and The second portion 139b2 may be approached to the semiconductor wafer 109. As a result, desirable electric field control and cis potential control are possible in the peripheral and outer regions of the semiconductor wafer 109, thereby achieving the effects of improved reliability of the plasma processing device and improved yield of the semiconductor wafer 109.

(Variation Example 1)

FIG. 5 is a cross-sectional view showing the peripheral portion of the wafer placement electrode of the plasma processing apparatus of Modification Example 1. Figure 5 is a modified example of Figure 4.

4 of the above embodiment, the shape of the dielectric ring 139' is different. The upper surface of the dielectric ring 139a' has a first surface 139a1, a third surface 139a3', and a second surface 139a2. The third surface 139a3' has an inclination greater than 90° with respect to the first surface 139a1 and the second surface 139a2. The third surface 139a3' has an inclination that approaches the sample stand ST along the vertical direction.

The ring-shaped thin film electrode 139b' has a ring width extending from the inner peripheral end 139bie to the outer peripheral end 139boe, and includes a first part 139b1, a third part 139b3', and a second part in the width direction ( 139b2). The first part 139b1, the third part 139b3', and the second part 139b2 are the first surface 139a1, the third surface 139a3', and the upper surface of the dielectric ring 139a', respectively. It is formed corresponding to the second surface 139a2. Accordingly, the third portion 139b3' has an inclination that approaches the sample stage ST along the vertical direction.

In Modification 1 as well, as in the above embodiment, the first portion 139b1 has an “overlapping area” between the first portion 139b1 and the semiconductor wafer 109 when viewed from the top. In addition, the first part 139b1 is arranged at a distance A in the vertical direction from the back surface 109b, and the third part 139b3' is arranged at a horizontal distance from the end 109e of the semiconductor wafer 109. They are placed spaced apart by B', and distance A is smaller than distance B'.

According to Modification 1, compared to the above embodiment, the lower part of the third portion 139b3' can be brought closer to the end 109e of the semiconductor wafer 109. Therefore, it affects the cis potential distribution around the end 109e of the semiconductor wafer 109, making it possible to change the cis potential control region.

(Variation 2)

Figure 6 is a cross-sectional view schematically showing the outline of the configuration of the plasma processing device of Modification Example 2. 2 of the above embodiment, the source of supply of high-frequency power is different. In Modification 2, the high-frequency power source 124 is connected to the conductor film 111 through the matching device 129 and the branch box 127.

Also in the configuration shown in FIG. 6, the change in load impedance from the configuration shown in FIG. 2 is corrected by appropriately changing the high-frequency power value of the high-frequency power source 124, thereby forming the semiconductor wafer 109 formed by the conductor film 111. ) The cis potential distribution in the peripheral and outer regions is similar to the cis potential distribution in the case of Fig. 2, and the same effect as in the above embodiment can be obtained.

In addition, in the above embodiment or modified example, the etching film disposed on the main surface of the semiconductor wafer 109 before processing is a silicon oxide film, and the processing gas for etching and the cleaning gas for cleaning include tetrafluoromethane gas and oxygen gas. , trifluoromethane gas is used. In addition, the etching film includes not only a silicon oxide film, but also a polysilicon film, a photoresist film, an anti-reflection organic film, an anti-reflection inorganic film, an organic material, an inorganic material, a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, and a low-k Materials, high-k materials, amorphous carbon films, Si substrates, metal materials, etc. can be used, and the same effect is obtained in these cases as well.

Additionally, processing gases for etching include chlorine gas, hydrogen bromide gas, tetrafluoromethane gas, trifluoromethane gas, difluoromethane gas, argon gas, helium gas, oxygen gas, nitrogen gas, carbon dioxide gas, carbon monoxide gas, and hydrogen. Gas, etc. can be used. In addition, processing gases for etching include ammonia gas, propane octafluoride gas, nitrogen trifluoride gas, sulfur hexafluoride gas, methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, neon gas, krypton gas, xenon gas, and radon gas. etc. can be used.

Above, the invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and of course various changes can be made without departing from the gist of the invention. For example, the wafer placement electrode 120 may be provided with a heater for controlling the temperature of the semiconductor wafer 109 inside the dielectric film 140 or inside the base electrode 108. Additionally, for such temperature control, at least one temperature sensor may be provided inside the substrate electrode 108 to be able to communicate with the controller 170 and detect the temperature.

In the above embodiment, a configuration was explained in which a microwave electric field with a frequency of 2.45 GHz and a magnetic field capable of forming ECR are supplied into the processing chamber 104, and processing gas is discharged to form plasma. However, the configuration described in the above embodiment may be used to form plasma using other discharges (effective magnetic field UHF discharge, capacitively coupled discharge, inductively coupled discharge, magnetron discharge, surface wave excitation discharge, and transfer/coupled discharge). , the same actions and effects as those described in the above embodiments, etc. can be exhibited. In addition, the same applies to the case where the above embodiment and modification examples 1 and 2 are applied to wafer placement electrodes disposed in other plasma processing devices that perform plasma processing, such as plasma CVD devices, ashing devices, surface modification devices, etc. The effect can be obtained.

OS: centered OU: centered
ST: Sample stand 100: Plasma etching device
101: Vacuum container 102: Shower plate
102a: gas introduction hole 103: dielectric window
104: processing chamber 105: waveguide
106: Power source for electric field generation 107: Magnetic field generation coil
108: electrode base 108a: top surface
108d: concave part (depression) 108p: convex part (protrusion)
109: semiconductor wafer 109a: main surface
109b: Back side 109e: End (circle)
110: Vacuum exhaust port 111: Conductor film
112: ground 113: susceptor ring
116: Plasma 120: Electrode for wafer placement
120a: tread surface 120b: top surface
124: high frequency power 125: high frequency filter
126: DC power supply 127: Branch box
129: Matcher 130: Load impedance variable box
139: dielectric ring 139a: dielectric ring
139a1: first side 139a2: second side
139a3: Third side 139a3': Third side
139b: thin film electrode 139b1: first part
139b2: Second part 139b3: Third part
139b3': Third part 139bie: Naejudan
139boe: outer edge 140: dielectric film
150: insulation plate 151: ground plate
152: Refrigerant flow path 160: Electric field/magnetic field forming part
170: controller

Claims (12)

A sample table is disposed in a processing chamber where plasma inside a vacuum processing device is formed and has a placement surface on which a wafer to be processed is placed, and is disposed in the central portion of the upper portion and has a cylindrical shape having the placement surface on the upper surface. a sample stand having a convex portion, a concave portion arranged to surround the convex portion in a ring shape and constituting an outer peripheral portion of the upper portion, and a high-frequency electrode to which high-frequency power is supplied during processing of the wafer;
A ring-shaped thin film electrode disposed in the concave portion surrounding the convex portion and supplied with high frequency power of a different magnitude from that supplied to the high frequency electrode during processing of the wafer, and a dielectric disposed above the thin film electrode to cover the convex portion. It has a susceptor ring having a part of the system,
The thin film electrode includes a first part that constitutes an inner peripheral end and is located lower than the placement surface and has a flat portion, and this first portion and a flat second portion that is disposed on the outer peripheral side of the wafer and is located higher than the upper surface of the wafer. And, a third part that connects the outer periphery of the first part and the inner periphery of the second part to form a step-shaped part,
The susceptor ring includes an inner peripheral end that covers the first part of the thin film electrode and is located below the outer peripheral end of the wafer when viewed from the top with the wafer placed on the mounting surface, and an upper surface that covers the second part. A plasma processing device comprising this flattened outer peripheral portion and a portion that integrally connects the inner peripheral end portion and the outer peripheral portion and has an inclined upper surface that increases toward the outer periphery and covers the second portion. According to paragraph 1,
The inner peripheral end of the thin film electrode is located below the outer peripheral end of the wafer placed on the placing surface in a planar view. According to claim 1 or 2,
A plasma processing device comprising an insulating ring made of a dielectric disposed between the upper surface of the concave portion and the thin film electrode. According to claim 1 or 2,
A plasma processing device, wherein the sample stand is provided with a substrate and a dielectric film disposed on the substrate and whose upper surface constitutes the placement surface. According to clause 4,
A plasma processing device comprising a high-frequency power source that supplies the high-frequency power to the substrate. According to clause 4,
A plasma processing device, wherein the dielectric film has a conductive film inside which the high-frequency power is supplied. A plasma processing method in which a wafer to be processed is placed on a placement surface of the upper part of a sample stand placed in a processing chamber inside a vacuum container, and the wafer is processed using plasma formed in the processing chamber,
The sample stand includes a cylindrical convex portion disposed in the central portion of the upper surface and having the mounting surface on the upper surface, a concave portion arranged to surround the convex portion in a ring shape and constituting an outer peripheral portion of the upper portion, and a high-frequency power source during processing of the wafer. A susceptor ring having a supplied high-frequency electrode, a ring-shaped thin film electrode disposed in the concave portion surrounding the convex portion, and a portion of a dielectric material disposed above the thin film electrode to cover it,
The thin film electrode includes a first part that constitutes an inner peripheral end and is located lower than the placement surface and has a flat portion, and this first portion and a flat second portion that is disposed on the outer peripheral side of the wafer and is located higher than the upper surface of the wafer. And, a third part that connects the outer periphery of the first part and the inner periphery of the second part to form a step-shaped part,
The susceptor ring includes an inner peripheral end that covers the first part of the thin film electrode and is located below the outer peripheral end of the wafer when viewed from the top with the wafer placed on the mounting surface, and an upper surface that covers the second part. This flattened outer peripheral portion is provided with a portion that integrally connects the inner peripheral end and the outer peripheral portion and has a sloping upper surface that increases toward the outer periphery and covers the second portion,
A plasma processing method in which high-frequency power of a different magnitude from that supplied to the high-frequency electrode is supplied during processing of the wafer. In clause 7,
A plasma processing method, wherein the inner peripheral end of the thin film electrode is located below the outer peripheral end of the wafer placed on the placing surface in a planar view. According to claim 7 or 8,
A plasma treatment method comprising an insulating ring made of a dielectric disposed between the upper surface of the concave portion and the thin film electrode. According to claim 7 or 8,
A plasma treatment method, wherein the sample stand is provided with a substrate and a dielectric film disposed on the substrate and whose upper surface constitutes the mounting surface. According to clause 10,
A plasma treatment method of supplying the high frequency power to the substrate. According to clause 10,
A plasma processing method in which the high-frequency power is supplied to a conductive film disposed inside the dielectric film.