KR20240098502A - Micro led display apparatus and tiling display apparatus - Google Patents

Abstract

A micro LED display device is disclosed that can cancel out EMI caused by a gate clock signal of the upper substrate by designing a pattern and circuit to reduce low-frequency band noise in the lower substrate of the micro LED. The micro LED display device includes an upper substrate on which a micro LED is mounted and a gate clock line to which a gate clock signal is supplied, and a lower substrate that is connected to the upper substrate through routing and has a base voltage line to which a base voltage is supplied; , A pseudo signal line through which a pseudo signal is supplied to cancel out noise generated by the gate clock signal is disposed on the lower substrate.

Description

Micro LED display device and tiling display device {MICRO LED DISPLAY APPARATUS AND TILING DISPLAY APPARATUS}

This specification relates to display devices, and more specifically, to micro LED display devices and tiling display devices.

In addition to display devices for televisions and monitors, display devices are widely used as display screens for laptop computers, tablet computers, smart phones, portable display devices, and portable information devices.

Recently, research and development on micro LED display devices that use micro LEDs as light emitting devices are in progress, and they are in the spotlight as next-generation display devices because they have high image quality and high reliability.

Due to the driving characteristics of micro LED display devices and tiling display devices, it is difficult to design a pseudo signal for EMI (Electro Magnetic Interference) stabilization within the upper board due to limitations in spatial pattern design for high voltage gate signals supplied to multiple blocks. there is.

There are limitations in designing micro LED display devices and tiling display devices with a close spacing to the ground plane, which plays a role in stabilizing panel common noise, due to the panel thickness.

Micro LED display devices and tiling display devices require timing distribution for high-voltage gate signals to avoid noise overlap of gate clocks that output and operate at the same timing when operating between units within a cabinet, and at this time, the step between screens is There is a problem that arises.

The inventors of the present specification have developed a micro LED display device and a tiling display device that can secure EMI reduction technology of the gate clock without interference to the operation of the light emitting unit within the structural limitations of the pattern design.

The problem to be solved according to an embodiment of the present specification is to provide a micro LED display device and a tiling display device that can offset EMI caused by the gate clock signal of the upper substrate by designing patterns and circuits to reduce low-frequency band noise in the lower substrate. I'm doing it.

In addition, the problem to be solved according to an embodiment of the present specification is to provide a micro LED display device and a tiling display device that can ensure a stable voltage supply by applying a conductive adhesive between the upper substrate and the lower substrate.

In addition, the problem to be solved according to an embodiment of the present specification is to provide a micro LED display device and a tiling display device that can prevent screen steps due to timing dispersion by supplying a phase compensation signal through the lower substrate.

The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A micro LED display device according to an embodiment includes an upper substrate on which a micro LED is mounted and a gate clock line supplied with a gate clock signal, and a base voltage line connected to the upper substrate through routing and supplied with a base voltage. Includes a lower substrate. A pseudo signal line through which a pseudo signal is supplied to cancel out noise generated by the gate clock signal is disposed on the lower substrate.

A tiling display device according to an embodiment includes a first panel, a second panel, and a control circuit that outputs a reference gate signal to the first panel and a gate clock signal with delayed timing to the second panel, and the first panel and each of the second panels includes an upper substrate and a lower substrate connected to the upper substrate through routing. A dispersion compensation circuit that compensates for the timing of the reference gate signal and the delayed gate clock signal is disposed on at least one of the upper substrate and the lower substrate.

According to embodiments, EMI caused by the gate clock signal of the upper substrate can be offset by designing patterns and circuits to reduce low-frequency band noise in the lower substrate of the micro LED.

Additionally, a stable voltage supply can be ensured by applying a conductive adhesive between the upper and lower substrates.

Additionally, by supplying a phase compensation signal through the lower substrate, screen steps due to timing dispersion can be prevented.

Additionally, within the structural limits of the pattern design within the micro LED unit, gate clock EMI can be reduced without interfering with the operation of the light emitting unit.

Additionally, side effects of the timing distribution technology applied to resolve the noise overlap phenomenon can be eliminated.

Additionally, there is an EMI improvement effect due to the arrangement of the ground plane between the upper and lower substrates.

Additionally, the ground plane can be expanded by designing the adhesive and sealant materials applied for fixation between the upper and lower substrates to be conductive.

In addition to the above-described effects, specific effects of the present invention are described below while explaining specific details for carrying out the invention.

Figure 1 is a view of a micro LED display device according to an embodiment developed with the upper substrate and the lower substrate separated.
Figure 2 is a cross-sectional view of a tiling display device according to an embodiment.
3 to 6 are diagrams illustrating an inversion circuit of a micro LED display device according to an embodiment.
Figure 7 is a waveform diagram of a gate clock signal and a pseudo signal in a micro LED display device according to an embodiment.
Figures 8 and 9 are diagrams illustrating termination patterns of the pseudo signal lines of Figure 1.
Figure 10 is a cross-sectional view of the upper side area of a micro LED display device according to one embodiment.
Figure 11 is a cross-sectional view of a lower side area of a micro LED display device according to an embodiment.
Figure 12 is a diagram of a tiling display device according to an embodiment.
FIG. 13 is a view showing the development of one micro LED display device of FIG. 12 with the upper and lower substrates separated.
Figure 14 is a waveform diagram for explaining noise cancellation in a micro LED display device according to an embodiment.
Figure 15 is a block diagram of a gate signal generating device in a micro LED display device according to an embodiment.
FIG. 16 is a detailed block diagram of a gate signal generating device in the micro LED display device of FIG. 15.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and the present embodiments only serve to ensure that the disclosure of the present specification is complete and that common knowledge in the technical field to which the present specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as ‘after’, ‘after’, ‘after’, ‘before’, etc., ‘immediately’ or ‘directly’ Non-consecutive cases may also be included unless ' is used.

In the case of a description of the signal flow relationship, for example, 'a signal is transmitted from node A to node B', unless 'immediately' or 'directly' is used, it is transmitted from node A to another node. This may include cases where a signal is transmitted to the B node.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Below, a micro LED display device according to some embodiments will be described.

In the specification, a pseudo signal can be defined as a signal that cancels out noise by reducing the peak current that occurs in the transition section of the gate clock signal used to drive the micro LED. For example, the pseudo signal may be designed to have a signal pattern that is an inverted gate clock signal.

Figure 1 is a view of a micro LED display device according to an embodiment, with the upper and lower substrates separated and developed.

For convenience of explanation, FIG. 1 shows a separate developed view of the upper substrate 10 and the lower substrate 20. The printed circuit board 40 and COF (Chip On Film) are attached to the back of the lower substrate 20. The back surfaces of the upper substrate 10 and the lower substrate 20 may be fixed by adhesive.

Figure 2 is a cross-sectional view of a tiling display device according to an embodiment. As an example, Figure 2 is a cross-sectional view of the lower side area A2 of Figure 1.

Referring to FIGS. 1 and 2 , a micro LED display device and a tiling display device according to an embodiment include an upper substrate 10 and a lower substrate 20 . The upper substrate 10 and lower substrate 20 may be glass. However, the present invention is not limited thereto, and the upper substrate 10 and lower substrate 20 may be made of a flexible material such as polyimide.

A micro LED 12 and a thin film transistor 11 are mounted on the upper substrate 10, and a gate clock line L1 to which a gate clock signal is supplied is disposed.

The micro LED 12 may be an LED with a size of 100 μm or less, or with the wafer removed.

The thin film transistor 11 may be a driving transistor driven in response to a data voltage or an emission transistor driven in response to an emission signal. The driving transistor and the emission transistor form a current path to transfer current to the micro LED 12, causing the micro LED 12 to emit light. For example, a micro LED display device can control the pulse width of the emission signal to determine the intensity of the current in the current path.

The upper substrate 10 and the lower substrate 20 are connected through routing 60. The upper substrate 10 and the lower substrate 20 are each provided with a pad portion 62, and the routing 60 is provided with a pad portion 62 of the upper substrate 10 and a pad portion 62 of the lower substrate 20. Connect.

A conductive adhesive 30 and a sealant 50 are formed between the upper substrate 10 and the lower substrate 20. The sealant 50 is formed between the conductive adhesive 30 and the routing 60 to insulate the conductive adhesive 30 and the routing 60.

The lower substrate 20 is connected to the upper substrate 10 through routing, and a power line L3 through which a power voltage is supplied is disposed on the lower substrate 20. The power supply voltage can be a base voltage (EVSS) or a high potential voltage (EVDD).

For example, a micro LED display device uses seamless tiling between units consisting of an upper substrate 10 that serves as a light emitter and a lower substrate 20 on which a printed circuit board 40 for generating micro LED driving signals is mounted. ) For implementation, the interior is fixed with at least one of the conductive adhesive 30 and the sealant 50.

The lower substrate 20 is arranged with a base voltage (EVSS) signal line that guarantees a potential of 0V, and is connected to the upper substrate 10 through upward side routing. All remaining signals other than the base voltage (EVSS) are connected to the printed circuit board 40 through downward side routing.

Here, the upper side routing can be defined as routing the upper substrate 10 and the lower substrate 20 in the upper side area A1, and the lower side routing can be defined as routing the upper substrate 10 and the lower substrate 20 in the lower side area A2. It may be defined as routing the lower substrate 20.

A driving circuit for driving the pixel circuit may be mounted on the printed circuit board 40, and a signal line that transmits a signal from the driving circuit to the display panel may be mounted on the COF.

A pseudo signal line L2 is disposed on the lower substrate 20 to supply a pseudo signal to cancel out noise generated by the gate clock signal.

The pseudo signal is supplied to the pseudo signal line L2 of the lower substrate 20 and has the same pattern as the inverted signal of the gate clock signal supplied to the gate clock line L1 of the upper substrate 10. The pseudo signal cancels out noise by reducing the peak current that occurs in the transition section of the gate clock signal.

For example, the inverted signal pattern can be designed as a pattern that inverts the gate clock signal pattern, and can be used as an offset signal for the high voltage signal output from the level shifter. For example, an inversion circuit for the level shifter output may be designed on the printed circuit board 40 or the lower board 20. The inversion circuit may be disposed on one side adjacent to the upper side area A1 or the lower side area A2 on the plane of the lower substrate 20.

3 to 6 are diagrams illustrating an inversion circuit of a micro LED display device according to an embodiment.

Referring to FIG. 3, the micro LED display device includes an inverting circuit (IV1) that supplies a signal obtained by inverting the gate clock signal as a pseudo signal to the pseudo signal line (L2).

For example, the inversion circuit IV1 may be mounted on the printed circuit board 40 that generates driving signals for the micro LED. The gate clock generation circuit of the printed circuit board 40 supplies a gate clock signal to the gate clock line L1 disposed on the upper board 10 via COF (Chip On Film).

The inversion circuit IV1 of the printed circuit board 40 supplies a signal obtained by inverting the gate clock signal as a pseudo signal to the pseudo signal line L2 disposed on the lower substrate 20.

As another example, referring to Figures 4 and 5, the inverting circuit (IV1) is mounted on the lower board (20) between the pseudo signal line (L2) and the printed circuit board (40) that generates the driving signals of the micro LED. You can.

For example, as shown in FIG. 4, the inversion circuit IV1 may be mounted on one side of the back of the lower substrate 20 adjacent to the portion where the COF is attached. The gate clock generation circuit of the printed circuit board 40 supplies a gate clock signal to the gate clock line L1 disposed on the upper board 10 via COF (Chip On Film).

The gate clock generation circuit of the printed circuit board 40 supplies the gate clock signal through COF (Chip On Film) to the inversion circuit (IV1) mounted on the back of the lower board 20 and on one side adjacent to the portion where the COF is attached. do. The inverting circuit IV1 supplies a signal obtained by inverting the gate clock signal as a pseudo signal to the pseudo signal line L2 on one side of the lower substrate 20 adjacent to the portion where the COF is attached.

As another example, as shown in FIG. 5, the inversion circuit IV1 may be mounted on the back of the lower substrate 20 and on one side adjacent to the upper side area A1. The gate clock generation circuit of the printed circuit board 40 supplies a gate clock signal to the gate clock line L1 disposed on the upper board 10 via COF (Chip On Film).

The gate clock signal is supplied to the inverting circuit IV1 mounted on the rear side of the lower substrate 20 and adjacent to the upper side area A1 through the gate clock line L1. The inverting circuit IV1 supplies a signal obtained by inverting the gate clock signal as a pseudo signal to the pseudo signal line L2 from above the lower substrate 20.

In another example, as shown in FIG. 6, an auxiliary gate clock line (L1a) connected to the gate clock line (L1) of the upper substrate 10 is disposed on the lower substrate 20. The auxiliary gate clock line (L1a) is connected to the slew compensation circuit (42). The slew compensation circuit 42 may be disposed on the printed circuit board 40 .

The slew compensation circuit 42 senses the gate clock signal transmitted from the auxiliary gate clock line (L1a), and takes into account the slew of the gate clock signal and uses the supplemented inverted signal pattern as a pseudo signal to the pseudo signal line (L2). supply to. For example, the gate clock signal may have slew formed at the rising edge or falling edge portion due to the impedance of the gate clock line, and the slew compensation circuit 42 compensates for the slew formed at the rising edge or falling edge portion of the gate clock signal ( A reversal signal pattern can be created by considering slew).

Figure 7 is a waveform diagram of a gate clock signal and a pseudo signal in a micro LED display device according to an embodiment. Figures 8 and 9 are diagrams illustrating termination patterns of the pseudo signal lines of Figure 1.

As shown in FIG. 7, the gate clock signal (GCLK_n) can be defined as an ideal signal without considering the impedance of the gate clock line, and the gate clock signal (GCLK_m) has rising and falling edges depending on the impedance of the gate clock line. It can be defined as a signal that has slew in the part.

The pseudo signal (Pseudo_n) has the same pattern as the inverted signal of the gate clock signal (GCLK_n). For example, the pseudo signal Pseudo_n may be designed to ensure the same rising and falling inverted as the gate clock signal GCLK_n of the upper substrate 10.

The pseudo signal (Pseudo_m) has the same pattern as the inverted signal of the gate clock signal (GCLK_m). For example, the pseudo signal Pseudo_m may be designed to ensure the same inverted rising and falling as the gate clock signal GCLK_m by considering the impedance of the gate clock line.

As another example, as shown in FIGS. 8 and 9, considering the slew of the gate clock signal due to the impedance of the gate clock line, the termination of the pseudo signal line L2 is a serpent pattern. can be formed. Here, termination may be defined as the end of the pseudo signal line (L2) adjacent to the ground.

As shown in FIG. 8, the end of the pseudo signal line L2 may be formed as a pulse-shaped serpent pattern L2a. Alternatively, as shown in FIG. 9, the end of the pseudo signal line L2 may be formed as a gently curved serpent pattern L2b.

The length of the end of the pseudo signal line L2 may be determined depending on the impedance of the gate signal line, and may be formed as a serpent pattern L2a or serpent pattern L2b depending on the length.

That is, by considering the slew of the gate clock signal according to the impedance of the gate signal line and designing the pattern at the end of the pseudo signal line (L2) to be complementary, the impedance of the pseudo signal line is adjusted to be the same as the impedance of the gate signal line, so that the gate clock An inverted signal identical to the signal can be obtained as a pseudo signal.

Figure 10 is a cross-sectional view of the upper side area of a micro LED display device according to an embodiment. Figure 11 is a cross-sectional view of a lower side area of a micro LED display device according to an embodiment.

Referring to FIGS. 1, 10, and 11, the upper substrate 10 and the lower substrate 20 are connected through upward routing in the upper side area A1 and downward routing in the lower side area A2.

In the upper side area A1, as shown in FIG. 10, a conductive adhesive 30 is formed between the upper substrate 10 and the lower substrate 20 of the upper side area A1.

The conductive adhesive 30 connects the base voltage electrode 80 of the upper substrate 10 and the base voltage electrode 80 of the lower substrate 20 through the routing 60 in the upper side area A1. The conductive adhesive 30 serves as a reference plane between the upper substrate 10 and the lower substrate 20 in the upper side area A1, thereby maintaining the base voltage electrode 80 of the upper substrate 10 or the lower substrate 20. The distance between the and reference planes can be reduced by half compared to before.

And, in the lower side area A2, as shown in FIG. 11, a conductive adhesive 30 and a sealant 50 are formed between the upper substrate 10 and the lower substrate 20. The sealant 50 is formed between the conductive adhesive 30 and the routing 60 in the lower side area A2 to insulate the conductive adhesive 30 and the routing 60.

The non-base voltage signal electrode 90 of the upper substrate 10 and the non-base voltage signal electrode 90 of the lower substrate 20 are connected through routing 60. The routing 60 may be formed of silver (Ag), and the sealing portion 70 that seals the routing 60 may be formed of an insulating material. The material of the routing 60 is not limited thereto and may be formed of a conductive material. For example, the sealing part 70 may be made of polyethylene, natural rubber, polyester, epoxy resin, synthetic resin, etc.

In this way, the reference plane of the micro LED is designed to be strengthened. The reference plane is connected to the ground and serves as a ground plane. A plane that serves as a ground plane is additionally designed between the upper substrate 10 and the lower substrate 20. Here, the ground plane serves to match the potential standard of the upper substrate 10 and the potential standard of the lower substrate 20. Additionally, the ground plane serves to emit EMI generated from the upper substrate 10 or the lower substrate 20 to the ground.

The upper side area A1 can reduce the distance from the reference plane to less than L/2 by applying the conductive adhesive 30 and sealant 50 between the upper substrate 10 and the lower substrate 20. Here, L may be defined as the distance between the electrodes of the upper substrate 10 and the lower substrate 20.

By reducing the distance between the electrode of the upper substrate 10 and the reference plane or the distance between the electrode of the lower substrate 20 and the reference plane, the standard of the potential of the upper substrate 10 and the lower substrate 20 can be quickly set. And, EMI generated from the upper substrate 10 or the lower substrate 20 can be quickly discharged to the ground. An EMI improvement effect can be expected by providing a ground plane between the upper substrate 10 and the lower substrate 20. In addition, during upper side routing, the sealant 50 can be grounded with the routing 60 during sealing so that it is connected to the signal electrode 90.

Figure 12 is a diagram of a tiling display device according to an embodiment.

FIG. 13 is a diagram illustrating one micro LED display device of FIG. 12.

FIG. 13 is a diagram in which the upper substrate 10 and the lower substrate 20 are separated and developed for convenience of explanation. The printed circuit board 40 and COF are attached to the back of the lower substrate 20. The back surfaces of the upper substrate 10 and the lower substrate 20 may be adhered and fixed.

Figure 14 is a waveform diagram for explaining noise cancellation in a micro LED display device according to an embodiment.

In FIG. 14, a reference signal may be defined as a reference signal used to generate a gate clock signal in a shift register. A pseudo signal can be defined as a signal used to cancel out noise by reducing the peak current occurring in the transition section of the gate clock signal.

Referring to FIGS. 12 to 14, the tiling display device according to one embodiment includes a first panel (B1), a second panel (B2), a third panel (B3), a fourth panel (B4), and a control circuit (FPGA). , Field Programmable Gate Array).

The control circuit (FPGA) outputs a reference gate signal to the first panel (B1) and the third panel (B3) and outputs a gate clock signal with delayed timing to the second panel (B2) and the fourth panel (B4).

Each of the first panel B1, the second panel B2, the third panel B3, and the fourth panel B4 includes an upper substrate 10 and a lower substrate 20. The upper substrate 10 and the lower substrate 20 are connected through routing 60. Routing 60 includes upward routing and downward routing, with the upward routing being disposed in the upward routing area (A1) and the downward routing being disposed in the downward routing area (A1).

A dispersion compensation circuit 44 is disposed on at least one of the upper substrate 10 and the lower substrate 20 to compensate for the timing of the reference gate signal and the delayed gate clock signal.

The dispersion compensation circuit 44 may be formed on at least one of the upper substrate 10 and the lower substrate 20. For example, the dispersion compensation circuit 44 may be provided on the gate clock line L1 of the top glass 10 adjacent to the routing in the upper side area. Alternatively, the dispersion compensation circuit 44 may be provided on the pseudo signal line L2 of the lower glass 20 adjacent to the routing in the upper side area.

A micro LED is mounted on the upper substrate 10 and a gate clock line (L1) to which a gate clock signal is supplied is disposed. A base voltage line (L3) is disposed on the lower substrate 20, connected to the upper substrate 10 through routing and supplied with a base voltage, and supplied with a pseudo signal to cancel out noise generated by the gate clock signal. A signal line (L2) is disposed.

For example, two or more panels operating with one control circuit (FPGA) apply timing distribution technology to prevent gate clock noise from overlapping. The gate clock signal is supplied to the display panel by adding the phase compensation signal (PSC, Phase Shift Compensation CLK) of the shift register in the control circuit (FPGA).

The control circuit (FPGA) outputs a reference gate signal to the first panel (B1) and the third panel (B3) and supplies a gate clock signal with delayed timing to the second panel (B2) and the fourth panel (B4). Alternatively, the control circuit (FPGA) outputs a delayed gate clock signal to the first panel (B1) and the third panel (B3) and supplies a reference gate signal to the second panel (B2) and the fourth panel (B4) to level Distributes the output signal of the shifter. For example, the level shifter of the first panel (B1) outputs an output signal using a reference gate signal, and the level shifter of the second panel (B2) outputs an output signal using a gate clock signal with delayed timing, Output timing may be distributed.

The dispersion compensation circuit 44 is designed on at least one of the upper substrate 10 and the lower substrate 20 to prevent screen steps caused by gate output timing differences due to timing dispersion. Here, the screen step may be exemplified as a timing difference between images displayed on the first to fourth panels B1 to B4.

For example, a distributed compensation circuit 44 is designed to supply a compensated shift register compensation signal to the gate clock line L1 of the upper substrate 10. For example, the dispersion compensation circuit 44 can be added to the dummy gate driver block in the upper substrate 10. Additionally, part of the base voltage signal line in the lower substrate 20 can be deleted and the dispersion compensation circuit 44 can be designed.

The dispersion compensation circuit 44 compensates for the timing of the gate clock signal whose timing is dispersed and delayed from the reference gate signal and supplies it to the gate clock line L1 of the top glass 10.

For example, the dispersion compensation circuit 44 may be provided on the gate clock line L1 of the top glass 10 adjacent to the routing in the upper side area. Alternatively, the dispersion compensation circuit 44 may be provided on the pseudo signal line L2 of the lower glass 20 adjacent to the routing in the upper side area.

Figure 15 is a block diagram of a gate signal generating device in a micro LED display device according to an embodiment. FIG. 16 is a detailed block diagram of a gate signal generating device in the micro LED display device of FIG. 15. Figures 15 and 16 show a timing distribution technique for the level shifter output signal.

15 and 16, the gate signal generating device includes a phase shift filter 200, a first level shifter 310, a second level shifter 320, a first phase compensation circuit 410, and a second phase compensation circuit. It includes a circuit 420, a first GIP (Gate In Panel) circuit 510, and a second GIP circuit. Here, the first GIP circuit 510 and the second GIP circuit may be composed of shift registers and may be named the first shift register 510 and the second shift register 520.

The gate signal generating device receives a phase compensation signal (PSC), a gate start pulse (GSP), a gate clock signal (GCLK1), and a master clock signal (MCLK1) from the timing controller 100, and generates a first gate signal based on these. (P_Gate Out1) to 2160th gate signals (P_Gate Out2160) are generated and sequentially output to each of the gate lines of the display panel.

The first level shifter 310 receives a phase compensation signal (PSC), a gate start pulse (GSP), a gate clock signal (GCLK1), and a master clock signal (MCLK1) from the timing controller 100. The first level shifter 310 transfers the phase compensation signal (PSC) to the first phase compensation circuit 410, and sends a start signal (VST) and a reset signal (RST) to the first phase compensation circuit 410 in response to the gate start pulse (GSP). It is output to the phase compensation circuit 410. The first level shifter 310 generates a first clock signal (CLK1) to a tenth clock signal (CLK10) based on the gate clock signal (GCLK1) and the master clock signal (MCLK1), and generates them in the first shift register 510. ) is output.

The phase shift filter 200 receives the gate clock signal (GCLK1) and the master clock signal (MCLK1) from the timing controller 100, delays them, and receives the delayed gate clock signal (F_GCLK2) and the delayed master clock signal (F_MCLK2). It is output to the second level shifter 320.

The second level shifter 320 receives a phase compensation signal (PSC) and a gate start pulse (GSP) from the timing controller 100. The second level shifter 320 transfers the phase compensation signal (PSC) to the second phase compensation circuit 420, and sends a start signal (VST) and a reset signal (RST) to the second phase compensation circuit 420 in response to the gate start pulse (GSP). It is output to the phase compensation circuit 420.

The second level shifter 320 generates first clock signals (CLK1) to tenth clock signals (CLK10) based on the delayed gate clock signal (F_GCLK2) and the delayed master clock signal (F_MCLK2), and transfers them to the second shift register. Printed at (520). The first to tenth clock signals CLK1 to CLK10 output from the second level shifter 320 are the first to tenth clock signals CLK1 to CLK10 to be output from the first level shifter 310. ) and has a different phase.

The first phase compensation circuit 410 compensates for the phases of the start signal (VST) and the reset signal (RST) based on the phase compensation signal (PSC) to generate the compensation start signal (P_VST) and the compensation reset signal (P_RST) to the first It is output to the shift register 510.

The second phase compensation circuit 420 compensates for the phases of the start signal (VST) and the reset signal (RST) based on the phase compensation signal (PSC) and adjusts the compensation start signal (P_VST) and the compensation reset signal (P_RST) to the second phase compensation circuit 420. Output to shift register 520.

The first shift register 510 sequentially outputs the first gate signal (P_Gate Out1) to the 2160th gate signal (P_Gate Out2160) in response to the compensation start signal (P_VST). The first shift register 510 initializes a specific node of the internal circuit to the base voltage or power supply voltage in response to the compensation reset signal (P_RST).

The second shift register 520 sequentially outputs the first gate signal (P_Gate Out1) to the 2160th gate signal (P_Gate Out2160) in response to the compensation start signal (P_VST). The second shift register 520 initializes a specific node of the internal circuit to the base voltage or power supply voltage in response to the compensation reset signal (P_RST).

The gate signal generating device may be provided on the left and right sides of each of the first to fourth panels B1 to B4. The gate signal generation device distributes EMI by adjusting the phase of the gate clock (level shifter ~ shift register). The first phase compensation circuit 410 and the second phase compensation circuit 420 may be provided in a dummy stage of the shift register. For example, the first shift register 510 and the second shift register 520 may include a plurality of stages that are sequentially driven in response to the compensation start signal (P_VST), and the plurality of stages may be configured to receive a first gate signal ( P_Gate Out1) to the 2160th gate signal (P_Gate Out2160) are sequentially output.

Here, at least one of the first stage and the last stage among the plurality of stages may be used as a dummy stage. For example, if the first stage is a dummy stage, the compensation start signal (P_VST) can be output to the second stage, and if the last stage is a dummy stage, the compensation start signal (P_VST) can be output to the last previous stage. You can. In other words, a phase compensation circuit is configured in the shift register dummy stage to prevent screen steps on the left and right sides of the panel.

The T1 period is a period for generating a phase difference between the first level shifter 310 and the second level shifter 320. The T2 period is a period in which the phases between the first shift register 510 and the second shift register 520 are compensated to be the same.

The timing controller 100 transmits a phase compensation signal (PSC) along with a gate start pulse (GSP), a gate clock signal (GCLK1), and a master clock signal (MCLK1) to the first level shifter 310 and the second level shifter 320. provided to. A phase shift filter 200 is provided between the timing controller 100 and the second level shifter 320, so that the delayed gate clock signal (F_GCLK2) and the delayed master clock signal (F_MCLK2) are transmitted to the second level shifter (320). ) is provided.

The first level shifter 310 and the second level shifter 320 shift the level-shifted first clock signal CLK1 to second clock signal CLK10 into the first shift register 510 and the second shift register 520. provided to.

And, the first level shifter 310 and the second level shifter 320 use the phase compensation signal (PSC), the start signal (VST), and the reset signal (RST) to operate the first phase compensation circuit 410 and the second phase compensation circuit. Provided to circuit 420. The first phase compensation circuit 410 and the second phase compensation circuit 420 compensate for the phases of the start signal (VST) and the reset signal (RST), and the phase-compensated start signal (P_VST) and reset signal (P_RST) is provided to the first shift register 510 and the second shift register 520.

The first shift register 510 and the second shift register 520 provide first to 2160th phase-compensated gate signals (P_Gate Out1) in response to the phase-compensated compensation start signal (P_VST) and the compensation reset signal (P_RST). ~ P_Gate Out2160) is output to the gate lines of the display panel.

A micro LED display device according to an embodiment is designed to cancel out noise caused by a gate clock in terms of panel design. A pseudo signal line (L2) identical to the gate clock line (L1) of the upper substrate (10) is disposed on the lower substrate (20). Also, the shape of the pseudo signal line is structured by considering the impedance between the level shifter and the shift register.

Additionally, the path of the pseudo signal line L2 is designed to be stable and to compensate for timing dispersion for the gate signal. A dispersion compensation circuit 44 is designed to compensate for the timing of the gate clock signal whose timing is dispersed and delayed from the reference gate signal on the lower substrate 20 and supply it to the gate clock line L1 of the upper substrate 10.

In addition, in the micro LED display device according to one embodiment, in terms of mechanical design, the adhesive and sealant between the upper substrate 10 and the lower substrate 20 are designed to be conductive to function as a ground plane (GND Plane). When routing the upper side, the sealant is designed to be grounded.

In addition, in terms of circuit design, the micro LED display device according to one embodiment is designed to enable supply of an offset signal by generating an inversion circuit for the output of the level shifter within the printed circuit board 40 and the board.

In this way, the micro LED display device according to one embodiment is connected to the upper substrate 10 and the upper substrate 10 on which the micro LED is mounted and the gate clock line L1 to which the gate clock signal is supplied is disposed through routing. and includes a lower substrate 20 on which a base voltage line L3 to which a base voltage is supplied is disposed. A pseudo signal line L2 through which a pseudo signal is supplied to cancel noise generated by the gate clock signal is disposed on the lower substrate 20.

The pseudo signal supplied to the pseudo signal line L2 of the lower substrate 20 may have the same pattern as the inverted signal of the gate clock signal supplied to the gate clock line L1 of the upper substrate 10.

The micro LED display device may further include an inverting circuit (IV1) that supplies a signal obtained by inverting the gate clock signal as a pseudo signal to the pseudo signal line (L2).

The inversion circuit IV1 may be formed on the printed circuit board 40 that generates driving signals of the micro LED.

Alternatively, the inversion circuit IV1 may be mounted on the lower substrate 20 between the printed circuit board 40 that generates driving signals of the micro LED and the pseudo signal line L2.

Considering the slew of the gate clock signal, the termination of the pseudo signal line L2 may be formed in a serpent pattern.

A second gate clock line L1a connected to the gate clock line L1 of the upper substrate 10 may be disposed on the lower substrate 20.

The micro LED display device includes a slew compensation circuit ( 42) may further be included.

The upper substrate 10 and the lower substrate 20 may be connected through routing in the upper side area A1 and routing in the lower side area A2.

A conductive adhesive 30 may be formed between the upper substrate 10 and the lower substrate 20 of the upper side area A1.

The conductive adhesive 30 may be connected to the electromotive voltage electrode 80 of the upper substrate 10 and the base voltage electrode 80 of the lower substrate 10 through the routing 60 of the upper side area A1.

A conductive adhesive 30 and a sealant 50 may be formed between the upper substrate 10 and the lower substrate 20 of the lower side area A2.

The cement 50 may be formed between the conductive adhesive 30 and the routing 60 in the lower side area A2.

The micro LED display device may further include a dispersion compensation circuit 44 that compensates for the timing of a gate clock signal whose timing is dispersed and delayed from the reference gate signal and supplies the timing to the gate clock line L1 of the upper substrate 10.

The dispersion compensation circuit 44 may be provided on the gate clock line L1 of the top glass 10 adjacent to the routing of the upper side area A1. Alternatively, the dispersion compensation circuit 44 may be provided on the pseudo signal line L2 of the lower glass 20 adjacent to the routing of the upper side area A1.

A micro LED display device according to an embodiment includes a first panel, a second panel, and a control circuit (FPGA) that outputs a reference gate signal to the first panel and a gate clock signal with delayed timing to the second panel, , each of the first panel and the second panel includes an upper substrate 10 and a lower substrate 20 connected to the upper substrate 10 through routing. A dispersion compensation circuit 44 is disposed on at least one of the upper substrate 10 and the lower substrate 20 to compensate for the timing of the reference gate signal and the delayed gate clock signal.

According to embodiments, EMI caused by the gate clock signal of the upper substrate 10 can be canceled by designing a pattern and circuit for reducing low-frequency band noise in the lower substrate 20 of the micro LED.

Additionally, a stable voltage supply can be ensured by applying a conductive adhesive 30 between the upper substrate 10 and the lower substrate 20.

In addition, by supplying a phase compensation signal through the lower substrate 20, screen steps due to timing dispersion can be prevented.

Additionally, within the structural limits of the pattern design within the micro LED unit, gate clock EMI can be reduced without interfering with the operation of the light emitting unit.

Additionally, side effects of the timing distribution technology applied to resolve the noise overlap phenomenon can be eliminated.

Additionally, there is an EMI improvement effect due to the arrangement of the ground plane between the upper and lower substrates.

In addition, the ground plane can be expanded by designing the adhesive and sealant materials applied for fixation between the upper substrate 10 and the lower substrate 20 to be conductive.

As described above, the present invention has been described with reference to the illustrative drawings, but the present invention is not limited to the embodiments and drawings disclosed herein, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that transformation can occur. In addition, although the operational effects according to the configuration of the present invention were not explicitly described and explained while explaining the embodiments of the present invention above, it is natural that the predictable effects due to the configuration should also be recognized.

10: upper substrate 20: lower substrate
30: Conductive adhesive 40: Printed circuit board
50: Sealant 60: Routing
70: sealing part 80: EVSS electrode
90: EVSS other signal electrode L1: Gate clock line
L2: pseudo signal line L3: base voltage line
IV1: Inverting circuit 42: Slew compensation circuit
44: Dispersion compensation circuit

Claims (20)

An upper substrate on which a micro LED is mounted and a gate clock line to which a gate clock signal is supplied is arranged; and
a lower substrate connected to the upper substrate through routing and having a base voltage line supplied with a base voltage;
A micro LED display device in which a pseudo signal line for supplying a pseudo signal to cancel out noise generated by the gate clock signal is disposed on the lower substrate. According to claim 1,
The pseudo signal supplied to the pseudo signal line of the lower substrate has the same pattern as the inverted signal of the gate clock signal supplied to the gate clock line of the upper substrate. According to claim 1,
A micro LED display device further comprising an inverting circuit that supplies a signal obtained by inverting the gate clock signal to the pseudo signal line as the pseudo signal. According to claim 3,
The inverting circuit is a micro LED display device formed on a printed circuit board that generates driving signals of the micro LED. According to claim 3,
The inverting circuit is a micro LED display device mounted on the lower substrate between the pseudo signal line and a printed circuit board that generates driving signals of the micro LED. According to claim 1,
A micro LED display device in which termination of the pseudo signal line is formed in a serpent pattern in consideration of slew of the gate clock signal. According to claim 1,
A micro LED display device in which a second gate clock line connected to the gate clock line of the upper substrate is disposed on the lower substrate. According to claim 7,
A micro LED display further comprising a slew compensation circuit that senses the gate clock signal transmitted from the second gate clock line and supplies an inverted signal that compensates for the slew of the gate clock signal to the pseudo signal line as the pseudo signal. Device. According to claim 1,
A micro LED display device wherein the upper substrate and the lower substrate are connected through routing in the upper side area and routing in the lower side area. According to clause 9,
A micro LED display device in which a conductive adhesive is formed between the upper substrate and the lower substrate in the upper side area. According to claim 10,
The conductive adhesive is connected to the electromotive voltage electrode of the upper substrate and the base voltage electrode of the lower substrate through routing in the upper side region. According to clause 9,
A micro LED display device in which a conductive adhesive and an insulating sealant are formed between the upper substrate and the lower substrate in the lower side area. According to claim 12,
The insulating cement is formed between the conductive adhesive and the routing of the lower side area. According to claim 1,
A micro LED display device further comprising a dispersion compensation circuit that compensates for the timing of a gate clock signal whose timing is dispersed and delayed from a reference gate signal and supplies the timing to the gate clock line of the top glass. According to claim 14,
The distributed compensation circuit is
A micro LED display device formed on at least one of the gate clock line and the pseudo signal line. 1st panel;
second panel; and
A control circuit that outputs a reference gate signal to the first panel and a gate clock signal with delayed timing to the second panel,
Each of the first panel and the second panel,
upper substrate and
It includes a lower substrate connected to the upper substrate through routing,
A tiling display device in which a dispersion compensation circuit that compensates for timing of the reference gate signal and the delayed gate clock signal is disposed on at least one of the upper substrate and the lower substrate. According to claim 16,
A micro LED is mounted on the upper substrate, and a gate clock line to which a gate clock signal is supplied is disposed,
A base voltage line connected to the upper substrate through routing and supplied with a base voltage is disposed on the lower substrate, and a pseudo signal line supplied with a pseudo signal to cancel out noise generated by the gate clock signal is disposed. , tiling display device. According to claim 17,
A tiling display device wherein the pseudo signal supplied to the pseudo signal line of the lower substrate has the same pattern as an inverted signal of the gate clock signal supplied to the gate clock line of the upper substrate. According to claim 19,
A tiling display device further comprising an inverting circuit that supplies a signal obtained by inverting the gate clock signal to the pseudo signal line as the pseudo signal. According to claim 17,
The distributed compensation circuit is
A tiling display device provided on at least one of the gate clock line and the pseudo signal line adjacent to the routing of the upper side area.

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