KR20240088538A - Substrate and semiconductor device comprising the same - Google Patents

Abstract

A board with improved power integrity is provided. The substrate includes a first layer including a first power line extending in a first direction and a second power line extending in the first direction; a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction; a first via electrically connecting the first power line and the third power line; and a second via electrically connecting the second power line and the fourth power line, wherein a first voltage is transmitted through the third power line, the first via, and the first power line, and the first voltage is transmitted through the third power line, the first via, and the first power line. A second voltage is transmitted through the 4 power line, the second via, and the second power line.

Description

Substrate and semiconductor device comprising the same}

The present invention relates to a substrate and a semiconductor device including the same.

A processor in a mobile device, where low power and high efficiency characteristics are important, may include a plurality of power domains that are provided with operating voltages at different levels and a plurality of cores installed in each power domain.

Meanwhile, in order to improve heat generation characteristics and timing characteristics, a plurality of cores installed in the same power domain can be arranged to be spaced apart from each other. Since multiple cores are placed spaced apart from each other, the configuration of a power delivery network (PDN) for supplying power to each core may become complicated. In particular, when the power transmission network is configured in the form of a plane, it is difficult to guarantee power integrity (PI) due to various factors even when multiple cores that are spaced apart from each other are connected.

US published patent US 2021/0202387 A1 (published on July 1, 2021)

The technical problem to be solved by the present invention is to provide a substrate with improved power integrity.

Another technical problem to be solved by the present invention is to provide a semiconductor device with improved power integrity.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A substrate according to some embodiments of the present invention for achieving the above technical problem includes: a first layer including a first power line extending in a first direction and a second power line extending in the first direction; a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction; a first via electrically connecting the first power line and the third power line; and a second via electrically connecting the second power line and the fourth power line, wherein a first voltage is transmitted through the third power line, the first via, and the first power line, and the first voltage is transmitted through the third power line, the first via, and the first power line. A second voltage is transmitted through the 4 power line, the second via, and the second power line.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a first power line extending in a first direction and transmitting a first voltage, and a first power line extending in the first direction and transmitting a second voltage. a first layer including a second power line for; a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction; a first via electrically connecting the first power line and the third power line; and a second via electrically connecting the second power line and the fourth power line, a first bump installed on the upper surface of the first layer and electrically connected to the first power line, and the first bump electrically connected to the first power line. 2 and a second bump electrically connected to the power line, wherein the first layer further includes a fifth power line for transmitting the first voltage, wherein the first power line, the second power line and the The fifth power line is sequentially arranged in a line along the first direction, the first power line and the fifth power line are connected to each other through a connection line, and the connection line connects the second power line. It has a curved shape to avoid, the first power line is disposed on one side of the fifth power line, and a capacitor (die-side capacitor) is disposed on the other side of the fifth power line, and the capacitor is disposed on the fifth power line. A power line is electrically connected to the first power line through the connection line.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a board having distinct first and second regions defined; a semiconductor package disposed on the first area; and a power management chip disposed on the second area, wherein the semiconductor package operates using different first powers and second voltages, and the power management chip operates using the first voltage, The board includes a first layer including a first power line extending in a first direction and a second power line extending in the first direction, and a second layer located below the first layer and different from the first direction. A second layer including a third power line extending in two directions and a fourth power line extending in the second direction, a first via electrically connecting the first power line and the third power line, and , includes a second via electrically connecting the second power line and the fourth power line, a first voltage is transmitted through the third power line, the first via, and the first power line, and the first voltage is transmitted through the third power line, the first via, and the first power line. A second voltage is transmitted through the 4 power line, the second via, and the second power line.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention.
FIG. 2 is a cross-sectional view for explaining the semiconductor device of FIG. 1.
Figure 3 is a perspective view illustrating a power transmission network installed on a substrate according to some embodiments of the present invention.
FIG. 4 is a plan view for explaining the first layer (L1) of FIG. 3.
FIG. 5 is a plan view for explaining the second layer (L2) of FIG. 3.
6 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention.
Figure 7 is a perspective view illustrating a power transmission network installed on a substrate according to some embodiments of the present invention.
8 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention.
Figure 9 is a perspective view illustrating a power transmission network installed on the board of a semiconductor device according to some embodiments of the present invention.
10 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
FIG. 11 is a plan view showing the first layer of the power transmission network implemented on the substrate shown in FIG. 10.
FIG. 12 is a diagram for explaining the arrangement of a plurality of cores in the plan view of FIG. 11.
FIG. 13 is a plan view showing another example of the first layer of the power transmission network implemented on the substrate shown in FIG. 10.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 1, the processor chip 10 may include a plurality of power domains 11a and 15a. The first power domain 11a receives a first operating voltage, and the second power domain 15a receives a second operating voltage different from the first operating voltage.

The processor chip 10 is disposed on a substrate (i.e., package substrate) 20. Through the substrate 20, a first operating voltage is provided to the first power domain 11a and a second operating voltage is provided to the second power domain 15a.

The processor chip 10 is used as an example as a chip disposed on the substrate 20, but the present invention is not limited thereto.

FIG. 2 is a cross-sectional view for explaining the semiconductor device of FIG. 1.

Referring to FIG. 2, a processor chip 10 is disposed on the upper surface of the substrate 20, and the substrate 20 and the processor chip 10 are connected through a bump BP. A ball (or external connection terminal) BL is disposed on the lower surface of the substrate 20. Instead of the bump (BP) or ball (BL), other types of members capable of electrical connection may be used.

Inside the substrate 20, a power transmission network (PDN) is configured to provide different operating voltages to a plurality of power domains (eg, 11a and 15a). In some embodiments, some layers of the power transmission network may be configured as a weave type rather than a plane type. The power transmission network may include a plurality of layers (L1, L2, L3), and the extension direction of the conductive lines (111, 121, 112, 122, 113, 131) disposed in one layer (for example, L1) (eg, Y direction) and the extension direction (eg, X direction) of the conductive line 211 disposed in another immediately adjacent layer (eg, L2) may be different. The bottom layer (eg, L3) may be in the form of a plane (P1), but is not limited to this.

The conductive lines 111, 112, and 113, the conductive lines 121 and 122, and the conductive line 131 transmit different voltages. For example, a first voltage may be connected to the conductive lines 111, 112, and 113, a ground voltage may be connected to the conductive lines 121 and 122, and a second voltage may be connected to the conductive line 131. Here, the conductive lines 111, 112, and 113 may be called a first power line, the conductive line 131 may be called a second power line, and the conductive lines 121 and 122 may be called a ground line.

In this case, the conductive lines 111, 112, and 113 disposed on the layer L1, the conductive line 211 disposed on the layer L2, and the play P1 may be electrically connected to each other.

Additionally, the conductive lines 121 and 122 disposed on the layer L1 are not electrically connected to the conductive line 211 and the plane P1. For example, the conductive lines 121 and 122 may pass through the hole H1 formed in the plane P1 and be connected to the ball BL through a via.

Additionally, the conductive line 131 disposed on the layer L1 is not electrically connected to the conductive line 211 and the plane P1. For example, the conductive line 131 may be formed in the plane P1, pass through the hole H2, and be connected to the ball BL through a via.

The configuration of the weave-type power transmission network will be described in detail later using FIGS. 3 to 13.

Figure 3 is a perspective view illustrating a power transmission network installed on a substrate according to some embodiments of the present invention. FIG. 4 is a plan view for explaining the first layer (L1) of FIG. 3. FIG. 5 is a plan view for explaining the second layer (L2) of FIG. 3.

Referring to Figures 3 to 5, the power transmission network includes a plurality of layers (L1, L2, L3).

The first layer (L1) extends in the first direction (Y) and includes a plurality of conductive lines (111, 121, 112, 122, and 131) that are parallel to each other.

Among the plurality of conductive lines 111, 121, 112, 122, and 131, the power lines 111 and 112 transmit a first voltage, the power line 131 transmits a second voltage, and the ground lines 121 and 122 ) carries the ground voltage (VSS). The second voltage is different from the first voltage and may be a ground voltage, but is not limited thereto.

A ground line 121 is disposed between adjacent power lines (for example, 111 and 112), and a ground line 122 is disposed between other adjacent power lines (for example, 112 and 131).

The second layer L2 extends in the second direction (X) and includes a plurality of conductive lines 211, 212, 213, 221, and 222 that are parallel to each other. The second direction (X) and the first direction (Y) may be orthogonal to each other, but are not limited thereto.

Among the plurality of conductive lines 211, 212, 213, 221, and 222, the power lines 211, 212, and 213 transmit the first voltage, and the ground lines 221 and 222 transmit the ground voltage VSS. A ground line 221 is disposed between adjacent power lines (for example, 211 and 212), and a ground line 222 is disposed between other adjacent power lines (for example, 212 and 213).

A plane (P1) may be formed in the third layer (L3), but is not limited to this. The plane P1 is connected to the first voltage.

Between the first layer (L1) and the second layer (L2), vias (V11, V12, V13, V14, and V15) are disposed. Vias V21, V22, and V23 are disposed between the second layer (L2) and the third layer (L3).

The power line (e.g., 211) of the second layer (L2) is electrically connected to at least one power line (e.g., 111, 112) in the first layer (L1) through the vias (V11 and V12). It is connected to Additionally, the power line (eg, 211) of the second layer (L2) is connected to the plane (P1) through vias (V21 and V22). Therefore, the first voltage applied through the ball is transmitted to the process chip 10 disposed on the upper surface of the substrate 20 through the vias V21 and V22, the power line 211, and the vias V11, V12, and V13. do.

Therefore, the first voltage applied through the ball is transmitted to the process chip 10 disposed on the upper surface of the substrate 20 through the vias V21 and V22, the power line 211, and the vias V11, V12, and V13. It can be. Vias (V21, V22), power lines 211, vias (V11, V12, V13), etc. constitute a power transmission network for transmitting the first voltage.

The ground line (for example, 221) of the second layer (L2) is electrically connected to at least one ground line (for example, 121 and 122) in the first layer (L1) through the vias (V14 and V15). It is connected to Additionally, the ground line (eg, 221) of the second layer (L2) is connected to the ball through the via (V23) penetrating the hole (H1) of the plane (P1).

Therefore, the ground voltage (e.g., VSS) applied through the ball is connected to the process chip 10 disposed on the upper surface of the substrate 20 through the via V23, the power line 221, and the vias V14 and V15. can be passed on. Vias (V23), power lines (221), vias (V14, V15), etc. constitute a power transmission network for transmitting ground voltage.

As such, according to some embodiments, each layer (e.g., L1) has conductive lines (e.g., 111, 121, 112, 122) connected to different voltages (first voltage, second voltage, ground voltage). , 131) is placed. Therefore, in order to prevent them from short-circuiting each other, the conductive lines (eg, 111, 121, 112, 122, and 131) extend in one direction (eg, the first direction (Y)).

In addition, conductive lines (e.g., 211, 212, 213, 221, 222) disposed in another layer (e.g., L2) immediately adjacent to a layer (e.g., L1) are connected in the one direction (e.g. , extends in a direction different from the first direction (Y) (for example, the second direction (X)).

By varying the extension direction (e.g., first direction (Y), second direction (X)) of the conductive lines formed in adjacent layers (e.g., L1, L2), the conductive lines formed in adjacent layers are formed in a weave ( It becomes a weave shape. By designing the power transmission network in a weave shape like this, a path for transmitting power can be easily designed. In other words, the design difficulty can be lowered.

Additionally, during the design process, when a plurality of bumps BP connected to the same voltage must be placed, there may be bumps placed separately. For example, in FIG. 3, bumps connected to the first voltage are mainly located on the left side of FIG. 3, and the bump BP1 is located at the right corner.

When designing a power transmission network, if each layer is configured in the form of a plane, these bumps BP1 are connected to the corresponding plane with a very thin line. Accordingly, the resistance and inductance from the corresponding ball to the bump BP1 become significantly higher, making the power integrity of the bump BP1 vulnerable.

However, when the power transmission network is designed in a weave shape, as in some embodiments, the bump BP1 is not directly connected to the conductive line disposed in the first layer L1, but is connected to the second layer through the via V13. It may be directly connected to the conductive line 211 disposed in (L2). Therefore, the resistance and inductance from the corresponding ball to the bump BP1 do not increase. Compared to other bumps, the power integrity of bump (BP1) is not compromised.

Additionally, matching the placement of balls installed on the bottom of the substrate to the placement of bumps in the corresponding domain helps maintain power integrity characteristics. That is, when viewed in the third direction (Z), arranging the ball and the bump to overlap helps maintain power integrity characteristics. However, as the performance of the process chip increases, the number of bumps increases and the spacing between bumps becomes significantly closer, so it is difficult to match the arrangement of the balls to the arrangement of the bumps. Here, if the power transmission network is designed in a plane shape, depending on the arrangement of other power sources and signals, there may be a ball that receives power independently (i.e., a single power ball). Such a single power ball makes it difficult to design a power transmission network and causes the number of stacked layers to increase. However, if the power transmission network is designed in a weave shape, it becomes easier to connect the bumps, making it easier to collect and place the balls in the desired location. The possibility of the existence of a standalone power ball is reduced.

Meanwhile, in the first layer (L1), the conductive line 131 for transmitting the second voltage is connected to the ball through vias (V31 and V32). The vias V31 and V32 may pass through the hole H2 of the plane P1 and be connected to the ball. As shown, there may be no conductive lines in contact with the vias V31 and V32 in the second layer L2. Unlike what is shown, a separate conductive line may exist in the second layer (L2).

6 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the description will focus on differences from those described using FIG. 1.

Referring to FIG. 6, the processor chip 10 may include a plurality of power domains 11a, 15a, and 11b. The first power domains 11a and 11b receive a first operating voltage, and the second power domain 15a receives a second operating voltage different from the first operating voltage.

The processor chip 10 is disposed on a substrate (i.e., package substrate) 20. Through the substrate 20, a first operating voltage is provided to the first power domains 11a and 11b, and a second operating voltage is provided to the second power domain 15a.

Figure 7 is a perspective view illustrating a power transmission network installed on a substrate according to some embodiments of the present invention. For convenience of explanation, differences from those described using FIGS. 3 to 5 will be mainly explained.

The power transmission network shown in FIG. 3 consists of three layers, while the power transmission network shown in FIG. 7 consists of four layers. The power transmission network may be implemented with five or more layers, or the power transmission network may be implemented with two layers.

Referring to FIG. 7, the power transmission network includes a plurality of layers (L1, L2, L3, and L4).

The first layer (L1) extends in the first direction (Y) and includes a plurality of conductive lines (111, 121, 112, 122, 131, 123, 132, 113, 124, and 114) that are parallel to each other.

Among the plurality of conductive lines (111, 121, 112, 122, 131, 123, 132, 113, 124, 114), the power lines (111, 112, 113, 114) transmit the first voltage, and the power lines (131, 132) delivers a second voltage different from the first voltage, and the ground lines 121, 122, 123, and 124 deliver a ground voltage (VSS). A ground line 121 is disposed between adjacent power lines (for example, 111 and 112), and a ground line 123 is disposed between other adjacent power lines (for example, 131 and 132).

The second layer L2 extends in the second direction (X) and includes a plurality of conductive lines 211, 212, 213, 221, 222, 231, and 232 that are parallel to each other.

Among the plurality of conductive lines (211, 212, 213, 221, 222, 231, 232), the power lines (211, 212, 213) transmit the first voltage, and the power lines (231, 232) transmit the second voltage. And the ground lines 221 and 222 transmit the ground voltage (VSS). A ground line 221 is disposed between adjacent power lines (for example, 211 and 212), and a ground line 222 is disposed between other adjacent power lines (for example, 212 and 213).

The third layer L2 extends in the first direction Y and includes a plurality of conductive lines 311, 321, 312, 322, 331, 321, 332, 313, 324, and 314 that are parallel to each other.

Among the plurality of conductive lines (311, 321, 312, 322, 331, 321, 332, 313, 324, 314), the power lines (311, 312, 313, 314) transmit the first voltage, and the power lines (331, 332) transmits the second voltage, and the ground lines 321, 322, 323, and 324 transmit the ground voltage (VSS). A ground line 321 is disposed between adjacent power lines (for example, 311 and 312), and a ground line 323 is disposed between other adjacent power lines (for example, 331 and 332).

Planes (P1, P2, P3) may be formed in the fourth layer (L4), but are not limited thereto. Planes (P1, P3) are connected to the first voltage, and plane (P2) is connected to the second voltage. A ball may be installed at the bottom of the plane (P1, P2, P3) to receive power from the outside or input/output a signal. The planes P1, P2, and P3 may be installed at the same level (or at the same height).

A via (eg, V11) is disposed between the first layer (L1) and the second layer (L2). A via (e.g., V21) is disposed between the second layer (L2) and the third layer (L3), and a via (e.g., V21) is disposed between the third layer (L3) and the fourth layer (L4). V31) is deployed.

For example, the first voltage is applied to the ball under the substrate 20, the plane (P1) and via (V31) of the fourth layer (L4), the power line 311 of the third layer (L3), and the via (V21). ), may be provided to the processor chip 10 through the power lines 211, 212, and 213 of the second layer, the via (V11), and the power line 111 of the first layer.

For another example, the second voltage is applied to the ball under the substrate 20, the plane (P2) and via (V32) of the fourth layer (L4), the power line 331 of the third layer (L3), and the via ( V22), the power lines 231 and 232 of the second layer, the via (V12), and the power line 131 of the first layer may be provided to the processor chip 10.

As shown in FIG. 6, in the processor chip 10, first domains 11a and 11b are spaced apart from each other by a second domain 15a. Even in this case, as shown in FIG. 7, the bumps BP disposed in the first domains 11a and 11b spaced apart from each other form a conductive line (e.g., 211) extending long in the second direction (X). , 212, 213, 221, 222) can be electrically connected to each other. Therefore, power integrity is increased.

1 to 7 illustrate the power transmission network applied to the substrate (package substrate), and below, the power transmission network applied to the board is described. The design principles of the power transmission network applied to the substrate and the design principle of the power transmission network applied to the board are similar.

8 is a conceptual diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, differences from those described using FIGS. 1 to 7 will be mainly explained.

Referring to FIG. 8 , a semiconductor device according to some embodiments of the present invention includes a board 30, semiconductor packages 10 and 20, and a power management chip 40.

The board 30 includes a first region (R1) and a second region (R2) that are distinct from each other. Semiconductor packages 10 and 20 are installed in the first region R1 of the board 30. The semiconductor packages 10 and 20 include a substrate 20 and a processor chip 10 installed thereon. A power management chip 40 is installed in the second region R2 of the board 30.

The semiconductor packages 10 and 20 may operate using different first and second voltages, and the power management chip 40 may operate using the first voltage.

Figure 9 is a perspective view illustrating a power transmission network installed on the board of a semiconductor device according to some embodiments of the present invention. For convenience of explanation, differences from those described using FIGS. 3 to 5 will be mainly explained.

Although the power transmission network shown in FIG. 9 is composed of five layers (L1, L2, L3, L4, and Ln), it is not limited to this.

The first layer (L1) extends in the first direction (Y) and includes a plurality of conductive lines (B111, B121, B112, B122, B131, B123, B132, and B113) that are parallel to each other.

Among the plurality of conductive lines (B111, B121, B112, B122, B131, B123, B132, B113), the power lines (B111, B112, B113) transmit the first voltage, and the power lines (B131, B132) transmit the first voltage. A second voltage different from that is transmitted, and the ground lines (B121, B122, and B123) transmit a ground voltage (VSS).

The second layer (L2) extends in the second direction (X) and includes a plurality of conductive lines (B211, B212, B213, B221, and B222) that are parallel to each other.

Among the plurality of conductive lines (B211, B212, B213, B221, B222, B231), the power line (B211, B212, B213) transmits the first voltage, the power line (B231) transmits the second voltage, and the ground line (B221, B222) carries the ground voltage (VSS). The power lines B211, B212, and B213 extend across the first area (R1 in FIG. 8) and the second area (R2 in FIG. 8).

The third layer (L3) is formed with a plane (P31). The plane (P31) is connected to the second voltage. The plane P31 is connected to the power line B231 of the second layer L2 and the power lines B131 and B132 of the first layer L1 through a via.

The fourth layer (L4) is formed with a plane (P41). Plane (P41) is connected to ground voltage.

The fifth layer (Ln) is formed with a plane (P51). The plane (P51) is connected to the first voltage. The fifth layer Ln is installed over the first area (R1 in FIG. 8) and the second area (R2 in FIG. 8).

In FIG. 8, the semiconductor packages 10 and 20 receive first and second voltages, and the power management chip 40 receives the first voltage. Therefore, in the power transmission network configuration shown in FIG. 9, the first voltage is transmitted to the semiconductor package 10 through the plane P51 disposed in the first region (R1 in FIG. 8) and the second region (R2 in FIG. 8). 20) and a power management chip 40. In addition, power lines B211, B212, and B213 extending in the second direction (X) to cross the first region (R1) and the second region (R2) are formed in the second layer (L2), (B211, B212, B213) are connected to the plane (P51) through a via. The power line B113 is formed in the second region R2 and is connected to the power lines B211, B212, and B213 through a via. This configuration can reduce power integrity.

10 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the description will focus on differences from those described using FIGS. 1, 6, and 8.

Referring to FIG. 10, the processor chip 10 includes a first processor (CPU1) and a second processor (CPU2). The first processor (CPU1) is included in the first power domain (see 11a in FIG. 1), and the second processor (CPU2) is included in the second power domain (see 15a in FIG. 1).

For example, the first processor (CPU1) may be a high-performance processor that consumes a lot of power, and the second processor (CPU2) may be a low-performance processor that consumes little power. As shown, the first processor (CPU1) includes a plurality of cores (11, 12, 13, and 14), and the second processor (CPU2) also includes a plurality of cores (15, 16, 17, and 18). .

Considering heat generation characteristics and timing characteristics, the plurality of cores 11, 12, 13, and 14 may be arranged to be spaced apart from each other within the first power domain 11a.

Additionally, each core (eg, 15) of the second processor (CPU2) may be disposed in the space between adjacent cores (eg, 11 and 12) of the first processor (CPU1). Each core (eg, 16) of the second processor (CPU2) may be placed in the space between adjacent cores (eg, 11 and 13) of the first processor (CPU1).

The processor chip 10 is disposed on a substrate (i.e., package substrate) 20. Through the substrate 20, a first operating voltage is provided to the first power domain (11a in FIG. 1), and a second operating voltage is provided to the second power domain (15a in FIG. 1).

FIG. 11 is a plan view showing the first layer of the power transmission network implemented on the substrate shown in FIG. 10. FIG. 12 is a diagram for explaining the arrangement of a plurality of cores in the plan view of FIG. 11.

First, referring to FIG. 11, in the first layer, the area where the first power domain 11a is implemented may be divided into four separate zones 11a_1, 11a_2, 11a_3, and 11a_4. The area where the second power domain 15a is implemented is located in the space between the separated areas 11a_1, 11a_2, 11a_3, and 11a_4 of the first power domain 11a.

As shown, if the four areas (11a_1, 11a_2, 11a_3, 11a_4) of the first power domain 11a are arranged in the upper left, upper right, lower left, and lower right respectively, the area where the second power domain 15a is implemented is It may be a “+” shape.

In the first area 11a_1, a power line PL1 extending in the first direction Y is formed. In the second area 11a_2, a power line PL3 extending in the first direction Y is formed. In the second power domain 15a disposed between the first zone 11a_1 and the second zone 11a_2, a power line PL2 extending in the first direction Y is formed. The power lines PL1 and PL3 transmit a first voltage, and the power line PL2 transmits a second voltage.

Power line PL1, power line PL2, and power line PL3 are arranged in order. The power line PL1, PL2, and PL3 are arranged in a row along the first direction Y. As shown, the power line PL1, PL2, and PL3 may be substantially arranged on one straight line.

In this case, the power line PL1 and the power line PL3 are electrically connected by the connection line CPL1. The connection line CPL1 has a meandering shape to avoid being short-circuited with the power line PL2.

As described above, the second power domain 15a is located between the first zone 11a_1 and the third zone 11a_3 of the first power domain 11a. The power line PL1 disposed in the first zone 11a_1, the power line PL5 disposed in the third zone 11a_3, and the power line PL4 disposed in the second power domain 15a are connected to each other. They are parallel and spaced apart in the second direction (X) and extend in the first direction (Y).

Additionally, in the first area 11a_1 of the first power domain 11a, there are a plurality of power lines PL1 extending in the first direction (Y), and the plurality of power lines PL1 extend in the second direction (X). are placed in parallel and spaced apart. Although not separately shown, a ground line is disposed in the space between adjacent power lines PL1 (for example, refer to reference numeral 99). The ground line may extend along the first direction (Y). In each of the other areas 11a_2, 11a_3, and 11a_4 of the first power domain 11a, a ground line extending in the first direction Y may be disposed between adjacent power lines PL3, PL5, and PL6. .

Also in the second power domain 15a, a ground line extending in the first direction (Y) may be disposed between adjacent power lines (eg, PL2).

In addition, between the power line (eg, PL1) installed in the first power domain 11a and the power line (eg, PL4) installed in the second power domain 15a, it extends in the first direction (Y). A ground line may be placed.

Here, referring to FIG. 12, a first processor (CPU1) is disposed in the first power domain 11a, and a second processor (CPU2) is disposed in the second power domain 15a.

Cores 11, 12, 13, and 14 of the first processor (CPU1) are disposed in each of the spaced apart regions (11a_1, 11a_2, 11a_3, and 11a_4 in FIG. 11) of the first power domain 11a. In other words, core 11 is disposed on power line PL1, core 12 is disposed on power line PL3, core 13 is disposed on power line PL5, and core 12 is disposed on power line PL5. (14) is placed on the power line PL6.

Cores 15, 16, 17, and 18 of the second processor (CPU2) are respectively arranged in the second power domain 15a located in the space between adjacent areas (11a_1, 11a_2, 11a_3, and 11a_4 in FIG. 11). do. For example, the core 15 may be placed on the power line PL2 and the core 16 may be placed on the power line PL4.

FIG. 13 is a plan view showing another example of the first layer of the power transmission network implemented on the substrate shown in FIG. 10. For convenience of explanation, differences from those described using FIGS. 10 to 12 will be mainly explained.

In the first layer shown in FIG. 13, the first region 11a_1 is located on one side of the second region 11a_2 of the first power domain 11a, and a capacitor (die-side) is located on the other side of the second region 11a_2. capacitors (ODC1, ODC2) are placed. Alternatively, the third zone 11a_3 is located on one side of the fourth zone 11a_4 of the first power domain 11a, and the capacitors ODC1 and ODC2 are disposed on the other side of the fourth zone 11a_4.

As described above, the cores 11, 12, 13, and 14 of the first processor (CPU1) are disposed in each of the spaced apart regions 11a_1, 11a_2, 11a_3, and 11a_4 of the first power domain 11a. do.

In the first layer (L1), the power line (PL1) of the first zone (11a_1) and the power line (PL3) of the second zone (11a_2) are connected to the connection line (CPL1), and the power line (PL3) of the third zone (11a_3) is connected to the first layer (L1). The power line PL5 and the power line PL6 of the fourth area 11a_4 are connected by a connection line. In addition, a plurality of power lines PL1, PL3, PL5, and PL6 formed in the first power domain 11a in the first layer are arranged in parallel. A plurality of power lines (PL1, PL3, PL5, PL6) arranged in parallel are connected to the plate 600 on which the capacitors (ODC1, ODC2) are arranged.

In other words, the power line PL1 is disposed on one side of the power line PL3, the capacitors ODC1 and ODC2 are disposed on the other side of the power line PL3, and the capacitors ODC1 and ODC2 are disposed on the power line PL3. ), is also electrically connected to the power line (PL1) through the connection line (CPL1).

A power line (PL5) is disposed on one side of the power line (PL6), and capacitors (ODC1, ODC2) are disposed on the other side of the power line (PL6), and the capacitors (ODC1, ODC2) are connected to the power line (PL6) and the connection line. It is also electrically connected to the power line (PL5).

Therefore, not only the cores 12 and 14 close to the capacitors ODC1 and ODC2, but also the cores 11 and 13 far away from the capacitors ODC1 and ODC2 can fully receive the effect of the capacitors ODC1 and ODC2.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: Processor chip
11a: first power domain
15a: second power domain
20; Substrate (or package substrate)
30: board
40: Power management chip
L1, L2, L3, L4, Ln: Layers
111, 112, 131: Power lines
121, 122: Ground line

Claims (10)

A first layer including a first power line extending in a first direction and a second power line extending in the first direction;
a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction;
a first via electrically connecting the first power line and the third power line; and
Includes a second via electrically connecting the second power line and the fourth power line,
A substrate where a first voltage is transmitted through the third power line, the first via, and the first power line, and a second voltage is transmitted through the fourth power line, the second via, and the second power line. . According to clause 1,
The substrate is installed on the upper surface of the first layer and further includes a first bump electrically connected to the first power line, and a second bump electrically connected to the second power line. According to clause 1,
Includes a first plane located below the second layer,
A first ball electrically connected to the third power line through a third via is installed on the lower surface of the first plane. According to clause 1,
The first layer further includes a fifth power line extending in the first direction,
Further comprising a second plane located below the second layer, separated from the first plane, and installed at the same level as the first plane,
A second ball electrically connected to the fifth power line is installed on the lower surface of the second plane. According to clause 1,
The first layer extends in the first direction and further includes a first ground line disposed between the first power line and the second power line. According to clause 1,
The first layer further includes a sixth power line for transmitting the first voltage,
The first power line, the second power line, and the sixth power line are arranged in a line along the first direction in that order. According to clause 6,
The first layer further includes an eighth power line extending in the first direction and transmitting the first voltage, and a ninth power line extending in the first direction and transmitting the second voltage. do,
The first power line, the ninth power line, and the eighth power line are arranged in parallel and spaced apart in a second direction. According to clause 7,
On the first layer, a first core, a second core, and a third core belonging to the first processor and spaced apart from each other are disposed,
The first core is disposed on the first power line, the second core is disposed on the sixth power line, and the third core is disposed on the eighth power line. A first layer including a first power line extending in a first direction and transmitting a first voltage, and a second power line extending in the first direction and transmitting a second voltage;
a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction;
a first via electrically connecting the first power line and the third power line; and
Includes a second via electrically connecting the second power line and the fourth power line,
Installed on the upper surface of the first layer, it includes a first bump electrically connected to the first power line, and a second bump electrically connected to the second power line,
The first layer further includes a fifth power line for transmitting the first voltage,
The first power line, the second power line, and the fifth power line are sequentially arranged in a line along the first direction,
The first power line and the fifth power line are connected to each other through a connection line, and the connection line has a curved shape to avoid the second power line,
The first power line is disposed on one side of the fifth power line, and a capacitor (die-side capacitor) is disposed on the other side of the fifth power line,
The capacitor is electrically connected to the fifth power line and the first power line through the connection line. A board on which distinct first and second areas are defined;
a semiconductor package disposed on the first area; and
Includes a power management chip disposed on the second area,
The semiconductor package operates using different first powers and second voltages, and the power management chip operates using the first voltage,
The board is
A first layer including a first power line extending in a first direction and a second power line extending in the first direction;
a second layer located below the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction;
a first via electrically connecting the first power line and the third power line;
Includes a second via electrically connecting the second power line and the fourth power line,
A semiconductor device in which a first voltage is transmitted through the third power line, the first via, and the first power line, and a second voltage is transmitted through the fourth power line, the second via, and the second power line. .

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