KR20240076869A - Neuron circuit using voltage change of bit line - Google Patents

Abstract

The present invention relates to a neuron circuit using the voltage change of a bit line. At the end of each bit line of a synapse array, two or more n latches are connected in parallel through an inverter and a data transmission transistor to control the synapse with an EN signal. The current flowing through the bit line with the input pulse of the array can be converted into n bits of digital voltage data and stored in n latches. This makes it possible to replace the previously used TIA and ADC circuits, making it possible to construct a digital conversion circuit relatively simply and reducing the required area.

Description

Neuron circuit using voltage change of bit line {NEURON CIRCUIT USING VOLTAGE CHANGE OF BIT LINE}

The present invention relates to a neuron circuit coupled to a synapse array. More specifically, the intensity of the current flowing in each bit line of the array varies depending on the input pulse applied to the word line of the synapse array, which is converted into digital voltage data 2 It is about a neuron circuit that stores data in one or more latches.

The current computing system based on the von Neumann architecture solves data sequentially as it is input, eliminating the von Neumann bottleneck and memory wall problem caused by data movement between the CPU and memory units. Have. To solve this problem, research on neuromorphic systems has been actively conducted recently.

As a neuromorphic system, a deep neural network with one or more hidden layers is mainly used, as shown in Figure 1. In this case, the input signal in the form of a vector is applied in parallel to all input layers, and the vector-matrix multiplication operation of the synaptic weight matrix is performed simultaneously on an analog basis. The biggest feature of neuromorphic is that it imitates the human brain, which operates in parallel with a sequential processing computer, allowing memory and computation to proceed simultaneously in large quantities.

Figure 2 shows the structure of a basic neuromorphic system. Depending on the voltage applied to the word line (WL), bit line (BL), and source line (SL) of the synapse array, current flows differently in each synapse element, and the size of the current summed to BL is determined accordingly. The vector-matrix multiplication operation is performed by summing the currents with BL. The corresponding current of each BL is applied as an input to the neuron circuit and goes through a conversion process, such as TIA and ADC, as shown in Figure 5, which will be described later, to determine the final digital output.

Figure 3 shows the structure of a memory system that is currently being commercialized. Control Logic receives the command (CMD), input data (DATA_EX), and cell address (ADD) of the memory cell array through the input/output device (I/O), and based on this, the row decoder , page buffer, etc. are controlled.

FIG. 4 shows the arrangement and brief operation of the page buffer used in the memory system structure of FIG. 3. One page buffer (PB) is connected to every BL in the memory array, and C _SO is generated in the SO node due to the parasitic capacitor of the BL in the page buffer. In the process of reading data, the voltage of C _SO due to the STRING current (I _CELL ) changes depending on the state of the data stored in the memory cell for which a read operation is desired. At this time, depending on the operation of the memory, if the threshold voltage (V _TH ) of the memory cell for which a read operation is desired becomes greater than the voltage applied to the word line, the cell current does not flow, so the SO node remains 'high', and V _TH is If it is lower than the voltage applied to , the SO node becomes 'low' due to cell current. This change in voltage at the SO node is detected in the page buffer and data is read. However, a technology to digitally change the voltage change of the bit line in the synapse array and store it in a neuron circuit using the operating principle of the memory array described above has not yet been proposed.

In the existing neuron circuit, as shown in Figure 5, the current summed through the vector-matrix multiplication operation is converted from analog current to analog voltage through TIA (Trans Impedence Amplifier), and this is converted into analog voltage through ADC (Analog-to-Digital Converter). Through this, the analog voltage is converted to digital voltage and the final digital output is determined. Therefore, the existing neuron circuit has the problem of requiring complex and relatively large TIA and ADC circuits.

Accordingly, the present invention seeks to provide a relatively simple and small-area neuron circuit by replacing the conventionally used TIA and ADC circuit with a circuit that uses the page buffer of a memory system.

In order to achieve the above object, the neuron circuit according to the present invention includes an inverter connected to a first contact point where a transistor for supplying V _DD is connected to the bit line of the synapse array; A data transfer transistor whose gate is connected to the output terminal of the inverter; two or more n latches connected in parallel to a second contact point to which the drain of the data transfer transistor is connected; and an EN Pulse Train that generates n EN signals input to the n latches in at least 2 ⁿ -1 pairs.

The data transfer transistor may be an NMOS whose source is connected to ground.

The n latches may convert the analog current flowing through the bit line into n-bit digital voltage data by the EN signal and store it.

The n latches are each a latch signal input transistor with one end connected to the second contact point, a reset signal input transistor with one end connected to ground, and disposed in opposite directions between the latch signal input transistor and the other end of the reset signal input transistor. It is configured to include two inverters connected in parallel, wherein the n latches have n output terminals with the other terminal of the latch signal input transistor as the output terminal of each latch, and the n output terminals are connected to the input terminal of the integrated AND gate. are connected to each other, the output terminal of the integrated AND gate is connected to each input terminal of the n separate control AND gates, and each input terminal of the n separate control AND gates is provided to be input together with one of the n EN signals, Another feature of the neuron circuit according to the present invention is that each output terminal of the n separate control AND gates is connected to the gate of one latch signal input transistor among the n latches.

The V _DD supply transistor is a PMOS connected to the V _DD supply terminal and the first contact point to apply a precharge (PCHn) signal to the gate, and a voltage sensing switch controlled by a SENS signal is installed at one end of the bit line. connected to the contact point, and C _SO due to the parasitic capacitance of the bit line between the first contact point and ground is Another feature of the neuron circuit according to the present invention is that the latch signal input transistor is an NMOS through which a latch signal (LAT) is input to the gate, and the reset signal input transistor is an NMOS through which a reset signal (RST) is input into the gate. Do this.

The method of operating a neuron circuit according to the present invention relates to a method of operating the above-described neuron circuit, and turns on the PMOS by applying a negative precharge (PCHn) signal to the V _DD supply transistor to connect the first contact to V To _DD Precharging and simultaneously applying a positive reset signal (RST) to each reset signal input transistor of the n latches to initialize all of the n output terminals to a data "1"state; applying V _DD as a SENS signal to the voltage sensing switch to sense a change in voltage of the precharged first contact; And in the EN Pulse Train, n EN signals are generated in 2 ⁿ -1 pairs and applied as a latch signal to each latch signal input transistor of the n latches, so that the initial data of the n output terminals of the n latches is "1". Characterized by converting the analog current flowing through the synapse array through the first contact into n-bit digital voltage data and storing it depending on whether the state changes.

The n EN signals may be controlled to be generated when the data transfer transistor is turned on, for example, by the SOn node 21, which will be described later.

The n EN signals can be controlled so that 2 ⁿ -1 pairs are generated in the EN Pulse Train in a predetermined order after the SENS signal is applied to the voltage sensing switch.

The neuromorphic circuit according to the present invention is characterized in that the above-described neuron circuit is connected to each bit line of the synapse array.

The method of operating a neuron circuit according to the present invention relates to a method of operating a neuron circuit in the above-described neuromorphic circuit, where the summation of a plurality of pulses according to time applied as input to the synapse array is a typical vector-matrix. It is characterized by a multiplication operation or a method of summing the n-bit digital voltage data of the pulse according to the input time of the synapse array by shifting the number of digits to the left by the input time as a weight.

The present invention is equipped to control with an EN signal by connecting two or more n latches in parallel through an inverter and a data transfer transistor at the end of each bit line of the synapse array, so that the current flowing in the bit line with the input pulse of the synapse array is n bit. It can be converted into digital voltage data and stored in n latches. This makes it possible to replace the previously used TIA and ADC circuits, making it possible to construct a digital conversion circuit relatively simply and reducing the required area.

Figure 1 is a conceptual diagram showing the vector-matrix product of a deep neural network structure and a synaptic weight matrix.
Figure 2 is a conceptual diagram of a synapse array and neuron circuit for neuromorphic implementation.
3 is a structural diagram of a memory system.
FIG. 4 is a conceptual diagram of the arrangement and simple operation method of the page buffer used in the memory system structure of FIG. 3.
Figure 5 is a conceptual diagram showing a conventional neuron circuit structure.
Figure 6 is a conceptual diagram showing the page buffer-based neuron circuit structure proposed by the present invention compared to Figure 5.
Figure 7 is a circuit diagram showing the neuron circuit configuration according to an embodiment of the present invention.
FIG. 8 is a basic operation timing diagram of the neuron circuit of FIG. 7.
FIG. 9 shows a graph of voltage changes at the SO node 11 and SOn node 21 according to the input of the synapse array in the neuron circuit with two latches of FIG. 7, and a (EN0, EN1) signal pair and its generation timing diagram. It shows.
FIGS. 10A and 10B are tables showing that when the (EN0, EN1) signal pair of FIG. 9 is applied to the neuron circuit with two latches of FIG. 7, each voltage change graph of the SO node 11 is converted into 2-bit digital data. am.
Figure 11 shows the (EN0, EN1, EN2) signal pair and its generation timing diagram along with a voltage change graph of the SO node and SOn node according to the input of the synapse array in a neuron circuit with three latches in another embodiment of the present invention. It shows.
FIGS. 12A and 12B are tables showing that when the (EN0, EN1, EN2) signal pair of FIG. 11 is applied to a neuron circuit with three latches, each voltage change graph of the SO node is converted into 3-bit digital data.
Figure 13 is a neuromorphic circuit diagram showing the neuron circuit of Figure 7 coupled to a synapse array.
Figure 14 is a conceptual diagram showing that the input bit slicing technique can be applied to the synapse array of Figure 13.
Figure 15 is an example diagram showing the operation of a neuron circuit when applying the input bit slicing technique of Figure 14.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

As illustrated in FIG. 7, the neuron circuit according to an embodiment of the present invention is connected to a first contact point (SO node, 11) where the V _DD supply transistor 12 is connected to the bit line (BL) of the synapse array. inverter (10); A data transfer transistor (20) whose gate is connected to the output terminal (SON node, 21) of the inverter; Two or more n latches (42, 44) connected in parallel to the second contact point (22) to which the drain of the data transfer transistor is connected; and an EN Pulse Train (not shown) that generates n EN signals (EN0, EN1) input to the n latches in at least 2 ⁿ -1 pairs.

The neuron circuit of this embodiment is connected to each bit line (BL) of the synapse array and has a parallel sensing buffer structure that can output digital data without going through the conventional TIA and ADC circuit, as shown in FIG. 6.

Figure 7 shows an example of configuring a neuron circuit with a page buffer including two latches 42 and 44, but a neuron circuit that outputs n-bit digital data can be configured with two or more n latches. That is, n is 2 or a natural number greater than 2.

Referring to FIG. 13, the neuron circuit 100 of this embodiment is connected to each bit line (BL) of the synapse array 200, and is connected to each bit line (e.g., an input pulse of the synapse array 200). The discharge current flowing through BL ₀ is converted into n bits of digital voltage data using n latches (40: 42, 44) and output (VOUT0, VOUT1).

The V _DD supply transistor 12 may be a P-channel MOSFET (PMOS) connected to the V _DD supply terminal and the first contact point 11 as usual to apply a precharge (PCHn) signal to the gate.

At one end of the bit line BL, a voltage sensing switch 14 controlled by a SENS signal is connected to the first contact point 11.

In FIG. 7 , the capacitor C _SO (16) connected between the first contact point 11 and ground may be caused by or include parasitic capacitance of the bit line BL.

The inverter 10 is connected between the first contact 11 and the data transfer transistor 20 to invert the analog discharge voltage of the first contact 11 to obtain a control signal (EN signal, etc.) to be described later. It is provided.

The output terminal (SON node, 21) of the inverter 10 is connected to a data transmission transistor 20 through a gate, so that the voltage of the first contact point 11 is first converted into digital.

The data transfer transistor 20 is preferably an NMOS (N-channel MOSFET) whose source is connected to ground, so that the converted digital voltage data is output to the second point 22 whose drain is connected.

The digital voltage data of the second dot 22 is stored in the n latches 42 and 44, and is used to distinguish the analog current flowing to the bit line BL by the voltage of the first contact 11, that is, The analog current flowing to the bit line (BL) varies depending on the input pulse of the synapse array 200. In order to distinguish this, it is desirable to convert it into n-bit digital voltage data and store it by the EN signal.

Referring to FIG. 9, the EN signal is triggered when the signal at the output terminal (SON node, 21) of the inverter 10 in the EN Pulse Train is 'High' (e.g., t0, t1, t2) to generate n ENs. It may be a pulse signal divided into signals (EN0, EN1) and output as one of 2 ⁿ -1 pairs.

The n latches 42 and 44 each include a latch signal input transistor 32 with one end connected to the second contact point 22, a reset signal input transistor 34 with one end connected to ground, and the latch signal input transistor 32. and two inverters 36 and 38 arranged in opposite directions between each other end of the reset signal input transistor 34 and connected in parallel.

The latch signal input transistor 32 is an NMOS through which a latch signal (eg, LAT0 or LAT1) is input to the gate, and the reset signal input transistor 34 is an NMOS through which a reset signal (eg, RST0 or RST1) is input into the gate. It can be.

The n latches 42 and 44 are provided so that the neuron circuit has n output terminals VOUT0 and VOUT1, with the other terminal of the latch signal input transistor 32 serving as the output terminal 39 of each latch.

The n output terminals (VOUT0, VOUT1) are each connected to the input terminal of the integrated AND gate 52, and the output terminal of the integrated AND gate 52 is connected to each input terminal of the n separate control AND gates 54 and 56. It is connected, and each input terminal of the n separate control AND gates 54 and 56 is provided to be input together with one of the n EN signals (EN0 and EN1).

Each output terminal of the n separate control AND gates 54 and 56 is connected to the gate of one latch signal input transistor 32 among the n latches 42 and 44.

By being configured as above, the digital voltage data of the second dot 22 is stored as n bits in the n latches 42 and 44.

Referring to FIGS. 8 to 10A and 10B together, the operation method of the above-described neuron circuit will be described.

First, as shown in the basic operation timing diagram of FIG. 8, a negative precharge (PCHn) signal is applied to the V _DD supply transistor 12 to turn on the PMOS to turn the first contact 11 to V _DD . Precharge is performed, and at the same time, each reset signal input transistor 34 of the n latches 42 and 44 applies a positive reset signal (RST), so that all n output terminals (VOUT0 and VOUT1) are in the data "1" state. Initialize.

Next, V _DD is applied as a SENS signal to the voltage sensing switch 14 to sense the voltage change at the precharged first contact point (SO node, 11). When the voltage sensing switch 14 is turned on by the SENS signal, the analog current flowing through the bit line BL changes according to the input pulse of the synapse array 200, and the discharge voltage curve of the first contact 11 changes, as shown in FIG. (1, 2, 3) changes and this is sensed.

To sense the voltage change of the first contact point 11, it is preferable to use the signal from the output terminal (SOn node, 21) of the inverter 10, as described above. In this case, as shown in Figure 9, when the signal at the output terminal (21) of the inverter (10) in the EN Pulse Train is 'High' (t0, t1, t2), it is triggered and divided into n EN signals (EN0, EN1) to generate 2 ⁿ -One pulse signal out of a pair can be output (generated).

Here, when the signal at the output terminal 21 of the inverter 10 is 'High', it can be defined as when the NMOS, which is the data transfer transistor 20, is turned on.

In addition, after the n EN signals (EN0, EN1) are applied to the voltage sensing switch 14 as a SENS signal, for example, V _DD , 2 ⁿ -1 pairs are generated in a predetermined order in the EN Pulse Train. It can be controlled to occur.

Thereafter, the n EN signals (EN0, EN1) generated from the EN Pulse Train are applied as latch signals (LAT0, LAT1) to each latch signal input transistor 32 of the n latches 42, 44, Depending on whether the initial data "1" state of the n output terminals (VOUT0, VOUT1) of the latches 42 and 44 changes, the analog current flowing through the first contact 11 to the synapse array 200 is converted into n-bit digital Proceed to the step of converting to voltage data and storing it.

The n EN signals are controlled so that 2 ⁿ -1 pairs occur in a predetermined order in the EN Pulse Train after the SENS signal is applied to the voltage sensing switch.

Referring to FIGS. 7, 9, 10A, and 10B, a specific example will be described.

The first discharge voltage curve (1) of the first contact (11) is inverted by the inverter (10), and then two EN signals (EN0, EN1) are {on(o), off(x) at t0 in the EN Pulse Train. )} to be generated as a pair. The output terminal (VOUT0) of the first latch (L0, 42) is a latch signal (LAT0) to the latch signal input transistor 32, and a pulse signal due to on(o) of EN0 is applied through the AND gate 54 for separation control. As the latch signal input transistor 32 turns on, the initial data “1” changes to “0”. Meanwhile, the output terminal (VOUT1) of the second latch (L1, 44) is turned off (x) of EN1 as a latch signal (LAT1) to the latch signal input transistor 32, that is, the pulse signal is not applied (in the '0' state). input) and output as "0" from the AND gate 56 for separation control, the latch signal input transistor 32 of the second latch 44 continues to be turned off, and the initial data "1" is maintained as is. Therefore, in the first discharge voltage curve (1, Case 1), the data (L1, L0) is converted into 2-bit digital data of '10' and stored by the two latches (42, 44), as shown in FIG. 10A, Afterwards, it continues as shown in Figure 10b.

The second discharge voltage curve (2, Case 2) is inverted by the inverter (10), and then at t1 in the EN Pulse Train, two EN signals (EN0, EN1) become a pair of {off(x), on(o)} to occur. The output terminal (VOUT0) of the first latch (L0, 42) outputs “0” to the AND gate (54) for isolation control due to the latch signal input transistor (32) turning off (x) EN0. The latch signal input transistor 32 remains turned off and the initial data “1” is maintained. Meanwhile, at the output terminal (VOUT1) of the second latch (L1, 44), a pulse signal due to on(o) of EN1 is applied to the latch signal input transistor 32 through the AND gate 56 for separation control, As (32) turns on, the initial data "1" changes to "0". Accordingly, in the second discharge voltage curve 2, data (L1, L0) is converted into 2-bit digital data of '01' and stored by the two latches 42 and 44, as shown in Figure 10a. It continues as in 10b.

The third discharge voltage curve (3, Case 3) is inverted by the inverter (10), and then at t3 in the EN Pulse Train, two EN signals (EN0, EN1) become a pair of {on(o), on(o)} to occur. In this case, the initial data "1" at the output terminal (VOUT0) of the first latch (L0, 42) and the output terminal (VOUT1) of the second latch (L1, 44) are all changed to "0". Accordingly, in the third discharge voltage curve 3, data (L1, L0) is converted into 2-bit digital data of '00' and stored by the two latches 42 and 44, as shown in FIG. 10A, and thereafter, as shown in FIG. It continues as in 10b.

After each discharge voltage curve of the first contact 11 is converted into 2-bit digital data and stored in the two latches 42 and 44, the data is maintained. As described above, the output terminal (VOUT0) of the first latch (L0, 42) and the output terminal (VOUT1) of the second latch (L1, 44) are respectively connected to the input terminal of the AND gate 52 for integration, and the integrated The output terminal of the AND gate 52 is connected to each input terminal of the two separate control AND gates 54, 56, and each input terminal of the two separate control AND gates 54, 56 is connected to two EN signals (EN0, EN1). ) This is because it is provided to be input together with one of the following. That is, when the output terminals (VOUT0, VOUT1) of the two latches (42, 44) are all initialized to data "1", the output data of the integration AND gate 52 becomes "1", and the two latch signals ( LAT0 and LAT1) are determined by the EN signal (EN0 or EN1) input by the AND gates 54 and 56 for separate control, respectively, but one of the output terminals (VOUT0 and VOUT1) of the two latches 42 and 44 After the data changes from "1" to "0", no matter which pair of EN0 and EN1 the EN signal is applied to, the latch signals (LAT0, LAT1) output from the output terminals of the AND gates (54, 56) for separation control remain at "0". This is because the latch signal input transistor 32 of each latch cannot be turned on.

Figures 11, 12a, and 12b show a case with three latches as another example. That is, Figure 11 shows the (EN0, EN1, EN2) signal pair and its generation timing diagram along with a graph of the voltage change of the SO node and SOn node according to the input of the synapse array in a neuron circuit with three latches, and Figure 12 is a table showing that when the (EN0, EN1, EN2) signal pair of FIG. 11 is applied to a neuron circuit with three latches, each voltage change graph of the SO node is converted into 3-bit digital data.

Here, too, using the above-described method, each discharge voltage curve (voltage change graph) at the SO node, which is the first contact point 11, can be converted into 3-bit digital data of data (L2, L1, L0) and stored in three latches. . That is, the first discharge voltage curve (1) is '110', the second discharge voltage curve (2) is '101', the third discharge voltage curve (3) is '100', and the fourth discharge voltage curve (4) is '100'. '011', the fifth discharge voltage curve (5) is converted to '010', the sixth discharge voltage curve (6) is converted to '001', and the seventh discharge voltage curve (7) is converted to '000' and stored in three latches. It can be saved.

In the above-described manner, when more than 3 n latches are connected in parallel to the second contact point 22 in FIG. 7, 2 ⁿ -1 SO node discharge voltage curves (voltage change graph) are digitally converted to n bits. By being able to convert, it becomes possible to implement a neuron circuit according to the input pulse of the synapse array 200 with more precision.

FIG. 13 is a neuromorphic circuit diagram showing the neuron circuit 100 of FIG. 7 coupled to the synapse array 200. A neuromorphic circuit can be formed by attaching the neuromorphic circuit 100 described above to each bit line of the BL of each array, that is, the synapse array 200. The intensity of the current flowing in the bit line (e.g., BL ₀ ) varies depending on the input pulse applied to the word lines (WL ₀ , WL ₁ , ..., WL _n-1 ) of the synapse array 200. . Accordingly, the discharge speed of C _SO (16) in the neuron circuit changes. Using this principle, the analog current flowing in the bit line of the synapse array is converted into digital data through the above-described method, and the effect of the input pulse on the synapse elements 201, 202, and 203 of the synapse array 200 is the neuron circuit. It can be stored in n latches (40: 42, 44) of (100).

FIG. 14 is a conceptual diagram showing that the input bit slicing technique can be applied to the synapse array of FIG. 13 in addition to the normal vector-matrix multiplication operation. The input bit slicing technique is a method of performing vector-matrix multiplication by assigning digits to the input pulse applied to the synapse array 200 according to the input time, as shown in FIG. 14. For other Input bit slicing techniques, please refer to the related paper ("Analog architectures for neural network acceleration based on non-volatile memory", T. Patrick Xiao, Applied Physics, 09 July 2020).

The stimulus applied as an input to the synapse array 200 causes current to flow through each bit line of the array by pulses according to time, and the current flows in a time period corresponding to each digit. At this time, the current flowing through the bit line is digitally converted into n bits and stored in n latches in the manner described above, and the sum of the converted data for each time period is used as a weight for the result of each time period, with the number of digits on the left equal to the corresponding input time of the time zone. Vector-matrix multiplication can be performed by shifting left to and finally summing.

Figure 15 is an example diagram showing the operation of a neuron circuit when applying the input bit slicing technique of Figure 14.

Referring to FIG. 15, the voltage change of the SO node due to the input of the synapse array 200 at the 2 ⁰ time zone, 2 ¹ time zone, 2 ² time zone, and 2 ³ time zone is the first discharge voltage curve (1, Case 1), respectively. With the second discharge voltage curve (2, Case 2) and the third discharge voltage curve (3, Case 3), each discharge voltage curve is digitally converted into 2 bits and stored in two latches in the above-described manner. Here, after converting to 2-bit digital data in each time zone, the SO node must be precharged again each time. At this time, the 2-bit digital data stored in the two latches of the neuron circuit are stored in the buffer, then the results from the next time period are shifted left to the appropriate number of digits, the weights are calculated and added repeatedly, the neuron operation is performed, and the final result is It will be printed.

10: inverter
20: Transistor for data transmission
32: Latch signal input transistor
34: Reset signal input transistor
40, 42, 44: Latch
52: AND gate for integration
54, 56: AND gate for separate control

Claims (10)

an inverter connected to a first contact point where a transistor for supplying V _DD is connected to the bit line of the synapse array;
A data transfer transistor whose gate is connected to the output terminal of the inverter;
two or more n latches connected in parallel to a second contact point to which the drain of the data transfer transistor is connected; and
A neuron circuit comprising an EN Pulse Train that generates n EN signals input to the n latches in at least 2 ⁿ -1 pairs.
According to claim 1,
A neuron circuit, wherein the data transfer transistor is an NMOS whose source is connected to ground.
According to claim 1,
A neuron circuit, wherein the n latches convert the analog current flowing through the bit line into n-bit digital voltage data by the EN signal and store it.
The method according to any one of claims 1 to 3,
The n latches are each a latch signal input transistor with one end connected to the second contact point, a reset signal input transistor with one end connected to ground, and disposed in opposite directions between the latch signal input transistor and the other end of the reset signal input transistor. It consists of two inverters connected in parallel,
The n latches have n output terminals with the other terminal of the latch signal input transistor as the output terminal of each latch,
The n output terminals are each connected to the input terminal of the integrated AND gate,
The output terminal of the integrated AND gate is connected to each input terminal of the n separate control AND gates,
Each input terminal of the n separate control AND gates is provided to be input together with one of the n EN signals,
A neuron circuit, wherein each output terminal of the n separate control AND gates is connected to the gate of a latch signal input transistor of one of the n latches.
According to claim 4,
The V _DD supply transistor is a PMOS connected to the V _DD supply terminal and the first contact point to apply a precharge (PCHn) signal to the gate,
At one end of the bit line, a voltage sensing switch controlled by a SENS signal is connected to the first contact point,
C _SO due to the parasitic capacitance of the bit line is between the first contact and ground. connected,
The latch signal input transistor is an NMOS through which a latch signal (LAT) is input to the gate,
A neuron circuit, characterized in that the reset signal input transistor is an NMOS through which a reset signal (RST) is input to the gate.
In the method of operating the neuron circuit of claim 5,
A negative precharge (PCHn) signal is applied to the V _DD supply transistor to turn on the PMOS, thereby turning the first contact point to V _DD. Precharging and simultaneously applying a positive reset signal (RST) to each reset signal input transistor of the n latches to initialize all of the n output terminals to a data "1"state;
applying V _DD as a SENS signal to the voltage sensing switch to sense a change in voltage of the precharged first contact; and
In the EN Pulse Train, n EN signals are generated in 2 ⁿ -1 pairs and applied as a latch signal to each latch signal input transistor of the n latches, so that the initial data of the n output terminals of the n latches is in the "1" state. A method of operating a neuron circuit, comprising converting the analog current flowing through the synapse array through the first contact into n-bit digital voltage data and storing it, depending on whether there is a change in .
According to claim 6,
A method of operating a neuron circuit, wherein the n EN signals are controlled to be generated when the data transfer transistor is turned on.
According to claim 6,
The n EN signals are controlled so that 2 ⁿ -1 pairs are generated in a predetermined order in the EN Pulse Train after the SENS signal is applied to the voltage sensing switch.
A neuromorphic circuit, characterized in that the neuron circuit of claim 4 is connected to each bit line of the synapse array.
In the method of operating the neuron circuit in the neuromorphic circuit of claim 9,
The summation of a plurality of pulses according to the time applied as input to the synapse array is a normal vector-matrix multiplication operation or a weighting of n-bit digital voltage data of the pulse according to the input time of the synapse array with the number of digits on the left equal to the input time. A method of operating a neuron circuit, characterized by moving to and summing.