KR20230078455A - Dc-dc converter and power device including the same - Google Patents

Abstract

A DC-DC converter according to an embodiment of the present invention includes a first transistor connected between a first capacitor and an input node, a second transistor connected between the first capacitor and a second capacitor, the second capacitor and the A first switching circuit including a third transistor connected between a first node between second transistors and a third capacitor, and a fourth transistor connected between the third capacitor and a ground node, the second capacitor and the first switching circuit. A fifth transistor connected between three capacitors, a sixth transistor and a seventh transistor connected between the first capacitor and the third capacitor, and an eighth transistor connected between the first capacitor and the ground node. A second switching circuit, a fourth capacitor connected to a node between the sixth transistor and the seventh transistor, and an LC connected to a third node where the first capacitor, the second transistor, and the eighth transistor are connected to each other. Include filters.

Description

DC-DC converter and power supply device including the same {DC-DC CONVERTER AND POWER DEVICE INCLUDING THE SAME}

The present invention relates to a DC-DC converter and a power supply device including the same.

Electronic devices are operated by a power voltage supplied from a battery or an external power source. In general, a DC voltage output from a battery or the like may be converted into a DC voltage suitable for operation of other devices inside an electronic device by a DC-DC converter. The DC-DC converter can be implemented with various circuits, has high power conversion efficiency regardless of the ratio of input voltage to output voltage, reduces the ripple component of the output voltage, and has a simple structure. Research is actively progressing.

One of the problems to be achieved by the technical idea of the present invention is to reduce the ripple of the output voltage, reduce the conduction loss of transistors provided as a switch element, improve power conversion efficiency, and implement a simple structure without an additional feedback circuit. It is to provide a DC-DC converter and a power supply device including the same.

A DC-DC converter according to an embodiment of the present invention includes a first transistor connected between a first capacitor and an input node, a second transistor connected between the first capacitor and a second capacitor, the second capacitor and the A first switching circuit including a third transistor connected between a first node between second transistors and a third capacitor, and a fourth transistor connected between the third capacitor and a ground node, the second capacitor and the first switching circuit. A fifth transistor connected between three capacitors, a sixth transistor and a seventh transistor connected between the first capacitor and the third capacitor, and an eighth transistor connected between the first capacitor and the ground node. A second switching circuit, a fourth capacitor connected to a node between the sixth transistor and the seventh transistor, and an LC connected to a third node where the first capacitor, the second transistor, and the eighth transistor are connected to each other. Include filters.

In the DC-DC converter according to an embodiment of the present invention, a first transistor providing a first current path for charging a first capacitor between an input node and an output node for a first time, a ground during the first time a second transistor providing a second current path discharging a second capacitor between a node and the output node, and a third current path discharging a third capacitor between the ground node and the output node during the first time period. a third transistor and a fourth transistor, fifth to eighth transistors connecting the first to third capacitors to each other during a second time different from the first time, and an inductor connected to the output node, and and an LC filter having an output capacitor connected to the inductor, wherein the second transistor provides the second current path and the third current path.

A power supply device according to an embodiment of the present invention includes a switched capacitor circuit having a plurality of transistors and a plurality of capacitors, and an LC filter having an inductor and an output capacitor, and generates an output voltage by stepping down the level of an input voltage. a DC-DC converter, a control logic for outputting a PWM (Pulse Width Modulation) signal by comparing the output voltage with a predetermined reference voltage, and a driver for outputting control signals for controlling the plurality of transistors based on the PWM signal. The control logic and the driver operate by receiving a power supply voltage that is less than the input voltage and greater than the output voltage from the DC-DC converter.

According to one embodiment of the present invention, a DC-DC converter may include a plurality of transistors, a plurality of capacitors, and an LC filter that operate as switches. The DC-DC converter can distribute current to the inductor included in the LC filter through a plurality of current paths to supply current, and thus, a change in operating efficiency of the DC-DC converter according to a ratio between an input voltage and an output voltage can be reduced. In addition, the DC-DC converter can be implemented with low-voltage transistors by reducing the number of transistors included in each of the plurality of current paths to reduce conduction loss and reducing the voltage applied to each of the transistors. In addition, it is possible to minimize voltage changes of capacitors without a separate feedback circuit.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a block diagram simply illustrating a DC-DC converter according to an embodiment of the present invention.
2 is a schematic circuit diagram of a DC-DC converter according to an embodiment of the present invention.
3 to 6 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.
7A to 7C are graphs for explaining the operation of a DC-DC converter according to an embodiment of the present invention.
8 and 9 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.
10 to 16 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.
17 is a simplified block diagram of a power supply device according to an embodiment of the present invention.
18 is a schematic diagram illustrating a power supply device according to an embodiment of the present invention.
19A to 19C are graphs for explaining the operation of a power supply device according to an embodiment of the present invention.
20 to 22 are graphs for explaining the operation of a power supply device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram simply illustrating a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 1, a DC-DC converter 10 according to an embodiment of the present invention includes a first switching circuit 11, a second switching circuit 12, a capacitor circuit 13 and an LC filter 14 etc. may be included. The DC-DC converter 10 may output an output voltage VOUT by stepping down the input voltage VIN, and the output voltage VOUT by the voltage conversion ratio of the input voltage VIN and the DC-DC converter 10. ) can be determined.

Each of the first switching circuit 11 and the second switching circuit 12 includes a plurality of switches, and each of the plurality of switches may be implemented as a transistor. For example, some of the plurality of transistors included in the first switching circuit 11 and the second switching circuit 12 may be NMOS transistors, and some may be PMOS transistors.

The capacitor circuit 13 may include a plurality of capacitors. For example, a plurality of capacitors may be connected to a plurality of transistors included in the first switching circuit 11 and the second switching circuit 12 to provide a switched capacitor circuit. At least one of the plurality of capacitors may be included in one integrated circuit chip together with the first switching circuit 11 and the second switching circuit 12, and some of the plurality of capacitors are disposed outside the integrated circuit chip It can be connected to an integrated circuit chip.

The LC filter 14 includes an inductor and an output capacitor, and may be connected to an output terminal of a switched capacitor circuit provided by the first switching circuit 11, the second switching circuit 12, and the capacitor circuit 13. One end of the inductor may be directly connected to the output terminal of the switched capacitor circuit, and the other end of the inductor may be connected to the ground node through the output capacitor. Therefore, it is possible to connect the LC filter 14 to the switched capacitor circuit while minimizing the number of additional pins of the integrated circuit chip.

In one embodiment of the present invention, the switched capacitor circuit provided by the first switching circuit 11, the second switching circuit 12 and the capacitor circuit 13 is connected to the inductor of the LC filter 14 through a plurality of current paths. current can be supplied. For example, the DC-DC converter 10 may operate according to a predetermined cycle, and one cycle of the DC-DC converter 10 may include a first time and a second time.

During the first time, the switched capacitor circuit may supply current to the inductor to store energy in the inductor. On the other hand, energy stored in the inductor may be discharged during the second time period. By supplying current to the inductor through the plurality of current paths for the first time, conduction loss may be reduced by minimizing the number of transistors included in each of the current paths. In addition, since the level of current that one transistor must handle can be reduced, the DC-DC converter 10 can be implemented with small-sized transistors.

2 is a schematic circuit diagram of a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 2 , a DC-DC converter 100 according to an embodiment of the present invention includes a switched capacitor circuit provided by a plurality of transistors TR1 to TR8 and a plurality of capacitors C1 to C4 and an LC filter etc. may be included. The LC filter may include an inductor (L) and an output capacitor (COUT). Some of the plurality of transistors TR1 to TR8 may be NMOS transistors, and some may be PMOS transistors.

Among the plurality of transistors TR1 to TR8, the first to fourth transistors TR1 to TR4 provide a first switching circuit, and the fifth to eighth transistors TR5 to TR8 provide a second switching circuit. can provide The DC-DC converter 100 may operate according to a predetermined cycle, and one cycle of the DC-DC converter 100 may include a first time and a second time. For example, during the first time period, the first to fourth transistors TR1 to TR4 may be turned on and the fifth to eighth transistors TR5 to TR8 may be turned off. On the other hand, during the second time period, the first to fourth transistors TR1 to TR4 may be turned off and the fifth to eighth transistors TR5 to TR8 may be turned on. Turning on/off of the plurality of transistors TR1 to TR8 may be determined by control signals CTR1 to CTR8.

The plurality of transistors TR1 to TR8 may be connected to the plurality of capacitors C1 to C4. For example, the first transistor TR1 may be connected between an input node to which the input voltage VIN is input and the first capacitor C1, and the second transistor TR2 may be connected between the first capacitor C1 and the second capacitor C1. (C2) can be connected between. Meanwhile, the third transistor TR3 may be connected between the first node N1 to which the second capacitor C2 and the second transistor TR2 are connected to each other and the third capacitor C3. Referring to FIG. 2 , the third transistor TR3 may be connected between the first node N1 and the second node N2 to which the third capacitor C3 is connected. The fourth transistor TR4 may be connected between the third capacitor C3 and the ground node.

The fifth transistor TR5 may be connected between the second capacitor C2 and the third capacitor C3. The sixth transistor TR6 and the seventh transistor TR7 are connected between the first capacitor C1 and the third capacitor C3, for example, a node between the sixth transistor TR6 and the seventh transistor TR7. A fourth capacitor C4 may be connected to. The eighth transistor TR8 may be connected between the first capacitor C1 and the ground node. Referring to FIG. 2 , the eighth transistor TR8 may be connected between the ground node and the third node N3 where the first capacitor C1, the second transistor TR2 and the inductor L are connected to each other.

The first to third capacitors C1 to C3 may be external capacitors disposed outside the integrated circuit chip including the plurality of transistors TR1 to TR8. On the other hand, the fourth capacitor C4 may be implemented inside the integrated circuit together with the plurality of transistors TR1 to TR8. The capacitance of each of the first to third capacitors C1 to C3 may be greater than that of the fourth capacitor C4. For example, the capacitance of the fourth capacitor C4 may be tens to hundreds of pF. Meanwhile, the capacity of the output capacitor COUT may also be greater than that of the fourth capacitor C4.

While the DC-DC converter 100 is operating, the voltage of the first node N1 may be 1/3 of the input voltage, and the voltage of the second node N2 may be 2/3 of the input voltage. Therefore, the voltage of the second capacitor C2 and the voltage of the third capacitor C3 can be maintained at 1/3 of the input voltage, and the voltage of the first capacitor C1 is 2/3 of the input voltage. level can be maintained.

As described above, one cycle of the DC-DC converter 100 can be divided into a first time and a second time, and during the first time, the first to fourth transistors TR1 to TR4 are turned on, and During the 2 hours, the fifth to eighth transistors TR5 to TR8 may be turned on. During the first time period, current is supplied to the inductor L through a plurality of current paths to charge the inductor L with energy, and during the second time period, the energy of the inductor L may be discharged. Also, in the DC-DC converter 100 according to the embodiment shown in FIG. 2 , voltages of the first to third capacitors C1 to C3 may be maintained constant without a separate feedback circuit. Hereinafter, it will be described in more detail with reference to FIGS. 3 to 6 .

3 to 6 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.

3 is a diagram for explaining the operation of the DC-DC converter 100 during the first time of one cycle, and FIG. 4 may be a diagram showing an equivalent circuit of the DC-DC converter 100 during the first time. . 5 is a diagram for explaining the operation of the DC-DC converter 100 during the second time period of one cycle, and FIG. 6 may be a diagram showing an equivalent circuit of the DC-DC converter 100 during the second time period. .

First, referring to FIG. 3 , as described above, in the DC-DC converter 100 for a first time, the first to fourth transistors TR1 to TR4 are turned on, and the fifth to eighth transistors TR5- are turned on. TR8) can be turned off. Therefore, as shown in FIG. 3 , the first to third currents I1 to I3 may be supplied to the inductor L through the plurality of current paths.

For example, the first current I1 may be supplied to the inductor L through a first current path including the first transistor TR1 and the first capacitor C1. The second current I2 may flow through a second current path including the second capacitor C2 and the second transistor TR2, and the third current I3 may flow through the third capacitor C3 and the second to second transistors TR2. It may flow through a third current path including the fourth transistors TR2 to TR4. During the first time, the first capacitor C1 may be charged, and the second capacitor C2 and the third capacitor C3 may be discharged.

As described with reference to FIG. 3 , each of the first current path and the second current path may include one transistor, and the third current path may include three transistors. In the DC-DC converter 100 according to an embodiment of the present invention, the number of transistors included in each current path can be optimized, and thus conduction loss proportional to the square of the current flowing through the transistor can be reduced. Conduction loss of the DC-DC converter 100 can be minimized by distributing current through the plurality of current paths to reduce the current flowing through each current path and simultaneously optimizing the number of transistors included in each current path. For example, as shown in FIG. 3 , currents I1- through a current path bypassing at least some of the plurality of transistors TR1-TR8 using the first to third capacitors C1-C3 I3) can be supplied to the inductor L, and thus the number of transistors included in each current path can be reduced.

In addition, since the currents I1-I3 required to charge energy in the inductor L are distributed through three current paths and supplied to the inductor L, the burden on transistors included in each current path can be reduced. , the DC-DC converter 100 can be implemented with small-sized transistors.

Referring to FIG. 4 showing an equivalent circuit of the DC-DC converter 100 during the first time, the second capacitor C2 and the third capacitor C3 are connected in parallel to each other, and the first capacitor C1 It may be connected in series with the second capacitor C2 and the third capacitor C3. Meanwhile, the LC filter may be connected to a node between the first capacitor C1 and the third capacitor C3. Accordingly, the voltage of each of the first to third capacitors C1 to C3 during the first time period may be expressed as Equation 1 below.

[Equation 1]

VIN = VC1 + VC2 = VC1 + VC3

Next, referring to FIG. 5 , as described above, during the second time, the first to fourth transistors TR1 to TR4 are turned off in the DC-DC converter 100 and the fifth to eighth transistors TR5 are turned off. -TR8) can be turned on. Therefore, at the second time, the first to third capacitors C1 to C3 are connected to each other, and the first capacitor C1 is discharged while the second and third capacitors C2 and C3 are charged. .

Referring to FIG. 6 showing an equivalent circuit of the DC-DC converter 100 during the second time, the first to third capacitors C1 to C3 are connected in series with each other, and the inductor L is connected to the ground node. can Therefore, the voltage of each of the first to third capacitors C1 to C3 during the second time period may be expressed as Equation 2 below.

[Equation 2]

VC1 = VC2 + VC3

Referring to Equations 1 and 2 together, the voltages of the second capacitor C2 and the third capacitor C3 may have a level corresponding to 1/3 of the input voltage, and the first capacitor C1 The voltage of may have a level corresponding to 2/3 of the input voltage. Accordingly, the output voltage VOUT output through the LC filter may be determined between 1/3 of the input voltage and the ground voltage. For example, the level of the output voltage VOUT may vary according to lengths of the first time period and the second time period within one period of the DC-DC converter 100 .

In an embodiment, as the first time period becomes longer and the second time period becomes shorter, the output voltage VOUT may have a level close to 1/3 of the input voltage. On the other hand, as the first time period becomes shorter and the second time period becomes longer, the output voltage VOUT may have a level close to the ground voltage.

Unlike the first time, since the first capacitor C1 is discharged and the second and third capacitors C2 and C3 are charged at the second time, the voltage of each of the first to third capacitors C1 to C3 is It can be kept constant without a separate feedback circuit. Hereinafter, a description will be made with reference to FIGS. 7A to 7C .

7A to 7C are graphs for explaining the operation of a DC-DC converter according to an embodiment of the present invention.

7A may be a graph showing one of the control signals CTR1 to CTR8 input to the DC-DC converter 100 . FIG. 7B may be a graph roughly showing the voltage of the third node N3, and FIG. 7C may be a graph roughly showing the voltages of each of the first to third capacitors C1 to C3.

Turning on/off of the plurality of transistors TR1 to TR8 included in the DC-DC converter 100 may be determined by the control signals CTR1 to CTR8 output from the control circuit. For example, the control circuit may match the first to eighth control signals CTR1 to CTR8 to the plurality of transistors TR1 to TR8 and output them. 7A may be a graph simply illustrating the third control signal CTR3 supplied to the third transistor TR3 among the plurality of transistors TR1 to TR8. For example, the first control signal CTR1 supplied to the first transistor TR1 may be the same as the third control signal CTR3.

Referring to FIGS. 7A to 7C , the DC-DC converter 100 may operate according to a predetermined cycle (TD). One period (TD) includes a first time (T1) and a second time (T2), the first time (T1) is the time to charge the energy in the inductor (L), the second time (T2) It may be the time during which the energy charged in the inductor (L) is discharged.

7B is a graph showing the voltage of the third node N3, and the third node N3 includes the first capacitor C1, the inductor L, and the second transistor (as described with reference to FIGS. 3 to 6). TR2) and the eighth transistor TR8 may be nodes connected to each other. During the first time T1, the second transistor TR2 is turned on, and the voltage of the third node N3 may be equal to the voltage of the second capacitor C2.

Therefore, as described above with reference to Equation 1, the voltage of the third node N3 during the first time period T1 may be determined to be a level corresponding to 1/3 of the input voltage VIN. On the other hand, during the second time period T2, the second transistor TR2 may be turned off and the eighth transistor TR8 may be turned on. Therefore, during the second time period T2, the third node N3 is connected to the ground node, and the voltage of the third node N3 may be determined as the ground voltage.

7C may be a graph showing voltages of each of the first to third capacitors C1 to C3. As described above with reference to Equations 1 and 2, the voltage VC1 of the first capacitor C1 may have a level corresponding to 2/3 of the input voltage VIN. On the other hand, each of the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3 may have a level corresponding to 1/3 of the input voltage VIN.

Meanwhile, during the first time T1, the first capacitor C1 may be charged, and the second capacitor C2 and the third capacitor C3 may be discharged. Therefore, as shown in FIG. 7C, the voltage VC1 of the first capacitor C1 increases minutely during the first time period T1, and the voltage VC2 of the second capacitor C2 and the voltage VC2 of the third capacitor C3 ) of the voltage VC3 may decrease minutely.

During the second time period T2 , as described above with reference to FIG. 6 , the first to third capacitors C1 to C3 may be connected in series with each other. During the second time period T2, the first capacitor C1 is discharged and the second capacitor C2 and the third capacitor C3 are charged, and thus, as shown in FIG. 7C, the voltage of the first capacitor C1 ( VC1) is slightly decreased, and the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3 may be slightly increased.

As described with reference to FIG. 7C , in an embodiment of the present invention, the voltage of each of the first to third capacitors C1 to C3 may be maintained constant without a separate feedback circuit. Therefore, the structure of the DC-DC converter 100 can be simplified and the number of elements required to implement the DC-DC converter 100 can be reduced.

Meanwhile, each of the control signals CTR1 to CTR8 input to the plurality of transistors TR1 to TR8 may be a square wave signal. However, the actual control signals CTR1 to CTR8 inevitably have a predetermined slew rate, and as a result, at least some of the control signals CTR1 to CTR8 may not have a perfect square wave. Therefore, before at least one of the first to fourth transistors TR1 to TR4 is completely turned off between the first time T1 and the second time T2 within one period, the fifth to eighth transistors are turned off. At least one of (TR5-TR8) may be turned on. Alternatively, at least one of the fifth to eighth transistors TR5 to TR8 is completely turned on between the second time T2 of the first period and the first time T1 of the second period immediately after the first period. Before being turned off, at least one of the first to fourth transistors TR1 to TR4 may be turned on.

Between the first time T1 and the second time T2, at least one of the first to fourth transistors TR1 to TR4 and at least one of the fifth to eighth transistors TR5 to TR8 are simultaneously turned- When it has an on state, a current path directly connecting the input node and the ground node may be created. Alternatively, as nodes that should not be directly connected to each other are connected to each other while the DC-DC converter 100 is operating, unintended charge loss may occur in at least one of the first to third capacitors C1 to C3.

8 and 9 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.

First, FIG. 8 may be a graph simply showing some of control signals input to a DC-DC converter according to an embodiment of the present invention. Meanwhile, FIG. 9 may be a circuit diagram simply illustrating the DC-DC converter 200 according to an embodiment of the present invention. The DC-DC converter 200 shown in FIG. 9 may have a structure similar to that previously described with reference to FIG. 2 , and therefore, a detailed description of the structure of the DC-DC converter 200 will be omitted.

Referring to FIG. 8 , each of the control signals CTR1 to CTR8 input to the plurality of transistors TR1 to TR8 of the DC-DC converter 200 may be a square wave signal having a predetermined slew rate. For example, the third control signal CTR3 may be a square wave signal having a duty ratio of 50% or more, and the eighth control signal CTR8 may be a square wave signal having a duty ratio of 50% or less. Both the third transistor TR3 to which the third control signal CTR3 is input and the eighth transistor TR8 to which the eighth control signal CTR8 is input may be NMOS transistors.

Ideally, the eighth transistor TR8 may be turned off during the first time T1 when the third transistor TR3 is turned on, and the second time (T1) when the eighth transistor TR8 is turned on. During T2), the third transistor TR3 may be turned off. However, as shown in FIG. 8, since both the third control signal CTR3 and the eighth control signal CTR8 have a predetermined slew rate, the slew rate is increased between the first time T1 and the second time T2. The third transistor TR3 and the eighth transistor TR8 may be turned on at the same time. For example, the third transistor TR3 and the eighth transistor TR8 may be simultaneously turned on at the first intermediate point TI1 and/or the second intermediate point TI2 . A similar phenomenon may occur in other transistors as well.

In the DC-DC converter 200, the first to fourth transistors TR1 to TR4 are turned on for a first time period T1, and the fifth to eighth transistors TR5 to TR8 are turned on for a second time period. may be turned on during (T2). However, before the first to fourth transistors TR1 to TR4 are all turned off during the transition from the first time T1 to the second time T2, the fifth to eighth transistors TR5 to TR8 At least one of them may be turned on. Alternatively, during the transition from the second time T2 to the first time T1 , the first to fourth transistors TR1 to TR4 are all turned off before the fifth to eighth transistors TR5 to TR8 are all turned off. ) may be turned on.

In this case, a current path in which the input node and the ground node are directly connected may be created. For example, when the first to third transistors TR1 to TR3 and the sixth to eighth transistors TR6 to TR8 are simultaneously turned on between the first time T1 and the second time T2 , a current path in which the input node and the ground node are directly connected may be created, as shown in FIG. 9 .

In the present invention, the on/off timing of each of the plurality of transistors TR1 to TR8 may be adjusted so that the above problem does not occur. Hereinafter, an on/off control operation of the plurality of transistors TR1 to TR8 will be described with reference to FIGS. 10 to 16 .

10 to 16 are diagrams provided to explain the operation of a DC-DC converter according to an embodiment of the present invention.

In the embodiment described with reference to FIGS. 10 to 16 , the DC-DC converter 300 operates according to a predetermined cycle, and one cycle may include a first time and a second time. The first time may be a time when energy is charged in the inductor (L), and the second time may be a time when the energy charged in the inductor (L) is discharged.

10 may be a diagram showing on/off states of the plurality of transistors TR1 to TR8 included in the DC-DC converter 300 during the first time period. Referring to FIG. 10 , the first to fourth transistors TR1 to TR4 may be turned on for a first time, and the fifth to eighth transistors TR5 to TR8 may be turned off. During the first time, the first capacitor C1 is charged, the second capacitor C2 and the third capacitor C3 are discharged, and the currents I1-I3 flowing through the three current paths are applied to the inductor L. Energy can be charged.

In the embodiments shown in FIGS. 10 to 16 , elapsed times may be defined between the first time and the second time in order to accurately control the on/off timings of the plurality of transistors TR1 to TR8 . For example, a first elapsed time and a second elapsed time may be defined in a section where the first time ends and the second time starts within one period. Each of the first elapsed time and the second elapsed time may overlap with at least one of the first time and the second time. Similarly, assuming that the first period and the second period are adjacent to each other, the third elapsed time and the fourth elapsed time are defined in the section where the second time of the first period ends and the first period of the second period begins. It can be. The third elapsed time may overlap the second time of the first period, and the fourth elapsed time may overlap the first time of the second period.

As an example, FIG. 11 is a diagram for explaining the operation of the DC-DC converter 300 for a first elapsed time, and FIG. 12 is a diagram for explaining the operation of the DC-DC converter 300 for a second elapsed time. can Meanwhile, FIG. 14 is a diagram for explaining the operation of the DC-DC converter 300 during the third elapsed time, and FIG. 15 may be a diagram for explaining the operation of the DC-DC converter 300 during the fourth elapsed time. there is.

First, referring to FIG. 11 , the first transistor TR1 , the second transistor TR2 , and the third transistor TR3 may enter a turn-off state during a first elapsed time. During the first elapsed time, the fourth transistor TR4 may still maintain a turn-on state. As the first to third transistors TR1 to TR3 are turned off, all current paths supplying current to the inductor L may be blocked. Next, referring to FIG. 12 , the fourth transistor TR4 may be turned off during the second elapsed time.

FIG. 13 may be a diagram showing on/off states of the plurality of transistors TR1 to TR8 included in the DC-DC converter 300 for a second time period after both the first elapsed time and the second elapsed time have elapsed. there is. Referring to FIG. 13 , the first to fourth transistors TR1 to TR4 may be turned off for a second time period, and the fifth to eighth transistors TR5 to TR8 may be turned on. During the second time period, the first to third capacitors C1 - C3 are connected in series, and the energy charged in the inductor L during the first time period may be discharged during the second time period.

As described above with reference to FIGS. 5 and 6 , the voltage of each of the second capacitor C2 and the third capacitor C3 may be maintained at a level corresponding to 1/3 of the input voltage for the second time period. Meanwhile, the voltage of the first capacitor C1 may be maintained at a level corresponding to 2/3 of the input voltage. Accordingly, the voltage of the first node N1 may be VIN/3, and the voltage of the second node N2 may be 2*VIN/3. A voltage of a node where the sixth transistor TR6 , the seventh transistor TR7 , and the fourth capacitor C4 are connected to each other may be the same as the voltage of the second node N2 .

If the second time passes within one cycle, the first time may start again in the next cycle. As described above, in the first and second consecutive periods, the third elapsed time and the fourth elapsed time are defined in the section where the second time of the first cycle ends and the first time of the second cycle begins. It can be. The third elapsed time may be a time included in the first period, and the fourth elapsed time may be a time included in the second period.

Referring to FIG. 14 , the fifth to seventh transistors TR5 to TR7 may first be turned off during the third elapsed time. Therefore, the third capacitor C3 and the second capacitor C2 are separated from each other, and the voltage of the first node N1 can be maintained at VIN/3. Voltages of a node where the sixth transistor TR6 and the seventh transistor TR7 and the fourth capacitor C4 are connected to each other and the second node N2 may be maintained at 2*VIN/3.

Next, referring to FIG. 15 , the eighth transistor TR8 may be turned off during the fourth elapsed time, and the fourth transistor TR4 may be turned on. Immediately after the fourth elapsed time, the first to third transistors TR1 to TR3 are turned on, and as shown in FIG. 16 , three current paths are created so that energy can be charged in the inductor L. For example, the operation of the DC-DC converter 300 during the third elapsed time may be the same as the operation of the DC-DC converter 300 during the second elapsed time, and the operation of the DC-DC converter 300 during the fourth elapsed time The operation may be the same as that of the DC-DC converter 300 during the first elapsed time.

As described with reference to FIGS. 10 to 16 , predetermined elapsed times are provided in each of the section from the first time to the second time and the section from the second time to the first time to form transistors TR1 to TR8 By adjusting the on/off timing of , it is possible to prevent the input node from being directly connected to the ground node. In addition, by minimizing loss due to charge sharing between the second capacitor C2 and the third capacitor C3, the voltage of the second capacitor C2 and the third capacitor C3 is set to a desired level, for example, VIN. /3, and the voltage of the fourth capacitor C4 can be maintained at 2*VIN/3.

In one embodiment, assuming that one cycle of the DC-DC converter 300 is 1us, each of the first time and the second time may vary according to the level of the output voltage VOUT. Meanwhile, the first to fourth elapsed times for preventing direct connection between the input node and the output node and reducing charge sharing loss due to direct connection between the second and third capacitors C2 and C3, which are flying capacitors. Each can be set to about several ns each. For example, the sum of the first to fourth elapsed times may be set to 5% or less of one cycle of the DC-DC converter 300 . Also, the first to fourth elapsed times may be set to the same time.

The control signals CTR1 to CTR8 that control the plurality of transistors TR1 to TR8 may be generated by a control circuit provided separately from the DC-DC converter 300 . The control circuit also includes an active element, and therefore, a predetermined power supply voltage may be required for operation of the control circuit. In one embodiment of the present invention, a voltage output at a constant level during operation of the DC-DC converter 300 may be supplied as a power supply voltage of the control circuit. For example, the voltage of the fourth node N4 where the sixth and seventh transistors TR6 and TR7 and the fourth capacitor C4 are connected to each other may be supplied as a power supply voltage to the control circuit. As described above, the voltage of the fourth node N4 may be maintained at a level of 2*VIN/3 during the operation of the DC-DC converter 300 . Therefore, it is possible to secure the power supply voltage necessary for the operation of the control circuit only with the input voltage VIN input to the DC-DC converter 300 without a separate power supply.

For example, the fourth node N4 may receive current from the input voltage VIN, and may also supply current to the first node N1. The current supplied by the input voltage VIN and the current flowing out of the first node N1 are small in magnitude and can cancel each other out, so that the voltage at the fourth node N4 reaches a level of 2*VIN/3. It may not have a significant impact on retention.

Meanwhile, when the seventh transistor TR7 is turned off, the voltage of the fourth node N4 may be affected by the parasitic capacitance of the seventh transistor TR7. Also, even when the sixth transistor TR6 is turned off, the voltage at the fourth node N4 may be affected by the parasitic capacitance of the sixth transistor TR6. However, until the sixth transistor TR6 and the seventh transistor TR7 are completely turned off, the fourth node N4 is connected to the second capacitor C2 and the second capacitor C2 having a larger capacity than the fourth capacitor C4. 3 Since it is connected to the capacitor C3, the parasitic capacitance of the sixth transistor TR6 and the seventh transistor TR7 may also not have a large effect on the voltage of the fourth node N4.

On the other hand, parasitic capacitances of the first and third transistors TR1 and TR3 may significantly affect the voltage of the fourth node N4. The parasitic capacitance of each of the first and third transistors TR1 and TR3 may affect the voltage of the fourth node N4 when the first and third transistors TR1 and TR3 are turned on. there is. When the first transistor TR1 and the third transistor TR3 are turned on, other transistors connected to the fourth node N4, for example, the sixth transistor TR6 and the seventh transistor TR7 are turned on. Since it is in an off state, the voltage of the fourth node N4 may increase or decrease due to the parasitic capacitance.

In one embodiment of the present invention, the first transistor TR1 and the third transistor TR3 may be formed to have the same or similar sizes so as to stably maintain the voltage of the fourth node N4 . In this case, the current supplied from the parasitic capacitance of the first transistor TR1 to the fourth node N4 and the current flowing from the fourth node N4 to the parasitic capacitance of the third transistor TR3 have similar magnitudes. As a result, the voltage of the fourth node N4 can be stably maintained by canceling the effects of the first transistor TR1 and the third transistor TR3.

17 is a simplified block diagram of a power supply device according to an embodiment of the present invention.

Referring to FIG. 17 , a power supply device 400 according to an embodiment of the present invention may include a DC-DC converter 410, a control logic 420, a driver 430, and the like. The DC-DC converter 410 may step down the input voltage VIN to output the output voltage VOUT, and may be implemented according to at least one of the embodiments described above with reference to FIGS. 1 to 16 . For example, the DC-DC converter 410 may include a switched capacitor circuit including a plurality of transistors and a plurality of capacitors, and an LC filter connected to the switched capacitor circuit.

The control logic 420 and the driver 430 may be included in one control circuit. The control logic 420 may receive the output voltage VOUT of the DC-DC converter 410 and output a pulse width modulation (PWM) signal to the driver 430 . The driver 430 may use the PWM signal received from the control logic 420 to adjust the duty ratio of the control signals CTR that control the plurality of transistors included in the DC-DC converter 410 . For example, the output voltage VOUT is determined according to the duty ratio of the PWM signal output by the control logic 420 and the control signals CTR output by the driver 430, and the input voltage VIN and The ratio of the output voltage (VOUT) may vary.

A predetermined power supply voltage may be required for the operation of active elements included in the control logic 420 and the driver 430 . In one embodiment of the present invention, the control logic 420 and the driver 430 convert at least one of the voltages generated while the DC-DC converter 410 receives the input voltage VIN and operates as a power supply voltage. available.

Hereinafter, the operation of the power supply device according to an embodiment of the present invention will be described in more detail with reference to FIG. 18 .

18 is a schematic diagram illustrating a power supply device according to an embodiment of the present invention.

Referring to FIG. 18 , a power supply 500 according to an embodiment of the present invention may include a DC-DC converter 510, a control logic 520, a driver 530, and the like. The DC-DC converter 510 may be a circuit that steps down the input voltage VIN to output an output voltage VOUT, and the output voltage VOUT is input to the control logic 520 through the voltage divider circuit 505. can The voltage divider circuit 505 includes a plurality of resistors and at least one capacitor, and outputs the sensing voltage VSENS determined by the output voltage VOUT to the control logic 520 .

The control logic 520 may include an error amplifier 521, a comparator 522, a latch 523, a timing controller 524, and the like. The error amplifier 521 may output the error voltage VEA by amplifying a difference voltage between the sensing voltage VSENS and the reference voltage VREF. For example, when the output voltage VOUT increases and the difference between the sensing voltage VSENS and the reference voltage VREF increases, the error voltage VEA may also increase.

The comparator 522 may receive the error voltage VEA and the ramp voltage RMP and output a square wave signal. For example, referring to FIG. 18 , the error voltage VEA may be input to the inverting terminal of the comparator 522 and the ramp voltage RMP may be input to the non-inverting terminal of the comparator 522 . In the embodiment shown in FIG. 18, the duty ratio of the square wave signal output from the comparator 522 may decrease as the magnitude of the error voltage VEA increases.

The latch 523 and the timing controller 524 may generate a PWM signal using the output of the comparator 522 . For example, the timing controller 524 outputs a PWM signal having a duty ratio capable of minimizing a change in the output voltage VOUT based on the output of the comparator 522 and simultaneously described with reference to FIGS. 10 to 16 . Similarly, on/off timings of transistors included in the DC-DC converter 510 may be controlled. For example, the timing controller 524 controls each of the transistors included in the DC-DC converter 510 so that the input node receiving the input voltage VIN from the DC-DC converter 510 is not directly connected to the ground node. The on/off timing of can be controlled.

The driver 530 may output control signals for controlling transistors included in the DC-DC converter 510 . For example, the driver 530 may include a level shifter 531 and a gate driver 532, and the gate driver 532 includes first to third control signals VS1 to VS3 swinging at different voltage levels. ) can be output.

The control logic 520 and the driver 530 may operate by receiving a voltage generated during operation of the DC-DC converter 510 as a power supply voltage. For example, the control logic 520 may use a VIN/3 level voltage generated during operation of the DC-DC converter 510 as a power supply voltage. Therefore, the maximum level of the PWM signal output by the timing controller 524 also cannot exceed the VIN/3 level.

However, as in the embodiments described above with reference to FIGS. 1 to 16 , a voltage higher than the VIN/3 level may be applied to at least some of the plurality of transistors included in the DC-DC converter 510. there is. For example, in the embodiment shown in FIG. 2 , the first transistor TR1 receives the input voltage VIN as it is, and therefore, inputting a voltage of the VIN/3 level to the first transistor TR1 results in a first The transistor TR1 may not be normally turned on/off.

In order to solve this problem, in one embodiment of the present invention, the level shifter 531 is used to increase the level of the PWM signal output by the timing controller 524, and a control voltage signal suitable for turning on/off the transistors. s (VS1-VS3) can be created. Accordingly, the driver 532 may operate using the power supply voltage (VIN) level, the 2*VIN/3 level, the VIN/3 level, and the ground voltage level.

When the DC-DC converter 510 is implemented according to one of the embodiments described above with reference to FIGS. 1 to 16 , the output voltage VOUT may have a magnitude of VIN/3 or less. In one embodiment, the first control voltage signal VS1 may be a signal that swings between the level of the ground voltage and the level of VIN/3, and the second control voltage signal VS2 may be between the level of VIN/3 and the level of 2*VIN/3. It can be a signal that swings between levels. The third control voltage signal VS3 may be a signal that swings between a level of 2*VIN/3 and the level of the input voltage VIN.

The first to third control voltage signals VS1 to VS3 may be selectively input to the transistors according to the level of the voltage applied across each of the transistors included in the DC-DC converter 510 . Illustratively referring to the circuit diagram shown in FIG. 2 , the third control voltage signal VS3 swinging at the highest level may be input to the seventh transistor TR7 , and the third transistor TR3 may have an intermediate level. The second control voltage signal VS2 swinging at may be input. Meanwhile, the first control voltage signal VS1 swinging at the lowest level may be input to the fourth transistor TR4.

19A to 19C are graphs for explaining the operation of a power supply device according to an embodiment of the present invention.

19A is a graph showing a first control voltage signal VS1 , and the first control voltage signal VS1 may be a PWM signal swinging between a ground voltage level and a VIN/3 level. Referring to the circuit diagram of the DC-DC converter 100 according to the exemplary embodiment shown in FIG. 2 , the first control voltage signal VS1 is applied as a control signal to the fourth transistor TR4 and the fifth transistor TR5. can be entered. A signal complementary to the first control voltage signal VS1 may be input as a control signal to each of the second transistor TR2 and the eighth transistor TR8 .

19B is a graph showing the second control voltage signal VS2, and the second control voltage signal VS2 may be a PWM signal that swings between a VIN/3 level and a 2*VIN/3 level. Likewise, referring to the circuit diagram of the DC-DC converter 100 shown in FIG. 2 , the second control voltage signal VS2 may be input as a control signal to the third transistor TR3 and the sixth transistor TR6. .

19C is a graph showing the third control voltage signal VS3, and the third control voltage signal VS3 may be a PWM signal that swings between a level of 2*VIN/3 and the level of the input voltage VIN. Referring to the circuit diagram of the DC-DC converter 100 shown in FIG. 2 together, the third control voltage signal VS3 may be input as a control signal to the first transistor TR1 and the seventh transistor TR7.

20 to 22 are graphs for explaining the operation of a power supply device according to an embodiment of the present invention.

Hereinafter, its operation will be described with reference to a drawing of the power supply device 500 shown in FIG. 18 . First, FIG. 20 may be a graph illustrating an embodiment in which the output voltage VOUT of the DC-DC converter 510 maintains a stable state at a level similar to the target voltage. Referring to FIG. 20 , when the output voltage VOUT maintains a stable state at a level similar to the target voltage, the error amplifier 521 included in the control logic 520 may output the first error voltage VEA1. there is.

The comparator 522 may compare the first error voltage VEA1 with the ramp voltage RMP and output the first PWM signal PWM1. When the ramp voltage RMP is input to the non-inverting terminal of the comparator 522 and the first error voltage VEA1 is input to the inverting terminal, the first PWM signal PWM1 generates the first error voltage VEA1 as the ramp It may have a high level for a time shorter than the voltage RMP. The period TD of the first PWM signal PWM1 may be the same as the period of the ramp voltage RMP, and the first time T1 corresponds to a time when the first error voltage VEA1 is less than the ramp voltage RMP. And, the second time T2 may correspond to a time when the first error voltage VEA1 is greater than the ramp voltage RMP.

Next, FIG. 21 may be a graph illustrating an embodiment in which the output voltage VOUT of the DC-DC converter 510 decreases to a level smaller than the target voltage. Referring to FIG. 21 , as the output voltage VOUT decreases to a level lower than the target voltage, the error amplifier 521 may output a second error voltage VEA2 smaller than the first error voltage VEA1.

The comparator 522 may compare the second error voltage VEA2 with the ramp voltage RMP and output the second PWM signal PWM2. 20 , the ramp voltage RMP may be input to the non-inverting terminal of the comparator 522, and the first error voltage VEA1 may be input to the inverting terminal. Therefore, the second PWM signal PWM2 has a high level during the first time T1 when the second error voltage VEA2 is less than the ramp voltage RMP, and the second error voltage VEA2 is less than the ramp voltage RMP. It may have a low level during the large second time period T2.

Compared to FIG. 20, in the embodiment shown in FIG. 21, since the second error voltage VEA2 has a lower level than the first error voltage VEA1, one cycle TD of the second PWM signal PWM2 The first time T1 may increase and the second time T2 may decrease. As a result, as the first time T1, which is the time for charging energy to the inductor connected to the output terminal of the switched capacitor circuit in the DC-DC converter 510, is relatively increased, the output voltage VOUT may increase again.

Next, FIG. 22 may be a graph illustrating an embodiment in which the output voltage VOUT of the DC-DC converter 510 increases to a level greater than the target voltage. Referring to FIG. 22 , as the output voltage VOUT increases greater than the target voltage, the error amplifier 521 may output a third error voltage VEA3 greater than the first error voltage VEA1.

The comparator 522 may output a third PWM signal PWM3 by comparing the third error voltage VEA3 input through the inverting terminal with the ramp voltage RMP input through the non-inverting terminal. The third PWM signal PWM3 has a high level during the first time T1 when the third error voltage VEA3 is less than the ramp voltage RMP, and the third error voltage VEA3 is greater than the ramp voltage RMP. It may have a low level during the second time period T2.

Compared to the graph of FIG. 20, in the embodiment shown in FIG. 22, since the third error voltage VEA3 has a higher level than the first error voltage VEA1, one period of the third PWM signal PWM3 ( Within TD), the first time T1 may decrease and the second time T2 may increase. As a result, as the first time T1, which is the time for charging energy in the inductor connected to the output terminal of the switched capacitor circuit in the DC-DC converter 510, is relatively short, the output voltage VOUT may decrease.

As described with reference to FIGS. 20 to 22 , the control logic 520 and the driver 530 adapt the duty ratio of the PWM signal according to the increase/decrease of the output voltage VOUT of the DC-DC converter 510. By adjusting the voltage positively, the DC-DC converter 510 can be stably driven.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

10, 100, 200, 300, 410, 510: DC-DC converter
400, 500: power unit
420, 520: control logic
430, 530: driver
VIN: input voltage
VOUT: output voltage
C1: first capacitor
C2: second capacitor
C3: third capacitor
C4: fourth capacitor
L: Inductor
COUT: output capacitor

Claims (10)

A first transistor connected between a first capacitor and an input node, a second transistor connected between the first capacitor and the second capacitor, and between a first node between the second capacitor and the second transistor and a third capacitor a first switching circuit including a third transistor coupled thereto, and a fourth transistor coupled between the third capacitor and a ground node;
A fifth transistor connected between the second capacitor and the third capacitor, a sixth transistor and a seventh transistor connected between the first capacitor and the third capacitor, and a connection between the first capacitor and the ground node. a second switching circuit including an eighth transistor;
a fourth capacitor connected to a node between the sixth transistor and the seventh transistor; and
an LC filter connected to a third node to which the first capacitor, the second transistor, and the eighth transistor are connected; A DC-DC converter comprising a.
According to claim 1,
wherein each of the first, second, fifth, and sixth transistors is a PMOS transistor, and each of the third, fourth, seventh, and eighth transistors is an NMOS transistor.
According to claim 1,
The first to eighth transistors and the fourth capacitor are included in one integrated circuit chip,
The first to third capacitors and the LC filter are elements external to the integrated circuit chip, the DC-DC converter.
According to claim 1,
The LC filter includes an inductor connected to the third node, and an output capacitor connected to the inductor.
According to claim 1,
The voltage across the first capacitor is greater than the voltage across each of the second capacitor and the third capacitor, the DC-DC converter.
a first transistor providing a first current path charging a first capacitor between an input node and an output node for a first time;
a second transistor providing a second current path discharging a second capacitor between a ground node and the output node during the first time period;
a third transistor and a fourth transistor providing a third current path discharging a third capacitor between the ground node and the output node during the first time period;
fifth to eighth transistors connecting the first to third capacitors to each other during a second time period different from the first time period; and
an LC filter having an inductor coupled to the output node and an output capacitor coupled to the inductor; Including,
The second transistor provides the second current path and the third current path, the DC-DC converter.
According to claim 6,
The sum of the first time and the second time corresponds to one period of each of the control signals controlling the first to eighth transistors;
The voltage of the output node is determined according to the ratio of the first time and the second time, DC-DC converter.
According to claim 7,
In each of the control signals, the one period includes a first elapsed time and a second elapsed time overlapping with at least one of the first time and the second time,
During the first elapsed time, the fourth transistor among the first to eighth transistors is turned on and the first to third and fifth to eighth transistors are turned off;
During the second elapsed time, the eighth transistor among the first to eighth transistors is turned on and the first to seventh transistors are turned off.
According to claim 7,
In each of the control signals, a third elapsed time and a fourth elapsed time are included between the second time of the first cycle and the first time of the second cycle immediately after the first cycle,
During the third elapsed time, the eighth transistor among the first to eighth transistors is turned on and the first to seventh transistors are turned off;
During the fourth elapsed time, the fourth transistor among the first to eighth transistors is turned on and the first to third and fifth to eighth transistors are turned off.
a DC-DC converter comprising a switched capacitor circuit having a plurality of transistors and a plurality of capacitors, and an LC filter having an inductor and an output capacitor, and generating an output voltage by stepping down a level of an input voltage;
Control logic for outputting a pulse width modulation (PWM) signal by comparing the output voltage with a predetermined reference voltage; and
a driver outputting control signals for controlling the plurality of transistors based on the PWM signal; Including,
The control logic and the driver operate by receiving a power voltage smaller than the input voltage and larger than the output voltage from the DC-DC converter.

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