KR20230043983A - Switch FET body current management device and method - Google Patents

Abstract

A method and apparatus for reducing gate induced drain leakage current in an RF switch stack are disclosed. The device uses multiple discharge paths and/or lower negative body bias voltages without compromising the power handling and non-linearity performance of the power switches. Also, a more compact bias voltage generation circuit with a smaller footprint can be implemented as part of the disclosed device.

Description

Switch FET body current management device and method

CROSS REFERENCES TO RELATED APPLICATIONS

This application is filed on July 31, 2020 entitled "Methods And Devices To Generate Gate Induced Drain Leakage Current Sink Or Source Path For Switch FETs" and is filed under US Patent Application Serial No. 16/945,283, filed on July 27, 2021. U.S. Patent Application Serial No. 17/386,374 filed on July 27, 2021 entitled "Switch FET Current Management Devices and Methods" and filed on July 27, 2021 entitled "Switch FET Current Management Devices and Methods" Priority is claimed to Application No. 17/386,409, the entire contents of all three of which are incorporated herein by reference.

technical field

The present disclosure relates to a switch FET, and more particularly to a device having a switch FET and a discharge path using a body current management method and/or a switch FET implementing a reduced negative body bias voltage for body current management. will be.

When designing communication systems, RF switches are typically implemented in a stacked configuration due to the large RF power handling requirements of these switch stacks. 1A shows a prior art field effect transistor (FET) switch stack 100 including transistors T ₁ , ..., T _n in a series arrangement. As shown in the drawing, the FET switch stack 100 includes a body resistor ladder including body resistors R _B1 , ..., R _Bn+1 , drain-source resistors R _DS1 , ..., R _DSN ) and a gate resistor structure on the gate side of the transistors. The switch stack 100 is biased using bias voltages VB and VG generated by a bias generation circuit (not shown).

In real world conditions, especially stacked switches that experience large RF swings during the off state, each transistor in the stack produces an undesirable gate induced drain/body leakage current (GIDL) that increases as the peak of the RF swing increases. will do The GIDL current flows through the body resistor ladder in the direction of arrow 110 as shown in FIG. 1A. Due to the unwanted flow of GIDL current, the DC voltage distribution across the body resistor ladder is modified. In other words, the various switch stack nodes in the body resistor ladder will experience different unwanted DC bias voltages than the biasing circuit provides to those nodes in the absence of this leakage current. Throughout the specification, the undesirable effect of the GIDL current on the DC bias voltage distribution across the stack is referred to as the "de-biasing" effect.

The debiasing effect is further illustrated by curve 102 in FIG. 1B , which shows exemplary DC average voltage profiles for the bodies of the transistors of switch stack 100 in FIG. 1A , relative to the location of the transistors in the stack. is plotted as The DC voltages of the FET body terminals decrease from top to bottom of the stack. That is, due to imbalance in voltage distribution due to unwanted GIDL current, the voltage of the body terminal of the transistor Tn becomes the highest positive voltage and that of the transistor T1 becomes the highest negative voltage.

Body debiasing, as described above, causes premature failure of transistors in FET switch stacks, particularly transistors placed closer to the top of the stacks. Also, the GIDL current must be sinked by a biasing circuit that provides bias voltages for the switch stack. The higher the GIDL current, the more complex the design of the bias generator due to the higher current strength capability requirements. Because of this, more design space may be required to accommodate the bias generator. In addition, the DC current consumption of the bias circuit also increases.

Referring to FIG. 1A , linearity performance is improved by applying a higher negative biasing voltage (VB) when the RF switch is off in operating conditions. However, a higher negative biasing voltage (VB) requires more complex biasing circuitry that occupies a larger area on the chip. DC current consumption also increases.

Accordingly, a method and apparatus are provided for reducing the undesirable effects of GIDL current while maintaining a simpler, cheaper, and smaller biasing circuit without compromising the linearity performance and power handling capability of RF switch stacks during off-state operation. need. There is also a need for methods and devices that help maintain proper voltage distribution across the stack to prevent the possibility of premature voltage breakdown.

The presently disclosed method and apparatus solve the above-mentioned problems and provide solutions to the above-described challenges.

According to a first aspect of the present disclosure, there is provided a field effect transistor (FET) switch stack comprising series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal. s - the first terminal is configured to receive an input radio frequency (RF) signal; A body resistive ladder coupled to the first terminal, the body resistive ladder including a plurality of body resistors connected in series, each body resistor coupled across body terminals of corresponding adjacent ones of the FETs connected in series. -; A first diode stack composed of one or more diodes and having a first cathode terminal connected to the first terminal and a first anode terminal connected to a body terminal of a first one of the series connected FETs.

According to a second aspect of the present disclosure, there is provided a field effect transistor (FET) switch stack comprising series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal. s - the first terminal is configured to receive an input radio frequency (RF) signal; A drain-source resistive ladder coupled to the first terminal, the drain-source resistive ladder comprising a plurality of drain-source resistors connected in series, each drain-source resistor having a resistance of corresponding adjacent FETs of the FETs connected in series. coupled across the drain-source terminals -; A first diode stack composed of one or more diodes and having a first anode terminal connected to the first terminal and a first cathode terminal connected to a source terminal of a first one of the series connected FETs.

According to a third aspect of the present disclosure, a method of driving bias voltages of a FET switch stack toward a voltage distribution across the FET switch stack is disclosed, the method comprising: a radio frequency (RF) voltage source across the FET switch stack from an RF signal; generating them; and creating a current discharge path to form a voltage distribution across the FET switch stack.

According to a fourth aspect of the present disclosure, a field effect transistor (FET) switch stack is provided, the FET switch stack coupled in series with one end coupled to a first terminal and the other end coupled to a second terminal. FETs, a first terminal configured to receive an input radio frequency (RF) signal; a body resistor ladder coupled to the first terminal, the body resistor ladder including a plurality of body resistor elements connected in series, each body resistor element coupled across body terminals of corresponding adjacent FETs of the series connected FETs; ; and a body current management circuit coupled to the body resistor ladder, the FET switch stack configured to receive a first bias voltage at the gate bias terminal of the FET switch stack and a second bias voltage at the body bias terminal of the FET switch stack. made up; In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages; In the off state, the second bias voltage has a lower negative voltage than the first bias voltage, and the body current management circuit is configured to provide one or more current discharge paths for gate induced drain leakage current.

According to a fifth aspect of the present disclosure, comprising series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal, wherein the first terminal receives an input radio frequency (RF) signal. A method of biasing a radiofrequency (RF) field-effect transistor (FET) switch stack in an off state is disclosed, the method comprising: applying a negative gate bias voltage to gate terminals of series-connected FETs; applying a negative body bias voltage to body terminals of the series connected FETs, the body bias voltage having a lower negative voltage than the gate bias voltage; in an off state of the RF FET switch stack, applying an RF signal across the RF FET switch stack; and while applying an RF signal, discharging gate induced drain leakage current through one or more current discharge paths, wherein the discharge pulls down voltages at body terminals of the series connected FETs at negative voltages higher than the body bias. - include

According to a sixth aspect of the present disclosure, a field effect transistor (FET) switch stack is provided, the FET switch stack coupled in series with one end coupled to a first terminal and the other end coupled to a second terminal. FETs, a first terminal configured to receive a radio frequency (RF) signal; a body resistor ladder coupled to the first terminal, the body resistor ladder including a plurality of body resistor elements connected in series, each body resistor element coupled across body terminals of corresponding adjacent FETs of the series connected FETs; ; and i) a diode element stack comprising two or more diode elements, the diode element stack coupled between the body resistor ladder and the first terminal, and ii) one or more additional diode elements coupled to the body resistor ladder. It includes a first diode element array that

According to a seventh aspect of the present disclosure, a method for controlling a gate-induced drain leakage current in an off state of a radio frequency (RF) switch stack, the RF switch stack comprising i) series connected FETs configured to receive an RF signal and ii) ) a body resistor ladder coupled to body terminals of series connected FETs, the method comprising: applying an RF signal to an RF switch stack; generating a first current discharge path for a gate induced drain leakage current through the body resistor ladder during a first time interval in an off state of the RF switch stack; and generating a second current discharge path for a gate induced drain leakage current through the body resistor ladder for a second time interval in the off state of the RF switch stack, wherein the second time interval comprises the first current discharge path and During the first overlapping time interval in the OFF state of the RF switch in which all of the second current discharge paths are generated, the first time interval partially overlaps in time.

The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present disclosure will become apparent from the detailed description, drawings and claims.

1A shows a prior art FET switch stack.
FIG. 1B shows a prior art averaged DC voltage profile across the bodies of the transistors of a switch stack relative to the position of those transistors within the stack when the FET switch stack is in the off state.
2A illustrates an exemplary FET switch stack according to one embodiment of the present disclosure.
2B shows simulation results representing exemplary RF signal waveforms according to an embodiment of the present disclosure.
2C shows example changes in the DC voltage of a node in the body resistor ladder of a switch stack according to one embodiment of the present disclosure.
3A illustrates an exemplary FET switch stack according to one embodiment of the present disclosure.
FIG. 3B shows the change in DC voltage of nodes in a drain-source resistive ladder relative to the location of these nodes in an exemplary FET switch stack according to one embodiment of the present disclosure.
3C illustrates an exemplary FET switch stack according to one embodiment of the present disclosure.
4A-4B illustrate exemplary FET switch stacks implemented in a series configuration according to one embodiment of the present disclosure.
5A illustrates an exemplary FET switch stack according to one embodiment of the present disclosure.
5B illustrates a portion of an exemplary FET switch stack according to one embodiment of the present disclosure.
5C illustrates an exemplary graph according to one embodiment of the present disclosure.
5D illustrates a portion of an exemplary FET switch stack according to one embodiment of the present disclosure.
5E depicts an exemplary graph according to one embodiment of the present disclosure.
5F illustrates a portion of an exemplary FET switch stack according to one embodiment of the present disclosure.
5g-5h and FIG. 6 illustrate exemplary FET switch stacks in accordance with embodiments of the present disclosure.
7 depicts an exemplary graph according to embodiments of the present disclosure.
8 shows a block diagram of an exemplary RF circuit in accordance with one embodiment of the present disclosure.
9 shows a bias generation circuit.
10-11 show example graphs in accordance with embodiments of the present disclosure.
12 shows a block diagram of an exemplary RF circuit according to one embodiment of the present disclosure.
Like reference numbers and designations in the various drawings indicate like elements.

2A illustrates an exemplary FET switch stack 200A, specifically a stack of at least four switches, according to one embodiment of the present disclosure. The FET switch stack 200A has one end connected to the RF port RF and the other end connected to a reference voltage (eg, ground). During operating states, an RF signal is passed through the RF port (RF) to the RF switch stack 200A. The FET switch stack 200A includes transistors T _i ,...,T _N in a series arrangement. This FET switch stack has a body resistor ladder including body resistors (R _B1 , ..., R _Bn+1 ), a drain-source including drain-source resistors (R _DS1 , ..., R _DSn ). It can be biased using a resistor ladder and a gate resistor structure on the gate side of the transistors. Also shown in FIG. 2A are bias voltages VB and VG used to bias the FET switch stack 200A. The bias voltages VB and VG may be generated by a bias voltage generating circuit (not shown for simplicity). In operating states, when the FET switch stack 200A is in an off state, the bias voltages VB and VG may be negative bias voltages.

With continuing reference to FIG. 2A , FET switch stack 200A includes diode stacks 201 and 202 , each coupled across one or more resistors of the body resistor ladder. According to embodiments of the present disclosure, diode stack 201 includes one or more diodes D ₁ , ... connected in series, having terminals A1 , K1 to which diode stack 201 is connected to a body resistor ladder. D _M ) is composed of. Further, the diode stack 202 includes one or more diodes D' ₁ , ..., D' _N connected in series, having terminals A2 and K2 to which the diode stack 202 is connected to the body resistor ladder. consists of Throughout the specification, the term diode is used to mean the diodes themselves as well as the diode-connected transistors. As long as the maximum positive voltage RF signal is applied to the FET switch stack 200A, the diode stack 201 is in an off state, and the voltage across the nodes of each diode in the diode stack 201 is within the voltage reliability limit of the diode. The smallest number of diodes connected in series can be used in the diode stack 201. As long as the maximum negative voltage RF signal is applied to the FET switch stack 200A, the diode stack 202 is in an off state, and the voltage across the nodes of each diode in the diode stack 201 is within the voltage reliability limit of the diode. The fewest number of diodes connected in series can be used in diode stack 202 .

Other embodiments are also contemplated that include only one of the two diode stacks 201 or 202 in accordance with the teachings of this disclosure, where only one existing diode stack can have more than one diode. In a preferred embodiment, terminal K1 is connected to RF port (RF), terminal A1 is connected to a node in the body resistor ladder, terminal A2 is connected to a node in the body resistor ladder, and terminal K2 is connected to a node in the body resistor ladder. ) is connected to a reference voltage (eg ground). Also, any of the resistors R _B1 , ..., R _Bn+1 may be divided into two or more resistors. Terminal A1 or A2 can be connected to the node between these divided resistors. Also, as shown in FIG. 2A , diode stacks 201 and 202 may be connected to opposite polarities across the body resistor ladder. For example, as described in more detail later, in operating conditions, diode stack 202 conducts current in a top-down direction, while diode stack 201 conducts current in a bottom-to-top direction. Also as mentioned above, any diode in diode stacks 201 or 202 may be implemented using diode connected transistors.

As mentioned earlier, undesirable GIDL currents in switch stacks cause debiasing issues that lead to possible premature failure of transistors in the stack, especially for transistors closer to the RF port. Also, the GIDL current must also be sinked (i.e. discharged out of the stack). Referring further to FIG. 2A , the diode stack 201 solves the deviceing problem by sinking the GIDL current to the RF port, and the diode stack 202 solves the deviceing problem by sinking the GIDL current to the ground. do.

With continued reference to FIG. 2A , the FET switch stack 200A receives an RF signal through an RF port (RF). During a negative swing of the RF signal when the FET switch stack 200A is in an off state, the diode stack 201 is turned on, thereby creating a discharge path for the GIDL current through the RF port RF. On the other hand, during the positive swing, the diode stack 202 is turned on, creating a discharge path for the GIDL current through ground. One skilled in the art will understand that the in-tandem use of the two diode stacks 201 and 202 also provides more symmetry to the structure of the FET switch stack 200A, thereby improving the switch stack's nonlinear distortion performance (e.g., harmonics). reduction) will be understood. It is also understood that such symmetry is optional and not required.

In the paragraphs below:

- V _RF+ and V _RF- represent peak positive and peak negative applied RF voltages, respectively;

● R _B1 = R _Bn+1 =R/2 and R _B2 = R _B3 =......=R _Bn =R,

● V _RB+ and V _RB- represent the peak positive and peak negative RF voltage drops across the R body resistor of the body resistor ladder, respectively;

- m and k represent the number of diodes of the diode stacks 201 and 202, respectively, where m and k may be the same or different, and

• V _th represents the threshold voltage of the diodes in the diode stacks 201 or 202.

By way of example and not limitation, if an RF voltage with a peak of 100V is applied to a switch stack with 25 transistors, then V _RB+ = 100/25 = 4V and V _RB- = -100/25 = -4V.

Referring again to FIG. 2A and using the above definition, during a negative swing of the applied RF voltage, if (X * V _RB- ) - VB < m * V _th , the diode stack 201 conducts, Start discharging GIDL current. Parameter X is a ratio defined based on the resistances of the body resistors to which the diode stack 201 is coupled. As an example for further clarification, for the embodiment shown in FIG. 2A , the parameter X is defined as X = (R _Bn + R _Bn+1 ) / R _Bn = (R + R/2) / R = 3/2 do. During the positive swing of the applied RF voltage, the diode stack 202 begins to conduct when (Y * V _RB+ ) + VB > k * V _th , where Y is the diode stack 202 similar to the case above. For Y = (R _B1 + R _B2 ) / R _B2 = (R/2 + R) / R = 3/2. During the positive swing of the applied RF signal, the diode stack 201 is in the off state and the peak voltage Vr1 across each diode in the diode stack 201 is Vr1 = ((X* V _RB+ ) - VB ) / m can be obtained On the other hand, during the negative swing of the applied RF voltage, the diode stack 202 is in the off state and the peak voltage Vr2 across each diode in the diode stack 202 is Vr2 = (-Y * V _RB- ) - VB) / can be obtained with k. According to embodiments of the present disclosure, Vr1 and Vr2 are less than the peak voltage reliability limit of reverse-biased-diodes in diode stacks 201 and 202 .

Figure 2b shows some simulation results showing the RF current flowing from the RF port through the body resistor ladder to ground as a function of time. Curve 210 represents the case prior to implementing the teachings of this disclosure (ie, without diode stacks). As can be seen, curve 210 is asymmetric with respect to the time axis (ie, amplitudes a1 and a2 are not equal). On the other hand, curve 220 represents the case after implementing the diode stacks. As can be seen, as a result of implementing the diode stacks, the RF current is more symmetrical in terms of positive peak to negative peak behavior. Finally, curve 230 shows the difference between curves 210 and 220 to highlight the positive impact of implementing diode stacks to mitigate the negative impact of undesirable GIDL current.

Figure 2c shows the DC voltage of nodes in the body resistor ladder versus the change in position of these nodes in the stack. Curves 260 and 270 represent variations without and with implementation of the teachings of this disclosure (ie, implementation of diode stacks 201 and 202 of FIG. 2A ), respectively. As previously mentioned, in the absence of implementation of the teachings of this disclosure, the DC voltage for each element from top to bottom falls as a decreasing function of its position in the stack. On the other hand, if there is an implementation of diode stacks, there is much less device-to-element variation of the DC voltage with respect to position: the curve is flatter and the voltage distribution is more uniform.

3A illustrates an exemplary FET switch stack 300A, in particular a stack of at least four switches, according to a further embodiment of the present disclosure. Although there are similarities between the structure of the FET switch stack 300A and the structure of the FET switch stack 200A of FIG. 2A, the biasing scheme of the FET switch stack 300A is positive logic. ) is different in that it works as In other words, in the preferred embodiment, when the FET switch stack 300A is in the off state during operation, the bias voltage VG is 0 V and the bias voltage VD applied to the drain-source resistor ladder is a positive bias voltage. am. Also, in the embodiment of FIG. 3A, capacitors C1 and C2 previously placed in the body resistor ladder of FIG. 2A are now designated (C' ₁ , C' ₂ ) and placed in the drain-source resistor ladder. Similar to that described with respect to the embodiment of FIG. 2A , the GIDL current has the same negative effect devising the FET switch stack 300A, except that the direction of current in the drain-to-source resistor ladder is different and is from bottom to top. Crazy. The reason for this difference is that when the switch stack FETs are in the off state, the GIDL current flows into the drain terminals and out of the body terminals of the FETs. In other words, going from drain-source resistor R _DS1 to drain-source resistor R _DSn , the average DC voltages at various nodes of the drain-source resistor ladder decrease. Also, unlike the diode stack 201, the diode stack 301 shown in FIG. 3A is connected to both ends of one or more drain-source resistors of the drain-source resistor ladder, and the diode stack 301 is connected in series with diodes ( D1, ...DM) and has terminals A3, K3. In a preferred embodiment, anode terminal A3 is connected to RF port RF and cathode terminal K3 is connected to a node other than ground in the drain-source resistor ladder.

2A and 3A, since the drain is biased at a positive voltage and the current flowing in the drain-source ladder and the current flowing in the body resistor ladder have opposite directions, the diode stacks are implemented with opposite polarities. The function of diode stack 301 is similar to that previously described with respect to diode stack 201, except that it is. In operating states, when the FET switch stack 300A is in the off state, during the positive swing of the applied RF signal, the diode stack 301 is in the on state (conductive), thus closing the drain-source resistor ladder. It creates a source path through the RF port (RF) for the undesirable GIDL current flowing through it. During negative swings of the applied RF signal, the diode stack 301 is in an off state (non-conducting).

FIG. 3B shows the DC voltage of nodes in the drain-source resistor ladder of FIG. 3A versus the variation of the location of these nodes in the stack. Curves 320 and 330 represent variations with and without an implementation of the teachings of this disclosure (ie, an implementation of the diode stack 301 of FIG. 3A ), respectively. As mentioned earlier, in the absence of a diode stack implementation, the DC voltage is an increasing function of position within the stack. Also shown, if there is an implementation of a diode stack, there is much less element-wise variation of the DC voltage with respect to position: the curve is flatter and the voltage distribution is more uniform.

3C illustrates an exemplary FET switch stack 300C, in particular a stack of at least four switches, according to a further embodiment of the present disclosure. The FET switch stack 300C functions as a positive logic, and the diode stack 302 used for the FET switch stack 300C to operate in tandem with the diode stack 301 to further overcome the negative effects of the GIDL current. Except for further inclusion, the principle of operation is similar to that described with respect to the FET switch stack 300A. In operating states, when the FET switch stack 300C is in the off state, during negative swings of the applied RF signal, the diode stack 302 turns on to provide for undesirable GIDL current a source path through ground. provides The diode stack 302 is in an off state during the positive swing of the applied RF signal. Similar to previously described, adding the stack 302 provides more symmetry to the structure, thereby improving the overall nonlinear distortion performance.

In the embodiments shown in Figures 2a, 3a and 3c, the FET switch stacks are implemented according to a shunt configuration, ie between the RF terminal and the reference or ground terminal. However, the teachings of this disclosure are equally applicable in scenarios where a FET switch stack is implemented based on a series configuration, ie between two RF terminals. 4A illustrates an FET switch stack 400A, in particular a stack of at least four switches, according to embodiments of the present disclosure. The FET switch stack 400A is basically the same as the FET switch stack 200A of FIG. 2A but implemented in a series configuration. An RF signal is input from the RF port RF1 and output from the RF port RF2. For better symmetry considering the serial configuration of the FET switch stack 400A, the bias voltages VG and VB are at the middle of each gate and body ladder rather than at the bottom of the ladders as in the FET switch stack 200A of FIG. 2A. is authorized to In a preferred embodiment, when the FET switch stack 400A is in an off state during operation, the bias voltages VG and VB may be negative bias voltages.

4B illustrates an FET switch stack 400B, in particular a stack of at least four switches, according to embodiments of the present disclosure. The FET switch stack 400B is basically the same as the FET switch stack 300C of FIG. 3C but implemented in an RF1-RF2 series configuration. An RF signal is input from the RF port RF1 and output from the RF port RF2. For better symmetry considering the series configuration of the FET switch stack 400B, the bias voltages VG and VD are applied at each gate and drain-source ladder rather than at the bottom of the ladders as in the FET switch stack 300C of FIG. 3C. is applied in the middle of In a preferred embodiment, when FET switch stack 400B is in the off state during operation, bias voltage VG is about 0V and bias voltage VD can be a positive bias voltage.

5A illustrates an exemplary FET switch stack 500A according to a further embodiment of the present disclosure. The structure and function of the switch stack 500A of FIG. 5A is similar to that described for the switch stack 200A of FIG. 2A except for some additional elements and functions described in detail below.

FET switch stack 500A includes diode stacks 501A and 502A, each coupled across one or more resistors of the body resistor ladder. According to embodiments of the present disclosure, diode stack 501A includes one or more diodes D1, ... in series, having terminals A1, K1 coupled to the body resistor ladder. DM). Resistor R0 connecting diode D1 to the body resistor ladder is optional, i.e., if resistor R0 is not used, diode D1 is connected directly to the body resistor ladder. Diode stack 502A is composed of one or more diodes D' ₁ ,..., D' _N connected in series, with terminals A2 and K2 connected to the body resistor ladder of diode stack 302A. . Resistor R0' connecting diode D'k to the body resistor ladder is optional.

As already mentioned in the previous embodiments, the term diode will be used to mean the diode itself as well as the diode-connected transistors. Still referring to FIG. 5A , the number of diodes connected in series used in the diode stack 501A in this embodiment also depends on the maximum positive voltage RF signal applied to the FET switch stack 500A and the diode stack 501A turned off. state, and the voltage across the nodes of each diode in the diode stack 501A can vary as long as it is within the voltage reliability limits of the diode. Similar considerations apply to diode stack 502A.

According to the embodiment shown in FIG. 5A, the FET switch stack 500A comprises a “horizontal” or “rung” diode D0 and an optional resistor RF arranged in series with an optional resistor R1. ) and a horizontal or transverse diode D0' arranged in series. The series combination of resistor R1 and diode D0 is connected at one end to node P1 of the body resistor ladder and at the other end to the node of a "vertical" or "rail" diode stack 501A ( connected to P2). The series combination of resistor R1' and diode D0' is connected at one end to node P3 of the body resistor ladder and at the other end to node P4 of a "vertical" or "rail" diode stack 502A. ) is connected to

The presence of transverse diodes DO and DO' is a discharge path for the GIDL current during the off state of the FET switch stack which is added to the discharge paths 510A and 511A provided by the stacks of rail diodes 501A and 502A. 513A, 512A. As will be explained in more detail later, when the FET switch stack is in the off state, two current discharge paths 510A and 513A are formed during negative RF signal swings to at least partially carry the undesirable GIDL current. Similarly, during positive RF signal swings, two current discharge paths 511A and 512A are formed to deliver GIDL currents generated during such swings to ground.

In accordance with the teachings of this disclosure, the FET switch stack 500A of FIG. 5A can be implemented in both a shunt (as shown) or series (where the bottom is coupled to the RF port instead of a reference voltage) configuration. Also, with continued reference to FIG. 5A , according to the teachings of this disclosure:

● Proceeding from the top of the body resistor ladder to the bottom, nodes P1 and P3 can be located at any point in the body resistor ladder and

● Node P2 may be located anywhere between the cathode of diode D1 at the bottom of diode stack 501A and the anode of diode DM at top of diode stack 501A;

- node P4 may be located anywhere between the anode of diode D'N at the bottom of diode stack 501A and the cathode of diode D'1 at top of diode stack 502A;

• Any of the resistors RB ₁ , ..., R _Bn+1 can be divided into two or more series resistors with common connection points serving as tapping points. Nodes P1 and P3 may be located at these tapping points. As an example, as shown in FIG. 5A, a series combination of body resistors RB2 and RB3 is coupled across the bodies of transistors T1 and T2. In this example, node P3 is between body resistors RB2 and RB3.

- As also mentioned in the next paragraph, additional paths are devised that are added to paths 512A and 513A by introducing transverse diodes (and optional associated resistors) added to diodes DO and DO'. It can be.

With continued reference to FIG. 5A , for purposes of simplicity and illustration, at the top of the FET switch stack 500A, a node on the body resistor ladder (i.e., P1) is connected to a corresponding node P2 in the diode stack 501A. Only one resistor-diode pair (R1, DO) is shown. Similarly, only one resistor-diode pair (R1', DO') connecting a node on the body resistor ladder (i.e., P3) to a corresponding node P4 in diode stack 502A is also in FET switch stack 500A. shown below. However, two or more of these transverse diodes or transverse diode-resistor combinations couple two or more nodes of the body resistor ladder to corresponding nodes of diode stack 501A and/or such transverse diodes or transverse diodes Other embodiments may be contemplated in which two or more of the diode-resistor combinations couple two or more nodes of the body resistor ladder to corresponding nodes of the diode stack 502A. Additional diodes and/or diode-resistor pairs create additional current discharge paths, thereby further reducing the negative effects of the undesirable GIDL current.

To further clarify the concepts disclosed above, reference is made to FIG. 5B which illustrates a portion of an exemplary implementation of the FET switch stack 500A of FIG. 5A. For simplicity, only a portion of the FET switch stack is shown. Diode stack 501B is an exemplary implementation of diode stack 501A of FIG. 5A and includes diodes D1,..., D6. A portion of the body resistor ladder including body resistors RB11, ..., RB15 is also shown. As can be seen in this exemplary embodiment, the two resistor-diode pairs (R11, D01 and (R12, D02)) connect two respective nodes on the resistor body ladder to corresponding corresponding nodes in diode stack 501B. coupling to nodes.

5C depicts an example graph in accordance with the teachings of this disclosure. Curve 550 represents the amplitude of an RF signal received through the RF port (RF) of FIG. 5A versus time, which consists of a positive RF signal swing (left) and a negative RF signal swing (right). Referring to FIGS. 5A, 5B, and 5C, when the FET switch stack 500A is in the off state, the diode stack 501B is turned on during the first time interval ΔT ₁ of the negative swing of the RF signal. to create a first discharge path for the GIDL current through resistor R0, in direction 510B, through RF port RF. Also, during the second time interval ΔT ₂ , diode D02 is turned on, thereby providing an additional second response to the GIDL current through resistor R12, through RF port RF, in direction 514B. A discharge path can be created. During a third time interval ΔT ₃ , diode D01 is turned on to create a third discharge path for GIDL current through resistor R11 through RF port RF in direction 513B. can do. In a preferred embodiment, as shown in FIG. 5C, the first discharge path in direction 510B is active during time intervals ΔT ₁ , ΔT ₂ , ΔT ₃ , and the second discharge path 514B is active during time intervals ΔT 1 , ΔT 2 , ΔT 3 . ΔT ₂ , ΔT ₃ , and the third discharge path 513B is active during the time interval ΔT ₃ . In other words, in this preferred embodiment, during a negative swing of the RF voltage, the various diodes are turned on at different times in the following order: diode stack 501B turns on first, then diode D02 It is turned on later, and finally the diode D01 is turned on.

Similar to previously shown in FIG. 5B, FIG. 5D shows another portion of an exemplary implementation of the FET switch stack 500A of FIG. 5A. For simplicity, only a portion of the FET switch stack is shown. Diode stack 501D, which is an exemplary implementation of diode stack 501A of FIG. 5A, includes diodes D1', ..., D5'. The portion of the body resistor ladder comprising body resistors RB11', ..., RB14' is also shown. As can be seen in this exemplary embodiment, the two resistor-diode pairs (R11', D01' and (R12', D02') connect two respective nodes on the resistor body ladder to the diode stack 501D. ) to the corresponding nodes in

Similar to previously shown in FIG. 5C , FIG. 5E depicts an example graph in accordance with the teachings of this disclosure. Curve 550 represents RF signal amplitude versus time received via the RF port (RF) of FIG. 5A. 5A, 5D, and 5E, when the FET switch stack 500A is in an off state, the diode stack 501D is turned on during the first time interval ΔT ₁ 'of the positive swing of the RF signal, Creates a first discharge path for the GIDL current through resistor RO', in direction 511D, through ground. Also, during the second time interval ΔT ₂ ′, diode D01′ is turned on, thereby providing a second discharge path for the GIDL current through resistor R11′, through ground, in direction 515D. can create During a third time interval ΔT ₃ ′, diode D02′ is turned on to create a third discharge path for the GIDL current through resistor R12′, through ground, in direction 516D. can In a preferred embodiment, and as shown in FIG. 5E, the first discharge path in direction 511D is active during time intervals ΔT ₁ ′, ΔT ₂ , ΔT ₃ ′, and the second discharge path 515D ) is active during time intervals ΔT ₂ ′, ΔT ₃ ′, and the third discharge path 516D is active during time interval ΔT ₃ ′. In other words, in this preferred embodiment, during the positive swing of the RF voltage, the various diodes are turned on at different times in the following order: diode stack 501D is turned on first, then diode D01' is turned on later, and finally the diode D02' is turned on. In the exemplary embodiment that follows, the conditions for this sequence to occur will be described in more detail.

5F shows a portion of an exemplary implementation of the FET stack 500A of FIG. 5A. The minimum RF voltage required at node A to turn on diode stack 501F can be calculated as:

V _A = _6Vth

Here, V _th represents the threshold voltage of each of the six diodes D1 and D6, and the voltage drop introduced by the presence of (R0) is not considered for simplicity. With an RF voltage (V _A ) at node A, the voltage (V _B ) at node B can be calculated as:

However, since there are five diodes (one horizontal and four vertical) in this discharge path, the minimum voltage required to activate the discharge path 515F, i.e. diodes DO, DI, ... D4 The minimum voltage required to turn on is 5V _th . In accordance with the above, and consistent with the representation of FIG. 5C , discharge path 511F will be activated first before discharge path 515F, where the duration of interval ΔT ₁ is greater than the duration of interval ΔT ₂ .

In view of the concepts disclosed above, one skilled in the art can, depending on the application, adjust various design parameters such as the voltage division across the body resistor ladder, the number of discharge paths and the number of diodes used in each path to counteract undesirable GIDL currents. It will be appreciated that the desired conditions (time and RF amplitude during positive and negative swings) can be achieved for turning on the plurality of discharge paths in order to do so. This provides more design flexibility when facing difficult performance requirements.

As mentioned in the paragraphs above, each horizontal diode, and possibly the top and bottom diodes of the rail diode stack, may be coupled to the body ladder through a resistor. The presence of these resistors is for current limiting purposes. For example, as shown in FIGS. 5C and 5E , there are time intervals during the positive and negative swings of the RF signal in which two or more diode paths conduct (e.g., _two diode path, three diode paths during the interval (ΔT ₃ ), with corresponding additional current stress on the rail diode stack. The presence of potential resistors such as (R0, R0'), (R1, R1'), (R11, R12), etc. will allow one skilled in the art to limit the total amount of current depending on the specific implementations and design needs of the diode paths of this disclosure. It serves as a tool to enable

With respect to the FET switch stack 500A, embodiments in accordance with the teachings of this disclosure may also assume that only one of the diode stacks 501A and 502A is present. Examples of such embodiments are given in Figures 5g and 5h.

6 illustrates an exemplary FET switch stack 600 according to a further embodiment of the present disclosure. The working principle of the FET switch stack 600 is that instead of the resistor-diode pair (R1, D0) being connected to a node in the diode stack 601, a separate series stack of diodes (Dm+1, ..., Dw ) is similar to that described with respect to the FET switch 500A of FIG. 5, except that it is coupled to the RF port RF. Similarly, instead of a resistor-diode pair (R1', DO') connected to a node in diode stack 401, a separate series stack of diodes (D'k+1,..., D'q) coupled to ground (or bottom RF port) via Elements 601, 602, 610, 611, 612, and 613 are corresponding components of elements 501A, 502A, 510A, 511A, 512A, and 513A of FIG. 5A, respectively. All teachings previously described with respect to FIGS. 5A-5H are equally applicable to the embodiment of FIG. 6 .

FIG. 7 depicts an exemplary graph 700 in accordance with an embodiment of the present disclosure, showing the change in GIDL current versus applied RF amplitude before and after application of the teachings described in FIGS. 5A-5H and FIG. 6 . Curve 710 corresponds to the case where only one discharge path is implemented. The FET switch stack 200A of FIG. 2A is an example of this case. On the other hand, curve 720 represents the case where two current discharge paths are implemented by the addition of one resistor-diode pair coupling a node on the body resistor ladder to each node in the diode stack. The FET switch stack 500A of FIG. 5A is an example of this case. As can be seen, by adding an additional discharge path using a resistor-diode pair, the GIDL current is suppressed and relatively smoothed. The presence of these additional paths has the ability to improve the non-linear performance of the switch stack and provide a more balanced voltage distribution across the stack.

Referring to the RF switch 200A of FIG. 2A and the RF switch 500A of FIG. 5A, as mentioned above, the bias voltages (VB , VG) is created. 8 shows an RF circuit 800 representing RF switches 200A and 500A, where bias voltage generation circuit 801 is shown separate from the core of these RF switches. Throughout this specification, the term “body current management” refers to a mechanism for responding to undesirable GIDL currents. As an example, referring to FIG. 2A , the combination of diode stacks 201 and 202 provides this mechanism. As a further example, with reference to FIG. 5A , this mechanism includes a resistor-diode pair (R1, DO), a resistor (R0) and diode stack 501A, a resistor-diode pair (R1', DO'), a resistor (R0'). ) and the diode stack 511A. As shown in RF circuit 800, device 802 is an RF switch that receives bias voltages VB and VG from bias voltage generator circuit 801 (e.g., RF switch stack 500A of FIG. 5A). ) or the RF switch stack 200A of FIG. 2A). Also shown in the RF circuit 800, the bias voltage generation circuit 801 is also a source of current Iss representing the current sourced by the bias voltage generation circuit 801 due to the undesirable GIDL current.

Referring further to the RF switches 200A and 500A of FIGS. 2A and 5A , as mentioned earlier, the higher the negative bias voltage (VB) during the off state of the RF switch, the greater the overall linearity of such a switch. Performance gets better. However, this entails the cost of a more complex design for the bias voltage generator circuit 801 as shown generally in FIG. 8, taking up more space and consuming more power. On the other hand, implementing a more compact design of the bias voltage generation circuit 801 may undesirably degrade the non-linear performance and degrade the power handling capability of the RF switch.

An exemplary value for the bias voltages (VB, VG) is -3V when the RF switch stack is in an off state. According to some embodiments of the present disclosure, RF switches may be envisioned in which a lower negative bias voltage (VB) may be provided to the RF switch stack during the off state, for example -2V. Body current management in these embodiments is such that, at least when applying higher RF signal amplitudes, the body bias voltages of the transistors in the FET switch stack are provided by the RF signal, through the bias voltage generation circuit 801 (e.g. For example, it may be implemented to be charge pumped to negative voltages higher than -2V (eg, -3V). As a result, a more compact bias voltage generation circuit 801 with low DC power consumption can be implemented without compromising the nonlinearity performance and power handling capability of the RF switch stack. That is, implementing the diode-based body current management methods disclosed so far as part of an RF switch stack design allows the use of smaller, less complex, and less expensive bias voltage generation circuitry without compromising the overall linearity performance of the RF switch stack. .

Switch stacks in the previously known off state may require the same body and gate bias voltage (ie, VB = VG). There are several reasons for this configuration. First, it is generally easier to design for only one negative supply voltage than to design for more than that. Second, choosing a higher negative value for the bias voltage (VG) puts the FET in a deeper off state, resulting in improved power handling. Finally, a higher negative bias voltage (VB) improves linearity. Contrary to this common technique, one of the advantages of the teachings disclosed herein is to incorporate body current methods as disclosed in the design of switch stacks, thereby providing a negative bias voltage without any impact on power handling requirements. That is, demand is reduced (relaxed). Also, as mentioned earlier, these switch stacks benefit from better linearity performance when a higher negative body bias voltage is applied. This is because, with the teachings of this disclosure, the body bias voltages of the transistors in the FET switch stack are charge pumped by the RF signal to higher negative voltages than provided by the bias voltage generation circuitry. This becomes possible without the need to design for bias voltages with . Those skilled in the art will appreciate that the approach according to the present disclosure is counterintuitive because it requires separate and different handling of the gate bias voltage and body bias voltage in the off state of the FET switch stack, thus adding control logic effort. On the other hand, the inventors have discovered that this counterintuitive approach yields the advantages and benefits outlined above.

In view of the foregoing, and with further reference to FIGS. 2A and 5A , in accordance with the teachings of this disclosure, the following embodiments may be provided:

● Bias voltages (VB, VG) are not the same

● The body bias voltage (VB) is a negative voltage lower than the gate bias voltage (VG) and

● The body bias voltage (VB) is a negative voltage lower than the gate bias voltage (VG) by at least 1V, and

● Body bias voltage (VB) is adjustable and

● The body bias voltage (VB) is adjusted according to the desired overall nonlinear performance and/or power handling requirements of the FET switch stack.

The body bias voltage (VB) is the number of diodes in the diode stacks 201 and 202 of FIG. 2A or the diode stacks 501A and 502A in FIG. 5A and/or the number of such diode stacks within each of the RF switch stacks. Adjusted according to location.

9 illustrates a bias voltage generation circuit 900 according to an embodiment of the present disclosure. Bias voltage generation circuit 900 is an exemplary implementation of bias voltage generation circuit 801 of FIG. ) and an oscillator 904. The multi-stage charge pump switch block 901 includes charge pump switch blocks SW1, SW2, and SW3. The LDO 902 includes an operational transconductance amplifier (OTA) 905 connected to a transistor TO. In operating states, different negative voltage levels (V_NEG1, V_NEG2, VSS) are generated at the outputs of the charge pump switches (SW1, SW2, SW3) respectively in descending order (i.e., from lower to higher notes). . That is, V_NEG1 is the lowest negative bias voltage generated by this circuit, and VSS is the largest negative bias voltage.

Also, as shown in FIG. 9 , the negative voltage VSS is fed back to the first input of the OTA 905 through the upper end of the resistor divider 903 . The lower end of resistor divider 903 receives a reference voltage VBG, which can be generated, for example as a bandgap reference voltage circuit (not shown). Based on the difference between the voltage received at the first input and the reference voltage (eg, ground) at the second input, the OTA 905 generates a signal at the output to control the conduction of the transistor TO to thereby control the conduction of the charge pump. The voltage (V_LDO) applied to the input of the switch block 901 is adjusted. Oscillator 904 includes a variable rate clock that serves to regulate the output current supply of bias voltage generator circuit 900 .

Referring to FIGS. 2A, 5A and 8-9, according to an embodiment of the present disclosure, any voltage among the output bias voltages V_NEG1 and V_NEG2 may be used as the body bias voltage VB, and a negative voltage (VSS) may be used as the gate bias voltage (VG) for any of the circuits shown in FIGS. 2A, 5A, 5G, 5H, and 6 prior to this application. In the following, further emphasis is placed on the advantages of the disclosed methods of setting the body bias voltage to lower negative voltage values while implementing the body current management technique previously shown in FIGS. 2A, 5A, 5G, 5H and 6. Some exemplary graphs will be presented to illustrate this.

Referring further to FIGS. 2A , 5A and 8-9 , FIG. 10 is graphs 1000 including two sets of curves 1001 and 1002 representing performance results obtained with and without implementing body current management, respectively. ) shows. Curves 1001 represent the dependence of power processing FET switches on body bias voltage (VB) that do not implement body current management. An example of this case is the FET switch stack 100 of FIG. 1A. As can be seen, as the body current bias voltage increases to lower negative values during the OFF state of the FET switch stack, performance degrades and the FET switch exhibits lower power handling capability. Throughout this specification, the term "power handling capability" is used to turn off using a given configuration (e.g., series or shunt) and RF port impedance termination (e.g., open or 50 ohms) without causing switch failure. It means the maximum power applied to the switch stack in the state. In contrast, curves 1002 represent the case where body current management according to the teachings of this disclosure is implemented. Exemplary FET switch stacks for this case are the FET switch stacks 200A and 500A of FIGS. 2A and 5A, respectively. As can be seen, the power handling capability has improved after implementing body current management, in particular in this case the dependence of the power handling capability of the RF switch stack on the applied bias voltage (VB) has been eliminated (i.e., the 1002 curves relatively flat), in which case it was found that FET switch stacks can benefit from the counterintuitive teachings of this disclosure without sacrificing power handling requirements. Each of the curves 1001 and 1002 includes two separate plots each corresponding to a different switch stack showing component-to-component variation.

FIG. 11 is a graph containing four sets of curves 1101, 1102, 1103, 1104, where VB is less negative than VSS, and performance results obtained without and with body current management implemented. shows 1100. Curve 1101 shows an exemplary change in body current (Iss) FET switch versus RF peak voltage for no implementation of current management, where the bias voltage VB is a negative voltage lower than VSS at the bias generation rail (i.e., VNEG1). connected to Curve 1102 shows an example change in body current (Iss) FET switches versus RF peak voltage when body current management is not implemented and the bias voltage (VB) is connected to VSS. Curve 1103 represents the case where body current management according to the teachings of this disclosure is implemented and the bias voltage VB is coupled to a negative voltage lower than Vss at the bias generation rail (ie, VNEG1). Curve 1104 represents the case where body current management according to the teachings of this disclosure is implemented and the bias voltage (VB) is coupled to Vss. As can be seen, for curve 1103 the maximum Iss that the bias generator has to deal with is reduced compared to curves 1101, 1102 and 1104, thus reducing the complexity and power consumption requirements of the bias generator.

12 shows an exemplary RF circuit 1200 according to one embodiment of the present disclosure. The principle of operation of the RF circuit 1200 is similar to that described for the RF circuit 800 in FIG. 8 except for the addition of a control circuit 1303. In operating states, when the RF switch 1202 is in the OFF state, according to the desired linearity performance of the RF switch 1202, the control circuit 1203 issues a control signal CTRL so that the body bias voltage VB is Indicates the level that should be provided to the RF switch 1202 by the bias voltage generation circuit 1201.

As already mentioned above, the bias voltage VB can be adjusted while the RF switch is off. In particular, as the RF power decreases, tuning (VB) to a larger negative voltage towards the optimal body voltage target voltage when the diodes are not conducting helps to maintain linearity in the off mode and good small signal isolation. can be useful In this back-off state, the body current to manage is usually not large. In this case, (VB) can be adjusted by variable or discrete steps. This tunability can be controlled, for example, by an analog control, a digital control register, or the decoded output of an RF detector that adjusts the voltage as a function of RF power applied to the switch in off mode.

As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulating gate whose voltage determines the conductivity of the transistor, and includes an insulating gate having a metal or metal analog, insulator, and/or semiconductor structure. includes The term "metal" or "metal analogue" includes at least one electrically conductive material (such as aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductor), and "insulator" includes ( at least one insulating material (such as silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

As used herein, the term “radio frequency” (RF) refers to oscillation rates ranging from about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. The RF frequency can be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

With respect to the drawings referenced herein, the dimensions of the various elements are not to scale; Some dimensions have been greatly exaggerated vertically and/or horizontally for clarity or emphasis. Also, references to orientation and direction (eg, "top", "bottom", "above", "below", "side", "vertical", "horizontal", etc.) are based on the illustrative drawings, and must be It is not an absolute orientation or direction.

Various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of appropriate component values is a matter of design choice. Various embodiments of the present invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or hybrid or discrete circuitry. Integrated circuit embodiments include, but are not limited to, standard bulk silicon, high resistance bulk CMOS, silicon-on-insulator (SOI) and silicon-on-sapphire (SOS). It may be fabricated using any suitable substrate and process. Unless otherwise noted above, embodiments of the present invention may be implemented with other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the present invention are particularly useful when fabricated using SOI or SOS based processes or processes with similar properties. Fabrication in CMOS using the SOI or SOS process provides low-power circuitry, the ability to withstand high-power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). make it possible Monolithic IC implementations are particularly useful because, usually by careful design, parasitic capacitance can be kept low (or at least kept uniform across all units so that it can be compensated for).

The voltage level may be adjusted and/or the voltage and/or logic signal polarity may be inverted according to a particular specification and/or implementation technology (e.g., NMOS, PMOS or CMOS, enhancement mode or depletion mode transistor device). Component voltage, current and power handling capabilities can be adjusted as needed, for example by sizing the device, "stacking" components (particularly FETs) in series to withstand higher voltages and/or "stacking" higher currents. can be coordinated by using multiple components in parallel to process Additional circuit components may be added to enhance the functionality of the disclosed circuitry and/or provide additional functionality without significantly altering the functionality of the disclosed circuitry.

Circuits and devices according to the present invention may be used alone or in combination with other components, circuits and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs) that may be included in IC packages and/or modules to facilitate processing, manufacturing, and/or improved performance. In particular, IC embodiments of the present invention are often used in modules where one or more of these ICs are combined with other circuit blocks (eg filters, amplifiers, passive components and possibly additional ICs) into a single package. The ICs and/or modules are then typically combined with other components, often on printed circuit boards, to form end products such as cellular phones, laptop computers or electronic tablets, or in a wide variety of products such as vehicles, test equipment, medical devices, and the like. form a higher level module that can be used in Through various configurations of modules and assemblies, these ICs typically enable communication modes, often wireless communication.

A number of embodiments of the present disclosure have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, some of the steps described above may be order independent and may therefore be performed in an order different from that described. Also, some of the steps described above may be optional. The various activities described in relation to the methods identified above may be executed in an iterative, serial and/or parallel fashion.

It is to be understood that the foregoing description is illustrative rather than limiting of the scope of the present invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the present invention includes any and all possible combinations of one or more of the processes, machines, manufactures or compositions of matter set forth in the claims below. (Bracketed labels for claim elements are for ease of reference to those elements and do not by themselves indicate any particular required order or enumeration of the elements; furthermore, such labels are not to be considered as starting a conflicting labeling sequence and are not intended for additional elements. Note that it may be reused in dependent claims by reference.)

Claims (80)

As a field effect transistor (FET) switch stack,
series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal;
A body resistive ladder coupled to the first terminal, wherein the body resistive ladder includes a plurality of body resistors connected in series, each body resistor having a corresponding one of the adjacent ones of the FETs connected in series. coupled to both ends of the body terminals -;
a first diode stack composed of one or more diodes and having a first cathode terminal connected to the first terminal and a first anode terminal connected to a body terminal of a first FET among the series connected FETs;
Including, FET switch stack. According to claim 1,
In the off state of the FET switch stack, the first diode stack is, in the conduction state during a negative RF swing of the RF signal, through the first terminal for gate-induced drain leakage current. create a discharge path; also
FET switch stack in a non-conductive state during a positive RF swing of the RF signal. According to claim 1,
The FET switch stack, wherein the series-connected FETs are four or more series-connected FETs. According to claim 1,
and a second diode stack having a second cathode terminal connected to the second terminal and a second anode terminal connected to a body terminal of a second one of the series connected FETs. According to claim 4,
The FET switch stack, wherein the series-connected FETs are four or more series-connected FETs. According to claim 4,
in the off state of the FET switch stack, the second diode stack creates an additional discharge path through the second terminal for the gate induced drain leakage current, in the conduction state during a positive RF swing of the input RF signal; , also
FET switch stack in a non-conducting state during a negative RF swing of the input RF signal. According to claim 6,
The FET switch stack is configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and receive a second bias voltage at a body bias terminal of the FET switch stack, wherein the gate bias terminal is configured to receive the second bias voltage through a resistor. 2 coupled to the gate of the bottom FET closest to the terminal and wherein the body bias terminal is coupled to the body of the bottom FET. According to claim 7,
In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages. According to claim 1,
and the body resistive ladder includes a first capacitor closest to the first terminal and a second capacitor closest to the second terminal. According to claim 1,
wherein the second terminal is connected to a reference voltage or ground. According to claim 6,
wherein the second terminal is configured as an output RF port. According to claim 11,
the FET switch stack is configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a body bias terminal, the gate bias terminal being coupled to a gate of an intermediate FET of the series connected FETs through a resistor; and wherein the body bias terminal is coupled to the body of the intermediate FET. According to claim 12,
In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages. As a field effect transistor (FET) switch stack,
series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal;
a drain-source resistive ladder coupled to the first terminal, the drain-source resistive ladder comprising a plurality of drain-source resistors connected in series, each drain-source resistor having a corresponding adjacent FET of the series-connected FETs; coupled across the drain-source terminals of -;
a first diode stack comprising one or more diodes and having a first anode terminal connected to the first terminal and a first cathode terminal connected to a source terminal of a first one of the series connected FETs;
Including, FET switch stack. 15. The method of claim 14,
in the off state of the FET switch stack, the first diode stack creates a source path through the first terminal for a gate induced drain leakage current, in a conduction state during a positive RF swing of the input RF signal; also
FET switch stack in a non-conducting state during a negative RF swing of the input RF signal. 15. The method of claim 14,
The FET switch stack, wherein the series-connected FETs are four or more series-connected FETs. 15. The method of claim 14,
and a second diode stack having a second anode terminal connected to the second terminal and a second cathode terminal connected to a drain terminal of a second one of the series connected FETs. 18. The method of claim 17,
The FET switch stack, wherein the series-connected FETs are four or more series-connected FETs. 18. The method of claim 17,
in the off state of the FET switch stack, the second diode stack creates an additional source path through the second terminal for the gate induced drain leakage current, in the conduction state during a negative RF swing of the input RF signal; , also
FET switch stack in a non-conductive state during a positive RF swing of the input RF signal. According to claim 19,
The FET switch stack is configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a drain bias terminal, the gate bias terminal being connected through a resistor to the gate of the bottom FET closest to the second terminal. coupled, wherein the drain bias terminal is coupled to the drain terminal of the bottom FET. 21. The method of claim 20,
In an off state of the FET switch stack, the first bias voltage is 0 volts, and the second bias voltage is a positive bias voltage. 15. The method of claim 14,
wherein the drain-to-source resistor ladder includes a first capacitor closest to the first terminal and a second capacitor closest to the second terminal. According to claim 21,
wherein the second terminal is connected to a reference voltage or ground. According to claim 19,
wherein the second terminal is configured as an output RF port. 25. The method of claim 24,
The FET switch stack is configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a drain bias terminal, the gate bias terminal being coupled to a gate of an intermediate FET of the series connected FETs through a resistor. and wherein the drain bias terminal is coupled to the drain terminal of the intermediate FET. 26. The method of claim 25,
In an off state of the FET switch stack, the first bias voltage is 0 volts, and the second bias voltage is a positive bias voltage. A method of driving bias voltages of a FET switch stack toward a voltage distribution across the FET switch stack, comprising:
generating radio frequency (RF) voltage sources across the FET switch stack from an RF signal; and
creating a current discharge path to form the voltage distribution across the FET switch stack;
Including, method. 28. The method of claim 27,
wherein generating the current discharge path is performed using a diode stack coupled to the FET switch stack. An RF module comprising the FET switch stack of claim 1 . A communications device comprising the FET switch stack of claim 1 . As a field effect transistor (FET) switch stack,
series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal;
a body resistor ladder coupled to the first terminal, the body resistor ladder including a plurality of body resistor elements coupled in series, each body resistor element being coupled across body terminals of corresponding adjacent FETs of the series coupled FETs; ringed -; and
a body current management circuit coupled to the body resistor ladder;
here,
the FET switch stack is configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and receive a second bias voltage at a body bias terminal of the FET switch stack;
In the OFF state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages;
In the off state, the second bias voltage is a negative voltage lower than the first bias voltage, and
wherein the body current management circuit is configured to provide one or more current discharge paths for gate induced drain leakage current. 32. The method of claim 31,
the body current management circuit comprises a first diode arrangement;
The first diode arrangement includes a diode stack comprising two or more diodes, the diode stack coupled between the body resistor ladder and the first terminal, the diode stack in the off state of the FET switch stack. FET switch stack configured to provide a first current discharge path of the one or more current discharge paths while 33. The method of claim 32,
wherein the diode stack is in a conducting state and is configured to provide the first current discharge path during a first time portion of a positive or negative swing of the RF signal in the off state of the FET switch stack. 34. The method of claim 33,
The first diode arrangement further includes one or more additional diodes coupled to the body resistor ladder, wherein the one or more additional diodes conduct at least a second current of the one or more current discharge paths during the off state of the FET switch stack. A stack of FET switches configured to provide a discharge path. 35. The method of claim 34,
wherein the one or more additional diodes are in a conducting state during at least a second time portion of the positive or negative swing of the RF signal in the off state of the FET switch stack and are configured to provide the at least second current discharge path. FET switch stack. 36. The method of claim 35,
wherein the at least second time portion is within the first time portion. 35. The method of claim 34,
At least one of the diode stack and the one or more additional diodes is coupled to the body resistor ladder through at least one coupling resistor, the coupling resistor coupled to the first current discharge path and the at least second current discharge path. A stack of FET switches, which when provided in combination with paths act as current limiting resistors during some of the positive or negative swings of the RF signal. 38. The method of claim 37,
wherein the diode stack and the one or more additional diodes are coupled to the body resistor ladder through respective coupling resistors. 35. The method of claim 34,
wherein the diode stack and the one or more additional diodes are coupled to the body resistor ladder at different tapping points of the body resistor ladder. 35. The method of claim 34,
The diode stack and the one or more additional diodes i) start providing the first current discharge path before starting providing the at least second current discharge path, and ii) in the off state of the FET switch stack, the RF and stop providing the first current discharge path after stopping providing the at least second current discharge path during the positive or negative swing of a signal. 35. The method of claim 34,
wherein the one or more additional diodes are configured to provide the at least second current discharge path in combination with a subset of diodes of the diode stack, whereby the at least second current discharge path partially overlaps the first GIDL discharge path. , FET switch stack. 35. The method of claim 34,
wherein the one or more additional diodes are configured to provide the at least second current discharge path without combining with a subset of diodes of the diode stack, whereby the at least second current discharge path is separated from the first current discharge path. , FET switch stack. 32. The method of claim 31,
further comprising a second diode array having a corresponding diode stack;
wherein the diode stack of the first diode array is in a conducting state during a first time portion of the positive swing of the RF signal in the off state of the FET switch stack and is configured to provide the first current discharge path; and
wherein the diode stack of the second diode arrangement is in a conducting state during a first time portion of the negative swing of the RF signal in the off state of the FET switch stack and is configured to provide the first current discharge path. switch stack. 34. The method of claim 33,
The first diode array,
and one or more additional diodes coupled to the body resistor ladder, the one or more additional diodes generating at least a second current during a second time portion of the positive swing of the RF signal in the off state of the FET switch stack. configured to provide a discharge path; also
The second diode array,
further comprising one or more additional diodes coupled to the body resistor ladder, the one or more additional diodes configured to transmit the at least second diode during a second time portion of the negative swing of the RF signal in the off state of the FET switch stack. A stack of FET switches configured to provide a current discharge path. 32. The method of claim 31,
In the off state, the second bias voltage is a negative voltage lower than a set body bias voltage corresponding to a set nonlinearity performance and power handling capability of the RF switch stack. 46. The method of claim 45,
The FET switch stack, wherein bias voltages of body terminals of each FET are pulled toward the set body bias voltage. 46. The method of claim 45,
The second bias voltage is a negative voltage lower than the set body bias voltage by at least 1V, the FET switch stack. 46. The method of claim 45,
The first bias voltage and the set body bias voltage are the same, FET switch stack. 46. The method of claim 45,
Wherein the second bias voltage is adjustable in the off state of the FET switch stack. 50. The method of claim 49,
wherein the second bias voltage is adjustable when the body current management circuitry is not providing the one or more current discharge paths. 38. The method of claim 37,
wherein the coupling resistor acts as a current limiting resistor during part of the positive or negative swing of the RF signal when the first current discharge path and the at least second current discharge path are provided through the same diodes. stack. As a circuit arrangement,
the FET switch stack of claim 31; and
a bias voltage generation circuit configured to generate a first bias voltage and a second bias voltage during at least an off state of the FET switch stack;
A circuit arrangement comprising a. 53. The method of claim 52,
wherein the bias voltage generation circuit comprises a multi-stage charge pump switch block configured to generate at least two different negative voltage levels. 54. The method of claim 53,
a first negative voltage level of the two or more different negative voltage levels is the first bias voltage and a second negative voltage level of the two or more different negative voltage levels is the second bias voltage; circuit arrangement. A series connected FET comprising one end coupled to a first terminal and the other end coupled to a second terminal, wherein the first terminal is configured to receive an input radio frequency (RF) signal. A method of biasing a field-effect transistor (FET) switch stack in an off state, comprising:
applying a negative gate bias voltage to gate terminals of the series-connected FETs;
applying a negative body bias voltage to body terminals of the series-connected FETs, wherein the body bias voltage is a negative voltage lower than the gate bias voltage;
in the off state of the RF FET switch stack, applying an RF signal across the RF FET switch stack; and
discharging a gate induced drain leakage current through one or more current discharge paths while applying the RF signal, the discharge causing voltages at body terminals of the series connected FETs at negative voltages higher than the body bias; pull down -;
Including, method. 56. The method of claim 55,
wherein the one or more current discharge paths are a plurality of current discharge paths. 57. The method of claim 56,
A first current discharge path of the plurality of current discharge paths is generated through a diode stack coupled with the RF FET stack switch, and a second current discharge path of the plurality of current discharge paths is generated through one or more additional diodes. generated, how. 56. The method of claim 55,
adjusting the negative body bias voltage to provide a different negative bias to the body terminal. As a field effect transistor (FET) switch stack,
series connected FETs having one end coupled to a first terminal and the other end coupled to a second terminal, wherein the first terminal is configured to receive a radio frequency (RF) signal;
a body resistor ladder coupled to the first terminal, the body resistor ladder including a plurality of body resistor elements coupled in series, each body resistor element being coupled across body terminals of corresponding adjacent FETs of the series coupled FETs; ringed -; and
A first diode element array; includes,
The first diode element array,
i) a diode element stack comprising two or more diode elements, the diode element stack coupled between the body resistor ladder and the first terminal; and
ii) one or more additional diode elements coupled to the body resistor ladder
Including, FET switch stack. The method of claim 59,
wherein the diode device stack is configured to provide a first gate induced drain leakage (GIDL) current discharge path during an off state of the FET switch stack. 61. The method of claim 60,
wherein the one or more additional diode elements are configured to provide at least a second GIDL current discharge path during the off state of the FET switch stack. 62. The method of claim 61,
The diode element stack and the one or more additional diode elements are in a conducting state during a portion of the positive or negative swing of the RF signal in the off state of the FET switch stack and the first GIDL current discharge path and the at least one 2 FET switch stack configured to provide in combination GIDL current discharge paths. 62. The method of claim 61,
wherein at least one of the two or more diode elements of the diode element stack is coupled to the body resistor ladder through at least one coupling resistor. 64. The method of claim 63,
wherein the coupling resistor serves as a current limiting resistor during the portion of the positive or negative swing of the RF signal when the first GIDL current discharge path and the at least second GIDL current discharge path are provided in combination. FET switch stack. 65. The method of claim 64,
wherein both the diode element stack and the one or more additional diode elements are coupled to the body resistor ladder through respective coupling resistors. The method of claim 59,
wherein the diode element stack and the one or more additional diode elements are coupled to the body resistor ladder at different tapping points of the body resistor ladder. 65. The method of claim 64,
wherein the diode element stack, the one or more additional diode elements and the at least one coupling resistor i) start providing the first GIDL current discharge path before starting providing the at least second GIDL current discharge path; , ii) stop providing the first GIDL current discharge path after stopping providing the at least second GIDL current discharge path during the positive or negative swing of the RF signal in the off state of the FET switch stack; consisting of a stack of FET switches. 65. The method of claim 64,
The one or more additional diode elements are configured to provide the at least second GIDL current discharge path in combination with a subset of diode elements of the diode element stack, whereby the second GIDL discharge path is different from the first GIDL discharge path. Some overlapping, FET switch stacks. 65. The method of claim 64,
The one or more additional diode elements are configured to provide the at least second GIDL discharge path without combining with a subset of diode elements of the diode element stack, whereby the second GIDL discharge path is different from the first GIDL discharge path. A separate, FET switch stack. 65. The method of claim 64,
and a second diode element arrangement having a corresponding diode element stack and one or more additional diode elements, wherein the diode element stack of the first diode element arrangement and the one or more additional diode elements are in the off state of the FET switch stack. and to provide in combination the first GIDL current discharge path and the at least second GIDL current discharge path during a portion of the positive swing of the RF signal at and
The diode element stack of the second diode element array and the one or more additional diode elements may be connected to the first GIDL current discharge path and the at least a first GIDL current discharge path during a portion of the negative swing of the RF signal in the off state of the FET switch stack. 2 FET switch stack configured to provide in combination GIDL current discharge paths. The method of claim 59,
wherein the FET switch stack is configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and a second bias voltage at a body bias terminal of the FET switch stack. 72. The method of claim 71,
In an off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages. The method of claim 59,
wherein the second terminal is configured to be coupled to a reference voltage or ground. The method of claim 59,
wherein the second terminal is configured to be coupled to an RF signal. The method of claim 59,
and wherein at least one of the diode element stacks and the one or more diode elements comprises diode-connected transistors or diodes. The method of claim 59,
and a first capacitor coupling the series connected FETs to the first terminal and a second capacitor coupling the series connected FETs to the second terminal. A method of controlling gate-induced drain leakage current in an off state of a radio frequency (RF) switch stack, the RF switch stack comprising i) series connected FETs configured to receive an RF signal and ii) body terminals of the series connected FETs. a body resistor ladder coupled to the method comprising:
applying the RF signal to the RF switch stack;
generating a first current discharge path for the gate induced drain leakage current through the body resistor ladder during a first time interval in the off state of the RF switch stack; and
generating a second current discharge path for the gate induced drain leakage current through the body resistor ladder during a second time interval in the off state of the RF switch stack;
The second time interval partially overlaps in time with the first time interval during the first overlapping time interval in the off state of the RF switch in which both the first current discharge path and the second current discharge path are generated, method. 78. The method of claim 77,
The first current discharge path is generated through a diode stack coupled to the RF switch stack and the body resistor ladder, and the second current discharge path connects one or more diodes added to the diode stack to the RF switch stack and the body resistor ladder. created by coupling to a body resistor ladder. 79. The method of claim 78,
wherein the diode stack and the one or more diodes are coupled to the body resistor ladder at different tapping points of the body resistor ladder. 78. The method of claim 77,
generating a third current discharge path for the gate induced drain leakage current through the body resistor ladder during a third time interval in the off state of the RF switch stack;
The third time interval is the first time interval and the second overlapping time interval in the off state of the RF switch in which the first current discharge path, the second current discharge path, and the third current discharge path are generated. partially overlapping in time with the second time interval.

Images