KR20230032816A - Zigzag Wired Memory Module - Google Patents

Abstract

A memory module according to one aspect of the technical idea of the present disclosure includes a printed circuit board including multi-layers on which a wiring structure is formed, and a length in a first direction is longer than a length in a second direction perpendicular to the first direction; and printing On the circuit board, a plurality of memory chips are arranged in first and second columns respectively extending in a first direction, each of which includes a plurality of solder balls continuously arranged in the first direction, and the wiring structure includes a first A plurality of memory chips arranged in the first column and the second column are alternately connected in a zigzag pattern.

Description

Zigzag Wired Memory Module {Zigzag Wired Memory Module}

The technical idea of the present disclosure relates to a semiconductor module such as a memory module employed in a data processing system, and more particularly, to a memory module wired in a zigzag pattern.

Semiconductor memory required for electronic products such as personal computers (PCs), server computers, and workstations, or data processing systems such as communication systems, is in the form of a memory module. It is configured and connected to the board of the system. The memory module may include a dual in-line memory module (DIMM) in which a plurality of memory packages are mounted on a board.

Recently, as electronic products or data processing systems have high capacity, high integration, high performance, and miniaturization, memory modules are also required to have high capacity, high integration, high performance, and miniaturization. In particular, as the operating speed of the memory increases day by day, the topology of signal lines constituting the memory module has been changed to be suitable for high-speed operation. Recently, a fly-by type connection in which channels are configured in a daisy-chain type and connected to each loading through a short-stub has been developed. However, as the routing of numerous signals included in the memory module becomes complicated, it becomes difficult to control the operation speed of the memory devices. Therefore, a memory module having a simpler routing structure is required.

An object to be solved by the technical concept of the present disclosure is to provide a memory module wired in a zigzag pattern.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above object, a memory module according to one aspect of the present disclosure includes a multi-layer printed circuit board having a length in a first direction longer than a length in a second direction perpendicular to the first direction. , A first memory chip mounted on a printed circuit board and having a length in the first direction longer than a length in the second direction, and disposed spaced apart from the first memory chip in the second direction, A second memory chip disposed to be longer than the length in the second direction, and a third memory chip disposed apart from the first memory chip in the first direction and having a length in the first direction longer than a length in the second direction. Signals are transmitted to a memory chip, a fourth memory chip disposed apart from the second memory chip in a first direction, and having a length in the first direction longer than a length in the second direction, and each of the first to fourth memory chips. and a signal line for transmitting, wherein the signal line is formed in a printed circuit board and connects between the first memory chip and the second memory chip and connects between the third memory chip and the fourth memory chip; and It is formed in the printed circuit board and includes a second wire connecting the second memory chip and the third memory chip.

In order to achieve the above object, a memory module according to one aspect of the present disclosure includes multi-layers in which a wiring structure is formed, and a length in a first direction is greater than a length in a second direction perpendicular to the first direction. A long printed circuit board and a plurality of memory chips including a plurality of solder balls arranged in first and second rows extending in a first direction, respectively, on the printed circuit board, each of which is continuously arranged in the first direction In the wiring structure, the plurality of memory chips arranged in the first column and the second column are alternately connected in a zigzag pattern.

In order to achieve the above object, a memory system according to an aspect of the present disclosure provides a printed circuit board having a length in a first direction longer than a length in a second direction perpendicular to the first direction, and on a printed circuit board. A memory module including a plurality of memory chips arranged in first and second columns extending in a first direction, each having a length in the first direction longer than a length in the second direction, and transmitting a signal to the memory module The printed circuit board is formed on a layer different from a layer on which a first wiring and a layer on which the first wiring is formed connect the plurality of memory chips arranged in the first and second columns in a straight line extending in a third direction. a second wire connecting the plurality of memory chips arranged in the first column and the second column in a straight line extending in a fourth direction, which is different from the third direction, and vias electrically connecting the first wire and the second wire; includes

The memory module according to the technical concept of the present disclosure can reduce a space required for routing by being zigzagly wired. Accordingly, it is possible to provide a memory module with improved space efficiency and improved cross-talk.

Since the memory module according to the technical idea of the present disclosure is wired in a zigzag pattern using different layers, the number of layers required to manufacture the memory module can be reduced, and accordingly, the cost required to manufacture the memory module can be saved.

Effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure belong from the following description. can be clearly derived and understood by those who have That is, unintended effects according to the implementation of the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a memory system according to an exemplary embodiment.
2 is a plan view of a memory module according to an exemplary embodiment.
3 is a diagram for explaining arrangement of solder balls according to an exemplary embodiment.
4 is a diagram for explaining a wiring structure of a memory module according to an exemplary embodiment.
5 is a diagram for explaining a wiring structure of a memory module according to an exemplary embodiment.
6 is a plan view of a memory module according to an exemplary embodiment.
7 is a plan view of a memory module according to an exemplary embodiment.
8A and 8B are plan views of a memory module according to an exemplary embodiment.
9 is a plan view of a memory module according to an exemplary embodiment.
10 is a plan view of a memory module according to an exemplary embodiment.
11 is a block diagram illustrating an example of applying a memory module according to an exemplary embodiment to a computing system.
12 is a block diagram illustrating an example of applying a memory module according to an exemplary embodiment to a mobile system.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following plan views, a horizontal direction is defined as a first direction (X), a vertical direction is defined as a second direction (Y), and a direction substantially perpendicular to the plan view is defined as a third direction (Z). Accordingly, the second direction (Y) may mean a direction perpendicular to the first direction (X). A direction indicated by an arrow in the drawing and a direction opposite to it will be described as the same direction. The definition of the foregoing direction is the same in all drawings hereinafter. In the drawings of this specification, only a part may be shown for convenience of illustration. When describing with reference to the drawings, the same or corresponding components are assigned the same reference numerals, and overlapping descriptions thereof will be omitted.

1 is a block diagram illustrating a memory system according to an exemplary embodiment.

Referring to FIG. 1 , a memory system 1 may include a memory controller 2 and a memory module 3 .

The memory controller 2 may transmit a command/address (C/A) signal (C/A, hereinafter referred to as 'C/A signal') to the memory module 3 and control the memory module 3. can do. The memory controller 2 may exchange data with the memory module 3 according to the C/A signal C/A. For example, the memory controller 2 may exchange data input/output signals (DQ1 to DQ3, hereinafter referred to as 'DQ signals') with the memory module 3.

The memory controller 2 may control the memory module 3 according to a request of a processor supporting various applications such as a server application, a personal computer (PC) application, and a mobile application. The memory controller 2 may be included in a host including a processor and may control the memory module 3 according to a request of the processor.

Transmission paths for the C/A signal (C/A) and the DQ signals (DQ1 to DQ3) may be provided between the memory controller 2 and the memory module 3, respectively. For example, the first to third memory chips 4 to 6 may share transmission paths for C/A signals (C/A), but do not share transmission paths for DQ signals (DQ1 to DQ3). may not be

The memory module 3 may include first to third memory chips 4 to 6 . The memory module 3 may represent any device comprising several memory chips, for example the memory module 3 may be a memory package.

The first to third memory chips 4 to 6 receive the C/A signal C/A from the memory controller 2 and exchange DQ signals DQ1 to DQ3 with the memory controller 2. can For example, the first memory chip 4 may exchange the first DQ signal DQ1 with the memory module 3 in response to the C/A signal C/A. Similarly, the second and third memory chips 5 and 6 may exchange the second DQ signal DQ2 and the third DQ signal DG3 with the memory module 3, respectively. In this embodiment, only the first to third memory chips 4 to 6 are shown, but the number of memory chips of the memory module 3 is not limited to those shown. In another embodiment, the number of memory chips included in the memory module 3 may be 4 or more.

Wiring for transmitting the C/A signal (C/A) to the first to third memory chips 4 to 6 may be formed inside the memory module 3 . The wiring for transmitting the C/A signal (C/A) to the first to third memory chips 4 to 6 may be implemented by arranging the first wiring and the second wiring having a straight line in a zigzag pattern. The first to third memory chips 4 to 6 may receive the C/A signal C/A from the memory controller 2 through the first wiring and the second wiring arranged in a zigzag pattern. Hereinafter, the wiring structure of the first to third memory chips 4 to 6 will be described in detail.

2 is a plan view of a memory module according to example embodiments. In detail, it is a diagram showing an embodiment of implementing the memory module 3 of FIG. 1 . Hereinafter, description will be made with reference to FIG. 1, and redundant description will be omitted.

Referring to FIG. 2 , the memory module 10 may include a printed circuit board (PCB) 11 and a plurality of memory chips 12A to 12F.

The memory module 10 includes a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small-outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully-buffered DIMM (FBDIMM), and an RBDIMM ( Rank-Buffered DIMMs), mini-DIMMs, micro-DIMMs, Registered DIMMs (RDIMMs), Load-Reduced DIMMs (LRDIMMs), Centaur DIMMs (CDIMMs), Differential DIMMs (DDIMMs), or Compute Express Link DIMMs (CXL DIMMs). can be implemented

The printed circuit board 11 may refer to a thin plate on which various electrical components (eg, memory chips, buffers, resistors, capacitors, etc.) are mounted. The printed circuit board 11 may be configured such that a copper wiring pattern is formed on one side or both sides of an insulating plate made of epoxy resin or the like. The printed circuit board 11 may be a rigid printed circuit board (rigid PCB), a flexible printed circuit board (flexible PCB), or a rigid-flexible printed circuit board (rigid-flexible PCB).

The printed circuit board 11 may include at least one of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, or combinations thereof. The printed circuit board 11 may be a semiconductor-on-insulator (SOI) board. The SOI substrate may include a plurality of layers made of at least one of epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. The printed circuit board 11 may be provided based on an insulating core such as a glass fiber reinforced resin core. For example, the printed circuit board 11 may include a glass fiber resin such as FR4 (Flame Retardant 4).

A plurality of memory chips 12A to 12F may be mounted on the printed circuit board 11 . The printed circuit board 11 may have a length in the first direction (X) longer than a length in the second direction (Y), and the plurality of memory chips 12A to 12F may extend in the first direction (X). The horizontal length CW, which is the length of , may be longer than the vertical length CH, which is the length in the second direction Y. As described below with reference to FIG. 3 , each of the plurality of memory chips 12A to 12F includes solder balls electrically connecting the plurality of memory chips 12A to 12F to the printed circuit board 11 . can do. Solder balls formed in each of the plurality of memory chips 12A to 12F may be continuously arranged in the first direction (X), and may be partially discontinuously arranged in the second direction (Y). Also, the number of solder balls formed in each of the plurality of memory chips 12A to 12F arranged in the first direction X may be greater than the number arranged in the second direction Y.

The plurality of memory chips 12A to 12F may be arranged at regular intervals from each other in the first direction (X) and the second direction (Y). The plurality of memory chips 12A to 12F may be arranged in at least two columns each extending in the first direction X, and memory chips (eg, 12B, 12D, and 12F) disposed in the first column and memory chips (eg, 12B, 12D, and 12F) disposed in the second column The arranged memory chips (eg, 12A, 12C, and 12E) may be arranged side by side. That is, a plurality of memory chips (eg, 12A, 12C, and 12E) disposed in the same column may be disposed on the same axis in the first direction (X). Among the plurality of memory chips 12A to 12F, memory chips (eg, 12A and 12B) adjacent in the second direction Y may be disposed on the same axis in the second direction Y. That is, among the plurality of memory chips 12A to 12F, memory chips adjacent to each other in the second direction Y (eg, 12A and 12B) may be aligned in the second direction Y.

In this embodiment, six memory chips 12A to 12F arranged side by side in two rows on the first surface S1 of the printed circuit board 11 are shown, but are not limited thereto. According to an embodiment, the memory chips 12A to 12F may be mounted on the first surface S1 of the printed circuit board 11 and on the second surface opposite to the first surface S1.

Each of the plurality of memory chips 12A to 12F may be a semiconductor memory package. The semiconductor memory package may include at least one semiconductor memory die, and the semiconductor memory die may include a semiconductor substrate having an integrated electronic circuit cut into a chip shape. Semiconductor memory dies include dynamic random-access memory (DRAM), static random-access memory (SRAM), FLASH, magnetic random-access memory (MRAM), resistive random-access memory (ReRAM), and ferroelectric random-access memory (FeRAM). Alternatively, it may be a semiconductor memory die on which a memory integrated circuit such as a phase-change random-access memory (PcRAM) is integrated.

The printed circuit board 11 may include a first wire CA1 and a second wire CA2 . The first wiring CA1 and the second wiring CA2 are formed inside the printed circuit board 11, but are shown on the printed circuit board 11 and the plurality of memory chips 12A to 12F for convenience of description. .

As described below with reference to FIGS. 3 to 5 , the first wiring CA1 and the second wiring CA2 are solder balls of the landing pad of the printed circuit board 11 and the plurality of memory chips 12A to 12F. The plurality of memory chips 12A to 12F may be electrically connected through the . The first wire CA1 and the second wire CA2 may transmit the C/A signal received from the memory controller (2 in FIG. 1 ) to the plurality of memory chips 12A to 12F. That is, the first wiring CA1 and the second wiring CA2 are C/A signal lines for transmitting the C/A signal received from the memory controller (2 in FIG. 1) to the plurality of memory chips 12A to 12F. (CL).

The C/A signal line CL may alternately connect the plurality of memory chips 12A to 12F arranged in the first column and the second column respectively extending in the first direction X in a zigzag pattern. The C/A signal line CL may include a first wire CA1 and a second wire CA2 that are alternately and repeatedly disposed. The first wire CA1 and the second wire CA2 may each have a straight line shape extending in different directions.

For example, the first wire CA1 may be formed in a straight line extending in the first direction X, and the second wire CA2 may be formed between the first direction X and the second direction Y. It may be configured in a straight line shape extending in the direction. Accordingly, the length of the first wire CA1 may be shorter than the length of the second wire CA2, but is not limited thereto. According to an embodiment, the length of the first wire CA1 may be the same as that of the second wire CA2.

The first wiring CA1 and the second wiring CA2 may be disposed on different layers of the printed circuit board 11 and may be electrically connected to each other through the via V. The via (V) may be formed in the third direction (Z) to connect the first wire (CA1) and the second wire (CA2). According to embodiments, the first wire CA1 may be disposed in a layer closer to the plurality of memory chips 12A to 12F in the third direction Z than the second wire CA2, but is not limited thereto, and The second wire CA2 may be disposed on a layer closer to the plurality of memory chips 12A to 12F in the third direction Z than the first wire CA1.

In the memory module 10 according to an exemplary embodiment of the present disclosure, a simple wiring structure may be implemented by repeatedly arranging the first wiring CA1 and the second wiring CA2 configured in a straight line in a zigzag pattern. Accordingly, space efficiency inside the printed circuit board 11 increases, and signal characteristics can be enhanced because the signal path through which the C/A signal must pass decreases. In addition, since the number of layers inside the printed circuit board 11 used to transmit signals between the plurality of memory chips 12A to 12F is reduced, the manufacturing cost of the memory module 10 can be reduced.

Hereinafter, structures of the first wiring CA1 and the second wiring CA2 formed in the printed circuit board 11 will be described in detail.

3 is a diagram for explaining a solder ball according to an exemplary embodiment, and FIGS. 4 and 5 are diagrams for explaining a wiring structure of a memory module according to an exemplary embodiment. In detail, FIG. 3 is a ball map for explaining the arrangement of solder balls of the memory chip 12 of FIG. 2, and FIG. 4 is a ball map of the memory module 10 of FIG. 5 is a cross-sectional view taken along line BB' of the memory module 10 of FIG. 2 .

Referring to FIG. 3 , the memory chip 12 may include a plurality of solder balls SB. This embodiment will be described centering on the memory chip 12 configured in the form of a ball grid array (BGA), but is not limited thereto. For example, the memory chip 12 may be connected to the printed circuit board 11 in the form of a Land Grid Array (LGA).

The solder balls SB may be disposed on a contact surface CS where the memory chip 12 faces the printed circuit board 11 . The solder balls SB may be electrodes for external connection. The solder balls SB may be continuously disposed in the first direction (X), and may be partially discontinuously disposed in the second direction (Y). The number of solder balls SB disposed in the first direction X may be greater than the number of solder balls disposed in the second direction Y.

The solder balls SB may be disposed separately in the first area A1 and the second area A2. In the first area A1, solder balls SB used to provide a command signal for controlling the operation of a memory cell or memory circuit integrated in the memory chip 12 and an address signal for providing an address location may be disposed. , In the second area A2, solder balls SB used to input or output data at a designated address may be disposed. That is, solder balls of the first area A1 may be signal pins for C/A signals, and solder balls of the second area A2 may be signal pins for DQ signals.

Referring to Figures 4 and 5, The printed circuit board 11 may be composed of multi-layers. For example, the printed circuit board 11 may include first to sixth layers L1 to L6. An upper surface of the first layer L1 may be the surface S1 of the printed circuit board 11 . Solder balls SB may contact the upper surface of the first layer L1. In this embodiment, the first to sixth layers L1 to L6 are shown, but are not limited thereto.

The first layer L1 may include a landing pad (LP). The landing pad LP may be exposed on the printed circuit board 11 . That is, the upper surface of the landing pad LP may be exposed on the first surface S1 of the printed circuit board 11 . The landing pad LP may transmit a C/A signal to the plurality of memory chips 12A to 12F by being connected to the solder balls SB included in the plurality of memory chips 12A to 12F. That is, the plurality of memory chips 12A to 12F may be electrically connected to the printed circuit board 11 through the landing pad LP.

A gap between the landing pads LP may be filled with a first insulating material I1. For example, the insulating material I1 may include glass or plastic. The insulating material (I1) includes chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or polyimide (PI), polyethylene terephthalate (PET), propylene Reinforced or soft plastics such as glycol (propylene glycol, PPG) and polycarbonate (PC) may be included, or sapphire may be included. In addition, the insulating material I1 may include an optical isotropic film. For example, the insulating material I1 may include Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), polycarbonate (PC), or polymethyl methacrylate (PMMA). .

A second layer L2 may be disposed under the first layer L1. The height of the second layer L2 may be higher than that of the first layer L1. The second layer L2 may include the same material as the first insulating material I1. For example, the second layer L2 may include propylene glycol (PPG). The second layer L2 may include a first via V1 connected to the landing pad LP. The first via V1 may be formed through the second layer L2.

A third layer L3 may be disposed under the second layer L2. The third layer L3 may include a first wire CA1 and a second insulating material I2. The first wiring CA1 may be connected to the landing pad LP through the first via V1 and electrically connected to the memory chips 12A to 12F by being connected to the solder balls SB through the landing pad LP. can be connected As shown in FIG. 2 , the first wire CA1 may be formed in a straight line extending in the second direction Y. The second insulating material I2 may insulate the first wirings CA1 from each other by filling the gap between the first wirings CA1. The second insulating material I2 may include the same material as the first insulating material I1.

A fourth layer L4 may be disposed under the third layer L3. The height of the fourth layer L4 may be higher than the heights of the first layer L1 and the third layer L3. The fourth layer L4 may include the same material as the first insulating material I1. For example, the fourth layer L4 may include propylene glycol (PPG). The fourth layer L4 may include a second via V2 connected to the first line CA1. The second via V2 may be formed through the fourth layer L4.

A fifth layer L5 may be disposed under the fourth layer L4. The fifth layer L5 may include a second wire CA2 and a third insulating material I3. The second wire CA2 may be connected to the first wire CA1 through the second via V2. That is, the second line CA1 may be electrically connected to the memory chips 12A to 12F through the first via V1 and the second via V2. As shown in FIG. 2 , the second wire CA2 may be formed in a straight line extending between the first direction X and the second direction Y. The length W1 of the first wire CA1 may be shorter than the length W2 of the second wire CA2, but is not limited thereto.

The third insulating material I3 may insulate the second wires CA2 from each other by filling the gap between the second wires CA2 . The third insulating material I3 may include the same material as the first insulating material I1.

A sixth layer L6 may be disposed below the fifth layer L5. The sixth layer L6 may include the same material as the first insulating material I1. For example, the sixth layer L6 may include propylene glycol (PPG).

According to the present embodiment, the first wiring CA1 and the second wiring CA2 disposed on different layers are connected to each other through the second via V2, and the memory chips 12A through the first via V1. ~12F). That is, the first wire CA1 and the second wire CA2 may transmit the C/A signal to the plurality of memory chips 12A to 12F through the first via V1 and the second via V2.

In this embodiment, the first layer L1 is illustrated as including the landing pad LP, but is not limited thereto. For example, a separate layer may be provided between the first layer L1 and the second layer L2. In this case, the first via V1 connecting the landing pad LP and the first line CA1 may be formed as a through via penetrating a plurality of layers.

In this embodiment, it is shown that the third layer (L3) and the fourth layer (L4) are continuously stacked, but in another embodiment, a plurality of layers are further formed between the third layer (L3) and the fourth layer (L4). can be placed. In this case, the second via V2 connecting the first wiring CA1 and the second wiring CA2 may be formed as a through via penetrating a plurality of layers.

Since the first wiring CA1, the second wiring CA2, the first via V1, the second via V2, and the landing pad LP are wires that transmit electrical signals, they are formed of highly electrically conductive metal materials. It can be. For example, the first wiring CA1 , the second wiring CA2 , the first via V1 , the second via V2 , and the landing pad LP may include gold (Au), silver (Ag), platinum ( It may include at least one of Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first wiring CA1 , the second wiring CA2 , the first via V1 , the second via V2 , and the landing pad LP are made of gold (Au), silver (Ag), It may be formed of a paste or solder paste containing at least one metal material of platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In this embodiment, the first wiring CA1, the second wiring CA2, the first via V1, the second via V2, and the landing pad LP are made of copper (Cu) having high electrical conductivity and relatively low price. ), but is not limited thereto.

As in the present disclosure, by configuring the first wire CA1 and the second wire CA2 in a straight line shape extending in a specific direction, the overall length of the wires transmitting the C/A signal may be shortened. Accordingly, since the length of lines through which the C/A signal passes is shortened, a signal cross talk phenomenon can be improved. That is, the memory module 10 having enhanced signal characteristics can be provided.

6 is a plan view of a memory module according to example embodiments. In detail, it is a diagram showing an embodiment of implementing the memory module 3 of FIG. 1 . That is, FIG. 6 is another embodiment of FIG. 2 . Hereinafter, description will be made with reference to FIGS. 1 to 5, and overlapping descriptions will be omitted.

Referring to FIG. 6 , the memory module 20 may include a printed circuit board 11 and memory chips 21A to 21G mounted on the printed circuit board 11 .

The printed circuit board 11 may have a length in the first direction (X) longer than a length in the second direction (Y), and each of the plurality of memory chips 21A to 21G also has a length in the first direction (X). The length of may be longer than the length of the second direction (Y). Although not shown in FIG. 5 , the plurality of memory chips 21A to 21G may include solder balls arranged as shown in FIG. 4 . That is, each of the plurality of memory chips 21A to 21G may include solder balls continuously arranged in the first direction (X) and partially discontinuously arranged in the second direction (Y). Each of the plurality of memory chips 21A to 21G may be electrically connected to the printed circuit board through solder balls.

The memory chips 21A to 21G may be arranged at regular intervals from each other in the first direction (X) and the second direction (Y). The memory chips 21A to 21G may be arranged in at least two columns, with memory chips disposed in a first column (eg, 21A, 21B, 21C, and 21D) and memory chips disposed in a second column (eg, 21E). , 21F, 21G) may be displaced. That is, a plurality of memory chips (eg, 21A, 21B, 21C, and 21D) disposed in the same column may be disposed on the same axis in the first direction (X). Memory chips (eg, 21A and 21E) adjacent to each other in the second direction Y and disposed in different columns may be disposed on different axes in the second direction Y. In this case, the fifth memory chip 21E is disposed in a different column from the first memory chip 21A and the second memory chip 21B, and is disposed between the first memory chip 21A and the second memory chip 21B. can be placed. That is, a plurality of memory chips (eg, 21A, 21B, 21C, and 21D) disposed in a first column and a plurality of memory chips (eg, 21E, 21F, and 21G) disposed in a second column adjacent to the first column. may be arranged to have a constant offset from each other.

The printed circuit board 11 may include a third wire CA3 and a fourth wire CA4 . The third wiring CA3 and the fourth wiring CA4 are formed inside the printed circuit board 11, but are shown on the printed circuit board 11 and the memory chips 21A to 21G for convenience of description.

As described above with reference to FIGS. 3 to 5 , the third wiring CA3 and the fourth wiring CA4 form the landing pad LP of the printed circuit board 11 and the plurality of memory chips 21A to 21G. It may be included in a C/A signal line for transmitting a C/A signal to the plurality of memory chips 21A to 21G through the solder balls of .

. The C/A signal line may include a third wire CA3 and a fourth wire CA4 that are alternately and repeatedly disposed. The third wiring CA3 and the fourth wiring CA4 may be formed in a zigzag shape inside the printed circuit board 11 . The length W3 of the third wire CA3 may be equal to the length W4 of the fourth wire CA4. Accordingly, since the speed of a signal transmitted between the memory chips 21A to 21G is constantly provided, signal characteristics may be improved.

As described above with reference to FIGS. 4 and 5 , the third and fourth wires CA3 and CA4 may be disposed on different layers of the printed circuit board 11, and the third and fourth wires CA3 and CA4 may be disposed on different layers. 4 may be electrically connected to each other through a via V connecting the wires CA4. The via V may include the first via (V1 in FIG. 4 ) and the second via (V2 in FIG. 4 ) described above with reference to FIGS. 4 and 5 . The first via may be formed in the third direction Z to connect the third wire CA3 and the landing pad, and the second via may connect the third wire CA3 and the fourth wire CA4. It may be formed in the third direction (Z). Depending on the embodiment, the via V may be configured as a through via.

According to embodiments, the third wire CA3 may be disposed in a layer closer to the plurality of memory chips 21A to 21G in the third direction Z than the fourth wire CA4, but is not limited thereto. The fourth wire CA4 may be disposed on a layer closer to the plurality of memory chips 21A to 21G in the third direction Z than the third wire CA3 .

7 is a plan view of a memory module according to example embodiments. In detail, it is a diagram showing an embodiment of implementing the memory module 3 of FIG. 1 . That is, FIG. 7 is another embodiment of FIG. 2 . Hereinafter, description will be made with reference to FIGS. 1 to 5, and overlapping descriptions will be omitted.

Referring to FIG. 7 , the memory module 30 may include a printed circuit board 11 and memory chips 31A to 31F mounted on the printed circuit board 11 .

The printed circuit board 11 may have a length in the first direction (X) longer than a length in the second direction (Y), and each of the plurality of memory chips 31A to 31F may also have a length in the first direction (X). The length of may be longer than the length of the second direction (Y). Although not shown in FIG. 7 , the plurality of memory chips 31A to 31F may include solder balls arranged as shown in FIG. 3 . That is, each of the plurality of memory chips 31A to 31F may include solder balls continuously arranged in the first direction (X) and partially discontinuously arranged in the second direction (Y). Each of the plurality of memory chips 31A to 31F may be electrically connected to the printed circuit board through solder balls.

The memory chips 31A to 31F may be arranged at regular intervals from each other in the first direction (X) and the second direction (Y). The memory chips 31A to 31F may be arranged in at least two columns, and memory chips disposed in the first column (eg, 31A, 31B, and 31C) are disposed in the second column (eg, 31D and 31E). , 31F) can be arranged side by side. That is, a plurality of memory chips (eg, 31A, 31B, and 31C) disposed in the same column may be disposed on the same axis in the first direction (X). Memory chips (eg, 31A and 31D) adjacent to each other in the second direction Y and disposed in different columns may be disposed on the same axis in the second direction Y.

The printed circuit board 11 may include a fifth wire CA5 and a sixth wire CA6 . The fifth wiring CA5 and the sixth wiring CA6 are formed inside the printed circuit board 11, but are shown on the printed circuit board 11 and the memory chips 31A to 31F for convenience of description.

As described above with reference to FIGS. 3 to 5 , the fifth wiring CA5 and the sixth wiring CA6 form the landing pad LP of the printed circuit board 11 and the plurality of memory chips 31A to 31F. A signal may be transmitted to the plurality of memory chips 31A to 31F through the solder balls. For example, the fifth wire CA5 and the sixth wire CA6 may be included in a C/A signal line for transmitting a C/A signal to the memory chips 31A to 31F.

The C/A signal line may include a fifth wire CA5 and a sixth wire CA6 that are alternately and repeatedly disposed. The fifth wiring CA5 and the sixth wiring CA6 may be arranged in a zigzag pattern inside the printed circuit board 11 . The fifth wire CA5 may be formed in a straight line extending in a direction between the first direction X and the second direction Y, and the sixth wire CA6 intersects the fifth wire CA5. It may be formed in a straight line shape extending in the direction. The fifth wire CA5 and the sixth wire CA6 may have the same length. Accordingly, since the speed of a signal transmitted between the memory chips 21A to 21G is constantly provided, signal characteristics may be improved.

As described above with reference to FIGS. 4 and 5 , the fifth wiring CA5 and the sixth wiring CA6 may be disposed on different layers of the printed circuit board 11 and are electrically connected through the vias V. can be connected The via V may include the first via (V1 in FIG. 4 ) and the second via (V2 in FIG. 4 ) described above with reference to FIGS. 4 and 5 . The first via (V1 in FIG. 4 ) may be formed in the third direction (Z) to connect the fifth wire CA5 and the landing pad, and the second via (V2 in FIG. 4 ) is the fifth wire CA5 ) and the sixth wire CA6, it may be formed in the third direction Z. Depending on the embodiment, the via V may be configured as a through via. In this embodiment, the via V may not be formed at the intersection of the fifth and sixth wires CA5 and CA6 . That is, the via V may be formed only at the ends of the fifth and sixth wires CA5 and CA6.

According to embodiments, the fifth wire CA5 may be disposed in a layer closer to the plurality of memory chips 31A to 31F than the sixth wire CA6, but is not limited thereto, and the sixth wire CA6 is It may be disposed in a layer closer to the plurality of memory chips 31A to 31F than the 5 wire CA5.

8A and 8B are diagrams illustrating memory modules 100 and 100' according to exemplary embodiments. In detail, FIGS. 8A and 8B may show another embodiment of the memory module 3 of FIG. 1 . Hereinafter, the memory modules 100 and 100' will be described with reference to FIGS. 1 to 5 .

Referring to FIG. 8A , the memory module 100 may be implemented as a dual in-line memory module (DIMM) conforming to a joint electron device engineering council (JEDEC) standard. For example, the memory module 100 may include a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). .

The memory module 100 may include memory chips C101 to C118 disposed on the printed circuit board 101 , an RCD controller 102 (Registered Clock Driver controller), and a tab 104 .

The memory chips C101 to C118 may be arranged so that a length in the first direction (X) is longer than a length in the second direction (Y). The solder balls SB included in each of the memory chips C101 to C118 may be continuously arranged in the first direction (X) and partially discontinuously arranged in the second direction (Y).

The memory chips C101 to C118 may be arranged in two columns. Some of the memory chips C101 to C118 may be disposed on the left side of the RCD controller 102, and some of the memory chips C101 to C118 may be disposed on the right side of the RCD controller 102. The memory chips C101 to C118 arranged in different columns may be arranged side by side. That is, memory chips (eg, C101 and C110) neighboring in the second direction Y may be disposed on the same axis in the second direction Y.

FIG. 8A shows 18 memory chips C101 to C118 disposed on the first surface 103 of the printed circuit board 101, but is not limited thereto, and the memory module 100 includes the printed circuit board 101. It may further include 18 memory chips disposed on a second surface opposite to the first surface 103 . The memory chips disposed on the first surface 103 of the printed circuit board 101 and the memory chips disposed on the second surface of the printed circuit board 101 may constitute different memory ranks.

In another embodiment, some of the memory chips C101 to C118 may be composed of ECC chips. The ECC chip may be a memory chip providing an error correction code for stored data. In one embodiment, the error correction code may include at least one of parity and a cyclic redundancy code (CRC).

The memory chips C101 to C118 may operate in response to the C/A signal and the DQ signal. As described above with reference to FIGS. 2 to 5 , a C/A signal line including wiring formed in a zigzag shape inside the substrate 101 to transmit the C/A signal to the memory chips C101 to C118. can be formed. The C/A signal line may include a first wiring CA1 and a second wiring CA2 formed in a straight line inside the substrate 101 . The first wire CA1 and the second wire CA2 may correspond to the first wire CA1 and the second wire CA2 of FIG. 2 .

For example, the first memory chip C101 and the second memory chip C110 may be connected through a first wire CA1 configured in a straight line extending in the second direction Y, and the second memory chip ( C110) and the third memory chip C102 may be connected through a second line CA2 configured in a straight line extending in a direction between the first direction X and the second direction Y.

The first wire CA1 and the second wire CA2 may form a wire structure by using different layers. The first wire CA1 and the second wire CA2 may be electrically connected through the via V.

The RCD controller 102 may control the memory chips C101 to C118 under the control of the memory controller (2 in FIG. 1 ) that controls the memory module 100 . For example, the RCD controller 102 may receive a C/A signal (C/A in FIG. 1) and a DQ signal (DQ in FIG. 1) from the memory controller (2 in FIG. 1). Although not shown, the RCD controller 102 may further receive a clock signal and a control signal from the memory controller (2 in FIG. 1). The RCD controller 102 may control the memory chips C101 to C118 in response to the received signals. RCD controller 102 may perform a buffer function.

The tab 104 may be a passage through which signals are transmitted and received between the memory module 100 and an external device. The tab 104 may be formed on an edge portion of a first surface 103 of the printed circuit board 101 and a second surface opposite to the first surface 103 . The tab 104 may have a plurality of connecting terminals, also referred to as 'tab pins'. The tap 104 may be assigned C/A signal input pins, no connection pins, and DQ signal pins. The memory module 100 may be electrically connected to a main board of an electronic circuit system such as a personal computer or a workstation through the tab 104 .

Referring to FIG. 8B , the memory module 100' may be another embodiment of the memory module 100 of FIG. 8A. The same reference numerals denote the same components, and duplicate descriptions are omitted.

The memory chips C101 to C118 may operate in response to the C/A signal and the DQ signal. As described above with reference to FIGS. 3 to 5, 7, and 8A, wiring formed in a zigzag shape inside the substrate 101 to transmit the C/A signal to the memory chips C101 to C118 is included. A C/A signal line may be formed. The C/A signal lines may have a wiring structure arranged in a zigzag pattern in units of two columns.

The C/A signal line may include a fifth wire CA5 and a sixth wire CA6 configured in a straight line inside the substrate 101 . The fifth wire CA5 and the sixth wire CA6 may correspond to the fifth wire CA5 and the sixth wire CA6 of FIG. 7 . The fifth wire CA5 may have a straight line extending in a direction between the first direction X and the second direction Y, and the sixth wire CA6 may intersect the fifth wire CA5. It may have a straight line shape extending to . The fifth wire CA5 and the sixth wire CA6 may be formed on different layers. The fifth wire CA5 and the sixth wire CA6 may have the same length.

9 is a diagram illustrating a memory module 200 according to an exemplary embodiment. In detail, FIG. 9 may represent another embodiment of the memory module 3 of FIG. 1 . Hereinafter, the memory module 200 will be described with reference to FIGS. 1 to 5 .

Referring to FIG. 9 , the memory module 200 is a SODIMM (Small Inline Memory Module) used in a device that emphasizes mobility, such as a mobile device or a notebook computer, among memory modules adopting a DIMM (Dual In-line Memory Module) structure. Outline Dual In-line Memory Module).

The memory module 200 may include memory chips C201 to C208 and a tab 202 disposed on a printed circuit board 201 .

The memory chips C201 to C208 may be arranged with a length in the first direction (X) longer than a length in the second direction (Y), and solder balls SB included in each of the memory chips C201 to C208 may be continuously arranged in the first direction (X).

The memory chips C201 to C208 may be arranged in two rows. The memory chips C201 to C208 may be uniformly arranged at regular intervals in the first direction (X). The memory chips C201 to C208 disposed in different columns may be alternately disposed in the second direction Y. That is, the memory chips disposed in the first column (eg, C201, C202, C203, and C204) interact with the memory chips disposed in the second column (eg, C206, C207, and C208) in the second direction (Y). Can be placed on different axes.

9 shows eight memory chips C201 to C208 disposed on the first surface 203 of the printed circuit board 201, but is not limited thereto, and the memory module 200 includes the printed circuit board 201. Eight memory chips disposed on a second surface opposite to the first surface 203 may be further included. The memory chips disposed on the first surface 203 of the printed circuit board 201 and the memory chips disposed on the second surface of the printed circuit board 201 may constitute different memory ranks. In another embodiment, some of the memory chips C201 to C208 may be composed of ECC chips.

The memory chips C201 to C208 may operate in response to the C/A signal and the DQ signal. As described above in FIG. 6 , in order to transmit the C/A signal to the memory chips C201 to C208, the third wiring CA3 and the fourth wiring CA4 formed in a straight line inside the substrate 201 are zigzag. can be placed in the form The third wire CA3 and the fourth wire CA4 may have the same length. The third wire CA3 and the fourth wire CA4 may be disposed on different layers and may be electrically connected to each other through the via V.

10 is a diagram illustrating a memory module 300 according to an exemplary embodiment. In detail, FIG. 10 may represent another embodiment of the memory module 3 of FIG. 1 . Hereinafter, the memory module 300 will be described with reference to FIGS. 1 to 5 .

Referring to FIG. 10 , a memory module 300 includes memory chips 302 disposed on a printed circuit board 301, a controller 303, a first PMIC 304 (first power management IC), and a second PMIC 305. ) and tabs 306 .

The memory chips 302 may be arranged longer in the first direction (X) than the length in the second direction (Y), and the solder balls SB included in each of the memory chips 302 are arranged in the first direction. It may be arranged continuously in (X) and partially discontinuously arranged in the second direction (Y).

The memory chips 302 may be arranged at regular intervals in the first direction (X) and the second direction (Y). The memory chips 302 may be arranged in six columns, and five memory chips may be arranged in each column. Memory chips 302 arranged in different columns may be arranged side by side.

10 shows 30 memory chips 302 disposed on the first surface 307 of the printed circuit board 301, but is not limited thereto, and the memory module 300 includes the first surface 307 of the printed circuit board 301. It may further include 30 memory chips disposed on a second surface opposite to surface 307 . The memory chips disposed on the first surface 307 of the printed circuit board 301 and the memory chips disposed on the second surface of the printed circuit board 301 may constitute different memory ranks.

In another embodiment, some of the memory chips 302 may be composed of ECC chips. The ECC chip may be a memory chip providing an error correction code for stored data. In one embodiment, the error correction code may include at least one of parity and a cyclic redundancy code (CRC).

The memory chips 302 may operate in response to the C/A signal and the DQ signal. As described above with reference to FIG. 7 , in order to transmit the C/A signal to the memory chips 302, the fifth wiring CA5 and the sixth wiring CA6 configured in a straight line are zigzag inside the printed circuit board 301. can be placed in the form

In the memory chips 302 , wires may be formed in units of two columns. For example, the wires transmitting the C/A signal are between the first row R1 and the second row R2, between the third row R3 and the fourth row R4, and the fifth row R5. and the sixth row R6 may be arranged in a zigzag pattern. The memory chips 302 may be wired in two columns in the form described above with reference to FIG. 7 .

That is, the wiring structure arranged in a zigzag pattern in two rows extends in a direction crossing the fifth wiring CA5 having a straight line extending in a direction between the first direction X and the second direction Y. A sixth wire CA6 having a straight line shape may be included. The fifth wire CA5 and the sixth wire CA6 may be formed on different layers. The fifth wire CA5 and the sixth wire CA6 may have the same length.

The controller 303 may control the memory chips 302, the first PMIC 304, and the second PMIC 305 according to the control of the memory controller (2 in FIG. 1) that controls the memory module 300. . For example, the controller 303 may receive a C/A signal (C/A in FIG. 1 ) and a DQ signal (DQ in FIG. 1 ) from the memory controller (2 in FIG. 1 ). Although not shown, the controller 303 may further receive a clock signal and a control signal from the memory controller (2 in FIG. 1). A C/A signal (C/A in FIG. 1) and a DQ signal (DQ in FIG. 1) may be received from the memory controller (2 in FIG. 1). Although not shown, the controller 303 may further receive a clock signal and a control signal from the memory controller (2 in FIG. 1). The controller 303 may control the memory chips 302 in response to the received signals. The controller 303 may perform a buffer function.

The first PMIC 304 and the second PMIC 305 may receive external power, generate a power voltage, and supply the generated power voltage to the plurality of memory chips 302 . The plurality of memory chips 302 may operate by receiving a power supply voltage from the first PMIC 304 and the second PMIC 305 .

The tap 306 may be a passage through which signals are transmitted and received between the memory module 300 and an external device. The tab 306 may be formed on an edge portion of a first surface 307 of the printed circuit board 301 and a second surface opposite to the first surface 307 . The tab 306 may have a plurality of connecting terminals, also referred to as 'tab pins'. C/A signal input pins and DQ signal pins may be assigned to the tap 306 . The memory module 300 may be electrically connected to a main board of an electronic circuit system such as a personal computer or a workstation through a tab 306 .

11 is a block diagram illustrating an example of applying a memory module according to an exemplary embodiment to a computing system.

Referring to FIG. 11 , a computing system 400 may include a processor 410 , a system controller 420 and a memory system 430 . The computing system 400 may further include a processor bus 440 , an expansion bus 450 , an input device 460 , an output device 470 and a storage device 480 .

The computing system 400 includes a UMPC (Ultra Mobile PC), a workstation, a net-book, a PDA (Personal Digital Assistants), a portable computer, a web tablet, a tablet computer, Wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console, navigation device, black box (black box) box), digital camera, DMB (Digital Multimedia Broadcasting) player, 3-dimensional television, digital audio recorder, digital audio player, digital video recorder ( digital picture recorder), digital picture player, digital video recorder, digital video player, storage constituting a data center, a device capable of transmitting and receiving information in a wireless environment, One of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system. It may be changed or extended to one of various components of an electronic device, such as one.

Processor 410 may execute various computing functions, such as executing specific software to perform specific calculations or tasks. For example, processor 410 may be a microprocessor or central processing unit. The processor 410 may be coupled to the system controller 420 through a processor bus 440 that includes an address bus, a control bus, and/or a data bus.

A host interface between the processor 410 and the system controller 420 includes various protocols for performing data exchange. For example, the system controller 420 may use a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, and an Advanced Technology Attachment (ATA) protocol. , Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol. It can be configured to communicate with the outside world.

The system controller 420 is coupled to an expansion bus 450, such as a peripheral component interconnect (PCI) bus. Accordingly, the processor 410, via the system controller 420, receives one or more input devices 460 such as a keyboard or mouse, one or more output devices 470 such as a printer or display device, or a hard disk drive or solid state drive. Alternatively, one or more storage devices 480 such as a CD-ROM may be controlled.

The memory controller 431 may control the memory module 432 to execute commands provided by the processor 410 . The memory module 432 may store data provided from the memory controller 431 and provide the stored data to the memory controller 431 .

The memory module 432 may include a plurality of semiconductor memory devices, for example, volatile memory including dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory. May contain volatile memory. Volatile memory may include dynamic random access memory (DRAM), static random access memory (SRAM), thyristor RAM (TRAM), zero capacitor RAM (Z-RAM), twin transistor RAM (TTRAM), or MRAM. Non-volatile memory includes electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (spin-transfer torque MRAM), conductive bridging RAM (CBRAM), and ferroelectric RAM (FeRAM). ), PRAM (Phase change RAM), Resistive RAM (RRAM), Nanotube RRAM (Polymer RAM: PoRAM), Nano Floating Gate Memory (NFGM), Holographic It may be a holographic memory, a molecular electronics memory device, or an insulation resistance change memory. One or more bits may be stored in a unit cell of the nonvolatile memory.

The memory module 432 may correspond to the memory module described above with reference to FIGS. 2 to 10 , and the plurality of semiconductor memory devices may correspond to the plurality of memory chips described above with reference to FIGS. 2 to 10 . . That is, the memory module 432 may be formed based on a printed circuit board wired in a zigzag pattern to transmit C/A signals.

12 is a block diagram illustrating an example of applying a memory module according to an exemplary embodiment to a mobile system.

Referring to FIG. 12, the mobile system 500 includes an application processor 910, a communication module 520 (connectivity module), a user interface 530, a non-volatile memory device 540, a memory module 550, and a power supply ( 560). The application processor 510 may include a memory controller 511 .

The application processor 510 may execute applications providing Internet browsers, games, videos, and the like. The communication module 520 may perform wireless or wired communication with an external device. The user interface 530 may include one or more input devices, such as a keypad or touch screen, and/or one or more output devices, such as speakers or display devices. The non-volatile memory device 540 may store a boot image for booting the mobile system 500 .

The memory module 550 may store data processed by the application processor 510 or may operate as a working memory. The memory module 550 may include a plurality of memory chips 551 and an RCD controller 552 . The memory module 550 may correspond to the memory module described above with reference to FIGS. 2 to 10 . That is, the memory module 550 may be formed based on a printed circuit board wired in a zigzag pattern to transmit C/A signals.

The power supply 560 may supply an operating voltage of the mobile system 500 . The mobile system 500 or components of the mobile system 500 may be mounted using various types of packages.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Embodiments have been described using specific terms in this specification, but they are only used for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the scope of the present disclosure described in the meaning or claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (10)

a printed circuit board including multi-layers and having a length in a first direction longer than a length in a second direction perpendicular to the first direction;
a first memory chip mounted on the printed circuit board and having a length in the first direction longer than a length in the second direction;
a second memory chip disposed apart from the first memory chip in the second direction and having a length in the first direction longer than a length in the second direction;
a third memory chip disposed apart from the first memory chip in the first direction and having a length in the first direction longer than a length in the second direction;
a fourth memory chip disposed apart from the second memory chip in a first direction and having a length in the first direction longer than a length in the second direction; and
a signal line for transmitting an address/command signal to each of the first to fourth memory chips;
The signal line is
a first wire formed in the printed circuit board, connecting between the first memory chip and the second memory chip, and connecting between the third memory chip and the fourth memory chip; and
A memory module comprising a second wire formed in the printed circuit board and connecting between the second memory chip and the third memory chip. According to claim 1,
The first wire and the second wire are
A memory module, characterized in that included in different layers included in the multi-layer. According to claim 2,
The memory module,
a landing pad exposed on the printed circuit board and electrically connecting the first to fourth memory chips and the printed circuit board;
a first via electrically connecting the landing pad and the first wire; and
The memory module of claim 1, further comprising a second via electrically connecting the first wire and the second wire. According to claim 1,
The second memory chip,
disposed on the same axis as the first memory chip in the second direction;
The fourth memory chip,
The memory module, characterized in that disposed on the same axis as the third memory chip in the second direction. According to claim 4,
The first wire has a straight line extending in the second direction,
The memory module according to claim 1 , wherein the second wire has a straight line extending in a direction between the first direction and the second direction. According to claim 4,
The first wire has a straight line extending in a direction between the first direction and the second direction;
The memory module according to claim 1 , wherein the second wiring has a straight line extending in a direction crossing the first wiring. According to claim 1,
The second memory chip,
disposed on an axis different from that of the first memory chip in the second direction;
The fourth memory chip,
The memory module, characterized in that disposed on a different axis from the third memory chip in the second direction. According to claim 1,
The memory module, characterized in that the length of the first wire and the length of the second wire are equal to each other. a printed circuit board including multi-layers on which a wiring structure is formed, and a length in a first direction is longer than a length in a second direction perpendicular to the first direction; and
On the printed circuit board, a plurality of memory chips including a plurality of solder balls arranged in a first row and a second row extending in the first direction, respectively;
The plurality of solder balls,
continuously arranged in the first direction, partially discontinuously arranged in the second direction, and the number arranged in the first direction is greater than the number arranged in the second direction;
The wiring structure is
A memory module comprising alternately connecting the plurality of memory chips arranged in the first column and the second column in a zigzag pattern within the printed circuit board. According to claim 9,
The wiring structure is
a first wire connecting the plurality of memory chips disposed in the first column and the second column in a straight line extending in a third direction;
It is formed on a layer different from the layer on which the first wire is formed and connects the plurality of memory chips disposed in the first column and the second column in a straight line extending in a fourth direction, which is different from the third direction. 2 wires; and
A memory module comprising a via electrically connecting the first wire and the second wire.

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