KR20220158425A - 3d flash memory manufactured through gate first process - Google Patents

Abstract

A three-dimensional flash memory manufactured through a gate first process is disclosed. According to one embodiment, a 3D flash memory includes stacked structures extending in a horizontal direction on a substrate and including interlayer insulating films and gate electrodes alternately stacked in a vertical direction; and vertical channel structures penetrating each of the stacked structures and extending in the vertical direction, each of the vertical channel structures covering a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern, and and a vertical channel pattern extending in a vertical direction, wherein the data storage pattern and the vertical channel pattern configure memory cells corresponding to the word lines, and each of the interlayer insulating films is formed of a metal oxide. formation can be characterized.

Description

3D flash memory manufactured through gate first process {3D FLASH MEMORY MANUFACTURED THROUGH GATE FIRST PROCESS}

The following embodiments relate to a 3D flash memory, and more specifically, a technology for a 3D flash memory manufactured through a gate first process.

A flash memory device is an electrically erasable programmable read only memory (EEPROM) by electrically controlling input and output of data by Fowler-Nordheimtunneling or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, and the like.

In such a flash memory device, a three-dimensional structure in which memory cell transistors are arranged in a vertical direction to form a cell string has been proposed to increase the degree of integration in order to meet the excellent performance and low price demanded by consumers.

3D flash memory has a problem in that the WL replacement process using a sacrificial layer is difficult to apply in manufacturing a word line, as the pitch of vertical cells has recently become extremely small for integration.

Accordingly, a gate first process for forming a word line without using a sacrificial layer has been proposed, but a problem in that the profile of channel holes is not uniform occurs during the gate first process.

Accordingly, the embodiments below seek to propose a technique to solve the described problem.

Embodiments provide a three-dimensional flash memory in which interlayer insulating layers are formed of metal oxide, a manufacturing method thereof, and an electronic system including the same, in order to solve the problem that the profile of channel holes is not uniform in applying the gate first process. Suggest.

In addition, embodiments of the present invention propose a three-dimensional flash memory, a manufacturing method thereof, and an electronic system including the same, which ensure insulation properties even when each of the interlayer insulation layers is formed of metal oxide.

However, the technical problems to be solved by the present invention are not limited to the above problems, and can be variously expanded without departing from the technical spirit and scope of the present invention.

According to an embodiment, a 3D flash memory may include stacked structures extending in a horizontal direction on a substrate and including interlayer insulating films and gate electrodes alternately stacked in a vertical direction; and vertical channel structures penetrating each of the stacked structures and extending in the vertical direction, each of the vertical channel structures covering a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern, and and a vertical channel pattern extending in a vertical direction, wherein the data storage pattern and the vertical channel pattern configure memory cells corresponding to the word lines, and each of the interlayer insulating films is formed of a metal oxide. formation can be characterized.

According to one aspect, each of the interlayer insulating films is formed of an oxide of a metal material constituting the gate electrodes.

According to another aspect, each of the interlayer insulating films may be characterized in that an insulation blocking film thinner than a thickness of each of the interlayer insulating films is embedded.

According to one embodiment, a method of manufacturing a three-dimensional flash memory includes preparing a semiconductor structure including interlayer insulating films and gate electrodes that are alternately stacked along a vertical direction while extending in a horizontal direction on a substrate; forming channel holes penetrating the semiconductor structure in the vertical direction; and forming vertical channel structures extending in the vertical direction inside the channel holes, wherein each of the interlayer insulating films is formed of a metal oxide.

According to one aspect, each of the interlayer insulating films may be characterized in that an insulation blocking film thinner than a thickness of each of the interlayer insulating films is embedded.

Embodiments provide a three-dimensional flash memory in which interlayer insulating layers are formed of metal oxide, a manufacturing method thereof, and an electronic system including the same, in order to solve the problem that the profile of channel holes is not uniform in applying the gate first process. can suggest

Accordingly, the 3D flash memory according to the exemplary embodiments may achieve an effect of uniformizing the profile of etched channel holes.

In addition, one embodiment may propose a 3D flash memory, a method of manufacturing the same, and an electronic system including the same, even if each of the interlayer insulating layers is formed of a metal oxide to ensure an insulating property.

However, the effects of the present invention are not limited to the above effects, and can be variously extended without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.
2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment.
FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'.
FIG. 4 is a cross-sectional view illustrating another implementation example of interlayer insulating films included in the 3D flash memory shown in FIG. 3, and corresponds to a cross-section of FIG. 2 taken along line A-A'.
FIG. 5 is a cross-sectional view showing the structure of a 3D flash memory according to another embodiment, corresponding to a cross-section of FIG. 2 taken along line A-A'.
FIG. 6 is a cross-sectional view illustrating another implementation example of interlayer insulating films included in the 3D flash memory shown in FIG. 5, and corresponds to a cross-section of FIG. 2 taken along line A-A'.
7 is a flowchart illustrating a method of manufacturing a 3D flash memory according to embodiments.
8A to 13 are cross-sectional views for explaining a manufacturing method performed to manufacture a 3D flash memory having the structure shown in FIGS. 3 to 4 .
14A to 19 are cross-sectional views illustrating a manufacturing method performed to manufacture a 3D flash memory having the structure shown in FIGS. 5 to 6 .
22 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, terms used in this specification (terminology) are terms used to appropriately express preferred embodiments of the present invention, which may vary according to the intention of a viewer or operator or customs in the field to which the present invention belongs. Therefore, definitions of these terms will have to be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. Also, as used herein, "comprises" and/or "comprising" means that a referenced component, step, operation, and/or element is one or more other components, steps, operations, and/or elements. The presence or addition of elements is not excluded. In addition, although terms such as first and second are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a portion referred to as a first portion in one embodiment may be referred to as a second portion in another embodiment.

Also, it should be understood that the various embodiments of the present invention are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one embodiment in another embodiment without departing from the spirit and scope of the present invention. In addition, it should be understood that the location, arrangement, or configuration of individual components in the scope of each embodiment presented may be changed without departing from the spirit and scope of the present invention.

Hereinafter, a 3D flash memory according to embodiments, an operating method thereof, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.

Referring to FIG. 1 , a three-dimensional flash memory array according to an embodiment includes a common source line CSL, a plurality of bit lines BL0, BL1, and BL2, and the common source line CSL and bit lines BL0. , BL1, and BL2) may include a plurality of cell strings CSTR.

The bit lines BL0 , BL1 , and BL2 may be two-dimensionally arranged while being spaced apart from each other along the first direction D1 while extending in the second direction D2 . Here, each of the first direction D1 , the second direction D2 , and the third direction D3 are orthogonal to each other and may form a rectangular coordinate system defined by X, Y, and Z axes.

A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 , BL1 , and BL2 . The cell strings CSTR may be connected in common to the common source line CSL while being provided between the bit lines BL0 , BL1 , and BL2 and one common source line CSL. In this case, a plurality of common source lines CSL may be provided, and the plurality of common source lines CSL are spaced apart from each other along the second direction D2 while extending in the first direction D1 and have a two-dimensional can be arranged sequentially. The same voltage may be electrically applied to the plurality of common source lines CSL, but different voltages may be applied as each of the plurality of common source lines CSL is electrically independently controlled without being limited or limited thereto. have.

The cell strings CSTR may be spaced apart from each other along the second direction D2 for each bit line while extending in the third direction D3 and may be arranged. According to an embodiment, each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL and first and second strings connected in series to bit lines BL0, BL1, and BL2. Select transistors SST1 and SST2, memory cell transistors MCT connected in series while being disposed between the ground select transistor GST and the first and second string select transistors SST1 and SST2, and an erase control transistor ECT ) can be configured. Also, each of the memory cell transistors MCT may include a data storage element.

For example, each of the cell strings CSTR may include first and second string select transistors SST1 and SST2 connected in series, and the second string select transistor SST2 may include bit lines BL0 and BL1 , BL2). However, without being limited thereto, each of the cell strings CSTR may include one string select transistor. As another example, the ground select transistor GST in each of the cell strings CSTR may be composed of a plurality of MOS transistors connected in series similarly to the first and second string select transistors SST1 and SST2. .

One cell string CSTR may include a plurality of memory cell transistors MCT having different distances from the common source lines CSL. That is, the memory cell transistors MCT may be connected in series while being disposed along the third direction D3 between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT may be connected between the ground select transistor GST and the common source lines CSL. Each of the cell strings CSTR is formed between the first string select transistor SST1 and the uppermost one of the memory cell transistors MCT and between the ground select transistor GST and the lowermost one of the memory cell transistors MCT. Dummy cell transistors DMC connected to each other may be further included.

According to an embodiment, the first string select transistor SST1 may be controlled by the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select transistor SST2 may be It can be controlled by 2 string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT may be respectively controlled by a plurality of word lines WL0 - WLn, and the dummy cell transistors DMC may be respectively controlled by a dummy word line DWL. The ground select transistor GST may be controlled by the ground select lines GSL0 , GSL1 , and GSL2 , and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erasure control transistors ECT may be provided. Common source lines CSL may be commonly connected to sources of erase control transistors ECT.

Gate electrodes of the memory cell transistors MCT, which are provided at substantially the same distance from the common source lines CSL, may be connected in common to one of the word lines WL0 - WLn and DWL to be in an equipotential state. . However, without being limited thereto, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source lines CSL, the gate electrodes provided in different rows or columns may be independently controlled. have.

Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) ) may extend along the first direction D1, be spaced apart from each other in the second direction D2, and be two-dimensionally arranged. ground selection lines GSL0, GSL1, and GSL2 provided at substantially the same level from the common source lines CSL, first string selection lines SSL1-1, SSL1-2, SSL1-3, and a second string The selection lines SSL2-1, SSL2-2, and SSL2-3 may be electrically separated from each other. Also, erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. The erase control transistors ECT may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines BL0 , BL1 , and BL2 and/or the common source lines CSL during an erase operation of the memory cell array, and the string select transistor SST and/or Alternatively, gate induced leakage current may be generated in the erasure control transistors ECT.

The above-described string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line.

2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment. FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'.

Referring to FIGS. 2 and 3 , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same.

Such interlayer insulating films ILD may be formed of an insulating material for insulation between the gate electrodes EL1 , EL2 , and EL3 . In particular, each of the interlayer insulating films ILD is a metal oxide having an insulating property such that the profile of the gate electrodes EL1 , EL2 , and EL3 and the channel holes CH penetrating the interlayer insulating films ILD in a vertical direction are uniform. It can be characterized in that it is formed as. In more detail, each of the interlayer insulating films ILD is formed of the same oxide as the gate electrodes EL1 , EL2 , and EL3 formed of a metal material, so that the gate electrodes EL1 , EL2 , and EL3 and the interlayer insulating films ( Profiles of the channel holes CH penetrating the ILD in the vertical direction may be uniform.

For example, each of the interlayer insulating layers ILD may be formed of an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 . For a more specific example, the gate electrodes EL1 , EL2 , and EL3 are formed of W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), and Mo (molybdenum) as described above. , Ru (ruthenium) or Au (gold), when formed of at least one metal material, each of the interlayer insulating films (ILD) is W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), or Au (gold). When formed, each of the interlayer insulating films ILD is formed of MoOx (molybdenum oxide), which is an oxide of Mo (molybdenum).

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by partially burying a portion of each of the vertical channel structures VS in the substrate SUB, but is not limited thereto, and the vertical channel structures VS are not limited thereto. The lower surface of (VS) may be made by contacting the upper surface of the substrate (SUB). When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of two vertical channel structures VS may pass through one of the stacked structures ST. However, without being limited thereto, three or more columns of vertical channel structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. have. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. This is due to the limitation that, when the channel holes CH are etched, the widths in the first direction D1 and the second direction D2 decrease toward the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a data storage pattern DSP, a vertical channel pattern VCP, a vertical semiconductor pattern VSP, and a conductive pad PAD. In each of the vertical channel structures VS, the data storage pattern DSP may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. can have a shape. The vertical semiconductor pattern VSP may fill a space surrounded by the vertical channel pattern VCP and the conductive pad PAD.

The data storage pattern DSP covers the inner walls of each of the channel holes CH and contacts the vertical channel pattern VCP inwardly and contacts the sidewalls of the gate electrodes EL1 , EL2 , and EL3 outwardly. can Accordingly, the regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP are the second gate electrodes along with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through EL2 may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 . That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains a state of charges (eg, a polarization state of charges) in a 3D flash memory. It can act as a data repository. For example, an ONO (tunnel oxide-charge storage layer (Nitride)-blocking oxide layer) layer or a ferroelectric layer may be used as the data storage pattern DSP. Such a data storage pattern DSP may represent binary data values or multi-valued data values with changes in trapped charges or holes, or represent binary data values or multi-valued data values with changes in states of charges.

The vertical channel pattern VCP may cover an inner wall of the data storage pattern DSP. The vertical channel pattern VCP may include a first portion VCP1 and a second portion VCP2 on the first portion VCP1.

The first portion VCP1 of the vertical channel pattern VCP may be provided under each of the channel holes CH and may contact the substrate SUB. The first portion VCP1 of the vertical channel pattern VCP may be used to block, suppress, or minimize leakage current in each of the vertical channel structures VS and/or to form an epitaxial pattern. A thickness of the first portion VCP1 of the vertical channel pattern VCP may be greater than, for example, a thickness of the first gate electrode EL1. A sidewall of the first part VCP1 of the vertical channel pattern VCP may be surrounded by the data storage pattern DSP. A top surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a higher level than a top surface of the first gate electrode EL1. More specifically, the top surface of the first part VCP1 of the vertical channel pattern VCP may be positioned between the top surface of the first gate electrode EL1 and the bottom surface of the lowermost one of the second gate electrodes EL2. A lower surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a lower level than an uppermost surface of the substrate SUB (ie, a lower surface of a lowermost one of the interlayer insulating layers ILD). A portion of the first portion VCP1 of the vertical channel pattern VCP may overlap the first gate electrode EL1 in a horizontal direction. Hereinafter, the horizontal direction refers to an arbitrary direction extending on a plane parallel to the first and second directions D1 and D2.

The second portion VCP2 of the vertical channel pattern VCP may extend in the third direction D3 from the upper surface of the first portion VCP1. The second portion VCP2 of the vertical channel pattern VCP may be provided between the data storage pattern DSP and the vertical semiconductor pattern VSP, and may correspond to the second gate electrodes EL2. Accordingly, the second portion VCP2 of the vertical channel pattern VCP may form memory cells together with regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP, as described above. .

A top surface of the second part VCP2 of the vertical channel pattern VCP may be substantially coplanar with a top surface of the vertical semiconductor pattern VSP. A top surface of the second part VCP2 of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the second portion VCP2 of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP is a component that transfers charges or holes to the data storage pattern DSP, and may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

The vertical semiconductor pattern VSP may be surrounded by the second portion VCP2 of the vertical channel pattern VCP. An upper surface of the vertical semiconductor pattern VSP may contact the conductive pad PAD, and a lower surface of the vertical semiconductor pattern VSP may contact the first portion VCP1 of the vertical channel pattern VCP. The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floated from the substrate SUB.

The vertical semiconductor pattern VSP may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern VCP. More specifically, the vertical semiconductor pattern VSP may be formed of a material having excellent charge and hole mobility. For example, the vertical semiconductor pattern VSP may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with impurities of the same first conductivity type as the substrate SUB (eg, P-type impurities). That is, the vertical semiconductor pattern VSP can improve the electrical characteristics of the 3D flash memory to increase the speed of memory operation.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

Conductive pads PAD may be provided on top surfaces of the second portion VCP2 of the vertical channel pattern VCP and on top surfaces of the vertical semiconductor pattern VSP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP and an upper portion of the vertical semiconductor pattern VSP. A sidewall of the conductive pad PAD may be surrounded by the data storage pattern DSP. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is doped with an impurity different from that of the vertical semiconductor pattern VSP (more precisely, an impurity of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). It may be formed of a semiconductor material.

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP (or vertical semiconductor pattern VSP), which will be described later.

Although the vertical channel structures VS have been described as having a structure including the conductive pad PAD, it is not limited thereto and may have a structure in which the conductive pad PAD is omitted. In this case, as the conductive pad PAD is omitted from the vertical channel structures VS, the upper surfaces of each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP are the upper surfaces of each of the stacked structures ST (ie, Each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP may extend in the third direction D3 so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers ILD. Also, in this case, the bit line contact plug BLPG, which will be described later, directly contacts the vertical channel pattern VCP instead of being indirectly electrically connected to the vertical channel pattern VCP through the conductive pad PAD. can be electrically connected.

Also, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the vertical semiconductor pattern VSP may be omitted without being limited or limited thereto.

In addition, although the vertical channel pattern VCP has been described as having a structure including the first part VCP1 and the second part VCP2, it is not limited thereto and may have a structure excluding the first part VCP1. can For example, the vertical channel pattern VCP is provided between the vertical semiconductor pattern VSP and the data storage pattern DSP and extends to the substrate SUB to contact the substrate SUB. can In this case, the lower surface of the vertical channel pattern VCP may be positioned at a lower level than the uppermost surface of the substrate SUB (the lower surface of the lowermost one of the interlayer insulating films ILD), and the upper surface of the vertical channel pattern VCP may be located at a level lower than that of the upper surface of the substrate SUB. A top surface of the pattern VSP may be substantially coplanar.

An isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL and the voltage applied to the common source line CSL. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ) and the voltage applied to the common source line (CSL), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data storage pattern (DSP) of the target memory cell, thereby program operation. can be performed.

In addition, the 3D flash memory according to an embodiment is not limited or not limited to the structure described above, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), and gate electrodes EL1, EL2, and EL3 according to implementation examples. , a bit line (BL), and a common source line (CSL) may be implemented in various structures.

FIG. 4 is a cross-sectional view illustrating another implementation example of interlayer insulating films included in the 3D flash memory shown in FIG. 3, and corresponds to a cross-section of FIG. 2 taken along line A-A'.

The 3D flash memory described below with reference to FIG. 4 has all components identical to the 3D flash memory described above with reference to FIG. 3 , but is characterized in that only structures of interlayer insulating films (ILD) are different. Accordingly, only interlayer insulating films ILD having different structures will be described below.

Referring to FIG. 4 , as described above, each of the interlayer insulating layers ILD has a profile of channel holes CH penetrating the gate electrodes EL1 , EL2 , and EL3 and the interlayer insulating layers ILD in a vertical direction. The gate electrodes EL1 , EL2 , and EL3 may be uniformly formed of a metal material and the same oxide (an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 ).

However, each of the interlayer insulating films ILD shown in FIG. 4 is different from the interlayer insulating films ILD shown in FIG. 3 in that each of them has an insulation blocking film IB. That is, as the insulating barrier layer IB is embedded in the interlayer insulating layers ILD, the insulation characteristics of each of the interlayer insulating layers ILD may be improved.

Here, the insulating blocking layer IB may be formed to extend in the horizontal direction within each of the interlayer insulating layers ILD to a thickness smaller than that of each of the interlayer insulating layers ILD. A position where the insulating blocking film IB is formed on each of the interlayer insulating films ILD may be a midpoint in a vertical direction in each of the interlayer insulating films ILD. However, it is not limited or limited thereto.

In the drawings above, the insulating blocking layer IB is shown as being inherent only to each of the interlayer insulating layers ILD interposed between the second gate electrodes EL2 among the interlayer insulating layers ILD, but is not limited thereto, and all interlayer insulating layers ILD are not limited thereto. It may be inherent in each of the interlayer insulating layers ILD.

FIG. 5 is a cross-sectional view showing the structure of a 3D flash memory according to another embodiment, corresponding to a cross-section of FIG. 2 taken along line A-A'.

Referring to FIG. 5 , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same.

Such interlayer insulating films ILD may be formed of an insulating material for insulation between the gate electrodes EL1 , EL2 , and EL3 . In particular, each of the interlayer insulating films ILD is a metal oxide having an insulating property such that the profile of the gate electrodes EL1 , EL2 , and EL3 and the channel holes CH penetrating the interlayer insulating films ILD in a vertical direction are uniform. It can be characterized in that it is formed as. In more detail, each of the interlayer insulating films ILD is formed of the same oxide as the gate electrodes EL1 , EL2 , and EL3 formed of a metal material, so that the gate electrodes EL1 , EL2 , and EL3 and the interlayer insulating films ( Profiles of the channel holes CH penetrating the ILD in the vertical direction may be uniform.

For example, each of the interlayer insulating layers ILD may be formed of an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 . For a more specific example, the gate electrodes EL1 , EL2 , and EL3 are formed of W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), and Mo (molybdenum) as described above. , Ru (ruthenium) or Au (gold), when formed of at least one metal material, each of the interlayer insulating films (ILD) is W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), or Au (gold). When formed, each of the interlayer insulating films ILD is formed of MoOx (molybdenum oxide), which is an oxide of Mo (molybdenum).

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by partially burying a portion of each of the vertical channel structures VS in the substrate SUB, but is not limited thereto, and the vertical channel structures VS are not limited thereto. The lower surface of (VS) may be made by contacting the upper surface of the substrate (SUB). When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of two vertical channel structures VS may pass through one of the stacked structures ST. However, without being limited thereto, three or more columns of vertical channel structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. have. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. This is due to the limitation that, when the channel holes CH are etched, the widths in the first direction D1 and the second direction D2 decrease toward the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a data storage pattern DSP, a vertical channel pattern VCP, a back gate BG, and a conductive pad PAD. In each of the vertical channel structures VS, the data storage pattern DSP may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. can have a shape. The back gate BG may be formed to apply a voltage to the vertical channel pattern VCP while at least a portion of the back gate BG is surrounded by the vertical channel pattern VCP. Hereinafter, that the back gate BG is included in the vertical channel pattern VCP may mean a state in which at least a portion of the back gate BF is covered by the vertical channel pattern VCP, as described above.

The data storage pattern DSP covers the inner walls of each of the channel holes CH and contacts the vertical channel pattern VCP inwardly and contacts the sidewalls of the gate electrodes EL1 , EL2 , and EL3 outwardly. can Accordingly, the regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP are the second gate electrodes along with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through EL2 may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 . That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains a state of charges (eg, a polarization state of charges) in a 3D flash memory. It can act as a data repository. For example, an ONO (tunnel oxide-charge storage layer (Nitride)-blocking oxide layer) layer or a ferroelectric layer may be used as the data storage pattern DSP. Such a data storage pattern DSP may represent binary data values or multi-valued data values with changes in trapped charges or holes, or represent binary data values or multi-valued data values with changes in states of charges.

The vertical channel pattern VCP may cover an inner wall of the data storage pattern DSP and may extend in the third direction D3. The vertical channel pattern VCP may be provided between the data storage pattern DSP and the back gate BG, and may correspond to the second gate electrodes EL2. Accordingly, as described above, the vertical channel pattern VCP may constitute memory cells together with regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP.

A top surface of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP is a component that transfers charges or holes to the data storage pattern DSP, and may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

At least a portion of the back gate BG is surrounded by and contacts the vertical channel pattern VCP, and may be formed to apply a voltage to the vertical channel pattern VCP for a memory operation. To this end, the back gate BG is a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), It may be formed of a conductive material including at least one selected from Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.). In addition to the metal material described above, the back gate BG may include at least one of all metal materials that can be formed by ALD.

In this case, the back gate BG extends along the third direction D3 from a level corresponding to the first gate electrode EL1 to a level corresponding to the second gate electrode EL2 within the vertical channel pattern VCP. can be formed That is, the upper surface of the back gate BG may be positioned at a level higher than that of the uppermost one of the second gate electrodes EL2 . However, without being limited thereto, the back gate BG may extend along the third direction D3 to a level corresponding to the third gate electrode EL3 within the vertical channel pattern VCP.

Although the lower substrate contacting the lower portion of the back gate BG is omitted in the drawing, a lower substrate contacting the lower surface of the back gate BG may be included according to an implementation example. Also, according to an implementation example, the back gate BG may be formed from inside the substrate SUB or from an upper portion of the substrate SUB.

The back gate BG is included in the vertical channel pattern VCP of each of the cell strings CSTR, and the back gate BG included in the vertical channel pattern VCP of each of the cell strings CSTR is The back gate BG may be electrically connected to all of the planes formed by the first direction D1 and the second direction D2. That is, the back gate BG may be commonly connected to the cell strings CSTR. In this case, the back gate BG of each of the cell strings CSTR may be collectively controlled so that the same voltage may be applied to all of them.

However, without being limited thereto, the back gates BG included in the vertical channel patterns VCP of each of the cell strings CSTR may be electrically connected to each other along the first direction D1 of FIG. 1 . In this case, each of the back gates BG of the cell strings CSTR arranged along the second direction D2 is electrically independently controlled so that different voltages can be applied. The same voltage may be applied to the back gates BG of each of the cell strings CSTR arranged along D1 by being collectively controlled.

Also, the back gates BG included in the vertical channel patterns VCP of each of the cell strings CSTR may be electrically connected to each other along the second direction D2 of FIG. 1 . In this case, each of the back gates BG of the cell strings CSTR arranged along the first direction D1 may be electrically independently controlled so that different voltages may be applied. The same voltage may be applied to the back gates BG of each of the cell strings CSTR arranged along D2 by being collectively controlled.

Since the insulating layer INS is disposed between the back gate BG and the vertical channel pattern VCP, direct contact between the back gate BG and the vertical channel pattern VCP may be prevented. Like the interlayer insulating layers ILD, the insulating layer ILD may be formed of an insulating material such as silicon oxide.

In the above, it has been described that the back gate BG is formed in an inner hole of the vertical channel pattern VCP and is formed while being surrounded by the vertical channel pattern VCP without gaps, but is not limited or limited thereto, and the vertical channel pattern ( It may also be formed in a structure in which at least a portion is wrapped by the VCP). For example, a structure in which the back gate BG and the insulating layer INS are included in at least a portion of the vertical channel pattern VCP or a structure penetrating the vertical channel pattern VCP may be implemented.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

A conductive pad PAD may be provided on a top surface of the vertical channel pattern VCP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP. A sidewall of the conductive pad PAD may be surrounded by the data storage pattern DSP. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is a semiconductor material doped with impurities different from those of the substrate SUB (more precisely, impurities of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). can be formed as

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP, which will be described later.

An isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL, the voltage applied to the common source line CSL, and the voltage applied to the back gate BG. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ), a voltage applied to the common source line (CSL), and a voltage applied to the back gate (BG), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data of the target memory cell. A program operation can be performed by transferring to a stored pattern (DSP).

In addition, the 3D flash memory according to another embodiment is not limited or not limited to the described structure, and according to an implementation example, a vertical channel pattern (VCP), a data storage pattern (DSP), a back gate (BG), and gate electrodes ( EL1, EL2, EL3), a bit line BL, and a common source line CSL may be implemented in various structures.

FIG. 6 is a cross-sectional view illustrating another implementation example of interlayer insulating films included in the 3D flash memory shown in FIG. 5, and corresponds to a cross-section of FIG. 2 taken along line A-A'.

The 3D flash memory described below with reference to FIG. 6 has all components identical to the 3D flash memory described with reference to FIG. 5 , but is characterized in that only structures of interlayer insulating films (ILD) are different. Accordingly, only interlayer insulating films ILD having different structures will be described below.

Referring to FIG. 6 , as described above, each of the interlayer insulating films ILD has a profile of the gate electrodes EL1 , EL2 , and EL3 and channel holes CH penetrating the interlayer insulating films ILD in a vertical direction. The gate electrodes EL1 , EL2 , and EL3 may be uniformly formed of a metal material and the same oxide (an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 ).

However, each of the interlayer insulating films ILD shown in FIG. 6 is different from the interlayer insulating films ILD shown in FIG. 5 in that each of them has an insulation blocking film IB. That is, as the insulating barrier layer IB is embedded in the interlayer insulating layers ILD, the insulation characteristics of each of the interlayer insulating layers ILD may be improved.

Here, the insulating blocking layer IB may be formed to extend in the horizontal direction within each of the interlayer insulating layers ILD to a thickness smaller than that of each of the interlayer insulating layers ILD. A position where the insulating blocking film IB is formed on each of the interlayer insulating films ILD may be a midpoint in a vertical direction in each of the interlayer insulating films ILD. However, it is not limited or limited thereto.

In the drawings above, the insulating blocking layer IB is shown as being inherent only to each of the interlayer insulating layers ILD interposed between the second gate electrodes EL2 among the interlayer insulating layers ILD, but is not limited thereto, and all interlayer insulating layers ILD are not limited thereto. It may be inherent in each of the interlayer insulating layers ILD.

7 is a flow chart showing a method of manufacturing a 3D flash memory according to embodiments, and FIGS. 8A to 13 illustrate a manufacturing method performed to manufacture a 3D flash memory having the structure shown in FIGS. 3 to 4. 14A to 19 are cross-sectional views for explaining a manufacturing method performed to manufacture the 3D flash memory having the structure shown in FIGS. 5 to 6 .

Referring to FIG. 7 , a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing the above-described 3D flash memory, and is performed by an automated and mechanized manufacturing system in a horizontal direction on a substrate (SUB). preparing a semiconductor structure (SEMI-STR) including interlayer insulating films (ILD) and gate electrodes (EL1, EL2, and EL3) that are formed to extend and are alternately stacked in a vertical direction (S710); forming channel holes CH penetrating the semiconductor structure SEMI-STR in a vertical direction (third direction D3) (S720); and forming vertical channel structures VS extending in the vertical direction (third direction D3) inside the channel holes CH. In particular, step S710 may be characterized by preparing a semiconductor structure SEMI-STR including interlayer insulating films ILD each formed of metal oxide. Also, according to an implementation example, an insulation blocking layer IB that is thinner than a thickness of each of the interlayer insulating layers ILD may be embedded in each of the interlayer insulating layers ILD included in the semiconductor structure SEMI-STR.

Hereinafter, steps S710 to S730 of FIG. 7 will be described in detail with reference to FIGS. 8A to 13 in relation to a method of manufacturing a 3D flash memory having the structure shown in FIGS. 3 to 4 .

Referring to FIGS. 8A and 8B , in step S710, the manufacturing system extends in the horizontal direction on the substrate SUB and alternately stacks interlayer insulating films ILD and gate electrodes EL1 and EL2 in the vertical direction. , EL3) may be prepared. In the semiconductor structure SEMI-STR, the interlayer insulating layers ILD and the gate electrodes EL1 , EL2 , and EL3 may be formed by, for example, a chemical vapor deposition method. However, the lowermost of the gate electrodes EL1 , EL2 , and EL3 and the lowermost of the interlayer insulating films ILD positioned between the substrate SUB may be formed through a thermal oxidation process after the deposition process.

In the semiconductor structure SEMI-STR, each of the interlayer insulating films ILD is insulated so that the profile of the gate electrodes EL1 , EL2 , and EL3 and the channel holes CH penetrating the interlayer insulating films ILD in the vertical direction are uniform. It may be characterized in that it is formed of a metal oxide having characteristics. In more detail, each of the interlayer insulating films ILD is formed of the same oxide as the gate electrodes EL1 , EL2 , and EL3 formed of a metal material, so that the gate electrodes EL1 , EL2 , and EL3 and the interlayer insulating films ( Profiles of the channel holes CH penetrating the ILD in the vertical direction may be uniform.

For example, each of the interlayer insulating layers ILD may be formed of an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 . For a more specific example, the gate electrodes EL1 , EL2 , and EL3 are formed of W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), and Mo (molybdenum) as described above. , Ru (ruthenium) or Au (gold), when formed of at least one metal material, each of the interlayer insulating films (ILD) is W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), or Au (gold). When formed, each of the interlayer insulating films ILD is formed of MoOx (molybdenum oxide), which is an oxide of Mo (molybdenum).

In addition, each of the interlayer insulating layers ILD included in the semiconductor structure SEMI-STR may have an insulating blocking layer IB, as shown in FIG. 8B . The insulating blocking layer IB is to improve the insulating characteristics of each of the interlayer insulating layers ILD, and is formed to extend in the horizontal direction within each of the interlayer insulating layers ILD with a thickness smaller than that of each of the interlayer insulating layers ILD. can

Hereinafter, a manufacturing method using a semiconductor structure SEMI-STR including interlayer insulating films ILD in which an insulating blocking film IB is embedded will be described. A manufacturing method using a semiconductor structure (SEMI-STR) including interlayer insulating layers (ILD) in which an insulating blocking layer (IB) is not embedded may also be performed in the same manner.

Referring to FIG. 9 , in operation S720 , the manufacturing system may form channel holes CH penetrating the semiconductor structure SEMI-STR in a vertical direction (eg, the third direction D3 ). The channel holes CH may be arranged in a zigzag shape while forming a plurality of columns on a plane formed by the first direction D1 and the second direction D2, recess a portion of the substrate SUB, and (SUB) can be exposed. The channel holes CH may expose sidewalls of the interlayer insulating layers ILD and the gate electrodes EL1 , EL2 , and EL3 .

In the manufacturing system, the step of forming channel holes (CH) (S720) includes a first step of forming a mask pattern (MASK) on the semiconductor structure (SEMI-STR); and a second step of performing an anisotropic etching process using the mask pattern MASK as an etching mask. However, this is only an example and various visual processes may be used in step S720.

Referring to FIGS. 10A to 10E , in step S730, the manufacturing system may form vertical channel structures VS extending in the vertical direction (eg, in the third direction D3) inside the channel holes CH. . At this time, the manufacturing system extends and forms the vertical channel structure VS (S730) in the vertical direction (S730) to cover the inner walls of each of the channel holes (CH) in the vertical direction ( For example, a first step of forming an extension in the third direction (D3)); As shown in FIG. 10B, a second step of forming a vertical channel pattern (VCP) extending in a vertical direction (eg, a third direction D3) covering a portion of a sidewall of the data storage pattern (DSP); A third step of forming a vertical semiconductor pattern VSP filling a space surrounded by the vertical channel pattern VCP as shown in FIG. 10C; and conductive pads PAD filling a space surrounded by a portion of a sidewall of the data storage pattern DSP, an upper surface of the vertical channel pattern VCP, and an upper surface of the vertical semiconductor pattern VSP, as shown in FIGS. 10D to 10E. It may include a fourth step of doing.

In more detail, the second step of extending and forming the vertical channel pattern VCP includes forming the first portion VCP1 covering the lower sidewall of the data storage pattern DSP and contacting the substrate SUB. step; and a 2-2 step of forming a second portion VCP2 covering the upper sidewall of the data storage pattern DSP on the first portion VCP1.

Since materials forming each of the data storage pattern DSP, vertical channel pattern VCP, vertical semiconductor pattern VSP, and conductive pad PAD have been described with reference to FIGS. 3 and 4, a detailed description thereof will be omitted. do.

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the third step of forming the vertical semiconductor pattern VSP, the data storage pattern DSP, Each of the channel pattern VCP and the vertical semiconductor pattern VSP may be formed by a chemical vapor deposition method or an atomic layer deposition method.

In the manufacturing system, the fourth step of forming the conductive pad PAD is a step 4-1 of recessing the top of the vertical channel pattern VCP and the top of the vertical semiconductor pattern VSP as shown in FIG. 10D and FIG. As shown in 10e, it may be subdivided into a 4-2 step of filling the recessed region with a doped semiconductor material or a conductive material.

Although not shown as a separate step, referring to FIG. 11 , the manufacturing system penetrates the semiconductor structure SEMI-STR in a vertical direction (eg, the third direction D3) and in one direction (eg, the first direction D1). ) may form a line-shaped isolation trench TR.

The isolation trench TR may be spaced apart from the vertical channel structures VS in a horizontal direction (eg, in the second direction D2 ). The isolation trench TR may recess a portion of the substrate SUB and may expose an upper surface of the substrate SUB. In addition, the separation trench TR may expose sidewalls of the interlayer insulating layers ILD and the gate electrodes EL1 , EL2 , and EL3 .

The manufacturing system includes forming the isolation trench TR in a first step of forming a mask pattern MASK on the semiconductor structure SEMI-STR; and a second step of patterning the semiconductor structure SEMI-STR using the mask pattern MASK as an etch mask. However, this is only an example, and various etching processes or patterning processes may be used to form the isolation trench TR.

Although not shown as a separate step, referring to FIG. 12 , the manufacturing system may form a common source region CSR in the substrate SUB exposed through the isolation trench TR. The common source region CSR is formed by doping an impurity having a conductivity different from that of the substrate SUB on the upper surface of the substrate SUB exposed by the isolation trench TR, so that the substrate ( SUB) can be formed in.

Although not shown as a separate step, referring to FIG. 13 , the manufacturing system includes an insulation spacer (SP) covering the sidewall of the isolation trench (TR) and filling the inner space of the isolation trench (TR) surrounded by the insulation spacer (SP). A common source plug (CSP) may be formed.

In more detail, the insulating spacers SP may be formed by depositing a spacer film on the substrate SUB and the stacked structures ST; and a second step of exposing the common source region CSR through an etch-back process or the like. A common source plug (CSP) may be formed after the first step and the second step.

In addition, although not shown as a separate step, referring to FIG. 13 , the manufacturing system forms a capping insulating layer CAP on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. can do. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP.

Subsequently, the manufacturing system may form a bit line contact plug BLPG electrically connected to the conductive pad PAD by penetrating the capping insulating layer CAP. Next, the manufacturing system may form a bit line BL electrically connected to the bit line contact plug BLPG on the capping insulating layer CAP to extend along the second direction D2 .

Hereinafter, steps S710 to S730 of FIG. 7 will be described in detail with reference to FIGS. 14A to 20 in relation to a method of manufacturing a 3D flash memory having the structure shown in FIGS. 5 to 6 .

Referring to FIGS. 14A and 14B , in step S710, the manufacturing system extends in the horizontal direction on the substrate SUB and alternately stacks interlayer insulating films ILD and gate electrodes EL1 and EL2 in the vertical direction. , EL3) may be prepared. In the semiconductor structure SEMI-STR, the interlayer insulating layers ILD and the gate electrodes EL1 , EL2 , and EL3 may be formed by, for example, a chemical vapor deposition method. However, the lowermost of the gate electrodes EL1 , EL2 , and EL3 and the lowermost of the interlayer insulating films ILD positioned between the substrate SUB may be formed through a thermal oxidation process after the deposition process.

In the semiconductor structure SEMI-STR, each of the interlayer insulating films ILD is insulated so that the profile of the gate electrodes EL1 , EL2 , and EL3 and the channel holes CH penetrating the interlayer insulating films ILD in the vertical direction are uniform. It may be characterized in that it is formed of a metal oxide having characteristics. In more detail, each of the interlayer insulating films ILD is formed of the same oxide as the gate electrodes EL1 , EL2 , and EL3 formed of a metal material, so that the gate electrodes EL1 , EL2 , and EL3 and the interlayer insulating films ( Profiles of the channel holes CH penetrating the ILD in the vertical direction may be uniform.

For example, each of the interlayer insulating layers ILD may be formed of an oxide of a metal material constituting each of the gate electrodes EL1 , EL2 , and EL3 . For a more specific example, the gate electrodes EL1 , EL2 , and EL3 are formed of W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), and Mo (molybdenum) as described above. , Ru (ruthenium) or Au (gold), when formed of at least one metal material, each of the interlayer insulating films (ILD) is W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), or Au (gold). When formed, each of the interlayer insulating films ILD is formed of MoOx (molybdenum oxide), which is an oxide of Mo (molybdenum).

In addition, each of the interlayer insulating layers ILD included in the semiconductor structure SEMI-STR may have an insulating blocking layer IB, as shown in FIG. 14B. The insulating blocking layer IB is to improve the insulating characteristics of each of the interlayer insulating layers ILD, and is formed to extend in the horizontal direction within each of the interlayer insulating layers ILD with a thickness smaller than that of each of the interlayer insulating layers ILD. can

Hereinafter, a manufacturing method using a semiconductor structure SEMI-STR including interlayer insulating films ILD in which an insulating blocking film IB is embedded will be described. A manufacturing method using a semiconductor structure (SEMI-STR) including interlayer insulating layers (ILD) in which an insulating blocking layer (IB) is not embedded may also be performed in the same manner.

Referring to FIG. 15 , in operation S720 , the manufacturing system may form channel holes CH penetrating the semiconductor structure SEMI-STR in a vertical direction (eg, the third direction D3 ). The channel holes CH may be arranged in a zigzag shape while forming a plurality of columns on a plane formed by the first direction D1 and the second direction D2, recess a portion of the substrate SUB, and (SUB) can be exposed. The channel holes CH may expose sidewalls of the interlayer insulating layers ILD and the gate electrodes EL1 , EL2 , and EL3 .

In the manufacturing system, the step of forming channel holes (CH) (S720) includes a first step of forming a mask pattern (MASK) on the semiconductor structure (SEMI-STR); and a second step of performing an anisotropic etching process using the mask pattern MASK as an etching mask. However, this is only an example and various visual processes may be used in step S720.

Referring to FIGS. 16A to 16K , in step S730, the manufacturing system may form vertical channel structures VS extending in the vertical direction (eg, in the third direction D3) inside the channel holes CH. . At this time, the manufacturing system extends and forms the vertical channel structure VS (S730) in the vertical direction (S730) to cover the inner walls of each of the channel holes (CH) in the vertical direction ( For example, a first step of forming an extension in the third direction (D3)); As shown in FIG. 16B, a second step of extending and forming the vertical channel pattern VCP covering a portion of the sidewall of the data storage pattern DSP in a vertical direction (eg, a third direction D3); A third step of extending and forming the inner hole of the vertical channel pattern VCP to the bottom of the substrate SUB in the vertical direction as shown in FIG. 16c; As shown in FIG. 16D, a fourth step of extending and forming the insulating film INS in the vertical direction (eg, the third direction D3) in the inner hole of the vertical channel pattern VCP; 16E to 16I, a fifth step of extending and forming a back gate BG in an inner hole of the insulating film INS in a vertical direction (eg, a third direction D3); and a sixth step of forming a conductive pad (PAD) filling a space surrounded by a portion of a sidewall of the data storage pattern (DSP) and an upper surface of the vertical channel pattern (VCP) as shown in FIGS. 16J to 16K. .

Materials forming the data storage pattern (DSP), vertical channel pattern (VCP), vertical semiconductor pattern (VSP), insulating film (INS), back gate (BG), and conductive pad (PAD), respectively, are described with reference to FIGS. 5 and 6 . Since it has been described, a detailed description thereof will be omitted.

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the fourth step of forming the insulating film INS, the data storage pattern DSP and the vertical channel pattern Each of the (VCP) and the insulating film (INS) may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The manufacturing system includes a fifth step of extending and forming the back gate BG, a 5-1 step of filling the internal hole of the insulating film INS with a conductive material as shown in FIG. 16E, and an insulating film (as shown in FIG. 16F). INS) and upper portions of the back gate BG are recessed, and as shown in FIG. 16G, a 5-3 step of filling the recessed region with the insulating film INS, as shown in FIG. 16H. Similarly, a 5-4 step of recessing the upper portion of the insulating layer INS and a 5-5 step of filling the vertical channel pattern VCP in the recessed region as shown in FIG. 16i may be subdivided and performed.

In addition, the manufacturing system includes the sixth step of forming the conductive pad PAD, the 6-1 step of recessing the top of the vertical channel pattern VCP as shown in FIG. The process may be subdivided into a 6-2 step of filling the doped semiconductor material or conductive material in the etched region.

Although not shown as a separate step, referring to FIG. 17 , the manufacturing system penetrates the semiconductor structure SEMI-STR in a vertical direction (eg, the third direction D3) and in one direction (eg, the first direction D1). ) may form a line-shaped isolation trench TR.

The isolation trench TR may be spaced apart from the vertical channel structures VS in a horizontal direction (eg, in the second direction D2 ). The isolation trench TR may recess a portion of the substrate SUB and may expose an upper surface of the substrate SUB. In addition, the separation trench TR may expose sidewalls of the interlayer insulating layers ILD and the gate electrodes EL1 , EL2M EL3 .

The manufacturing system includes forming the isolation trench TR in a first step of forming a mask pattern MASK on the semiconductor structure SEMI-STR; and a second step of patterning the semiconductor structure SEMI-STR using the mask pattern MASK as an etch mask. However, this is only an example, and various etching processes or patterning processes may be used to form the isolation trench TR.

Although not shown as a separate step, referring to FIG. 18 , the manufacturing system may form a common source region CSR in the substrate SUB exposed through the isolation trench TR. The common source region CSR is formed by doping an impurity having a conductivity different from that of the substrate SUB on the upper surface of the substrate SUB exposed by the isolation trench TR, so that the substrate ( SUB) can be formed in.

Although not shown as a separate step, referring to FIG. 19 , the manufacturing system includes an insulation spacer (SP) covering the sidewall of the isolation trench (TR) and filling the inner space of the isolation trench (TR) surrounded by the insulation spacer (SP). A common source plug (CSP) may be formed.

In more detail, the insulating spacers SP may be formed by depositing a spacer film on the substrate SUB and the stacked structures ST; and a second step of exposing the common source region CSR through an etch-back process or the like. A common source plug (CSP) may be formed after the first step and the second step.

In addition, although not shown as a separate step, referring to FIG. 19 , the manufacturing system forms a capping insulating layer CAP on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. can do. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP.

Subsequently, the manufacturing system may form a bit line contact plug BLPG electrically connected to the conductive pad PAD by penetrating the capping insulating layer CAP. Next, the manufacturing system may form a bit line BL electrically connected to the bit line contact plug BLPG on the capping insulating layer CAP to extend along the second direction D2 .

20 is a schematic perspective view of an electronic system including a 3D flash memory according to embodiments.

Referring to FIG. 20 , an electronic system 2000 including a 3D flash memory according to embodiments includes a main board 2001, a controller 2002 mounted on the main board 2001, and one or more semiconductor packages 2003. ) and DRAM 2004.

The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 provided on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and an external host.

The electronic system 2000 may use any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS), for example. Depending on one, you can communicate with external hosts. The electronic system 2000 may be operated by power supplied from an external host through, for example, a connector 2006 . The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the electronic system 2000 includes the DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 1103b spaced apart from each other. The first and second semiconductor packages 2003a and 1103b may be semiconductor packages each including a plurality of semiconductor chips 2020 . Each of the first and second semiconductor packages 2003a and 1103b includes a package substrate 2010, semiconductor chips 2020 on the package substrate 2010, and adhesive layers 2030 disposed on a lower surface of each of the semiconductor chips 2020. ), connection structures 2040 electrically connecting the semiconductor chips 2020 and the package substrate 2010 and a molding layer 2050 covering the semiconductor chips 2020 and the connection structures 2040 on the package substrate 2010 can include

The package substrate 2010 may be a printed circuit board including package upper pads 2011 . Each of the semiconductor chips 2020 may include input/output pads 2021 . Each of the semiconductor chips 2020 may include the 3D flash memory described above with reference to FIGS. 1 to 6 . More specifically, each of the semiconductor chips 2020 may include gate stack structures 2022 and memory channel structures 2023 . The gate stack structures 2022 may correspond to the above-described stack structures ST, and the memory channel structures 2023 may correspond to the above-described vertical channel structures VS.

The connection structures 2040 may be, for example, bonding wires electrically connecting the input/output pads 2021 and the package upper pads 2011 . Accordingly, in each of the first and second semiconductor packages 2003a and 1103b, the semiconductor chips 2020 may be electrically connected to each other using a bonding wire method, and the package upper pads 2011 of the package substrate 2010 and can be electrically connected. According to example embodiments, in each of the first and second semiconductor packages 2003a and 1103b, the semiconductor chips 2020 are provided with a through electrode (Through Silicon Via) instead of the bonding wire type connection structures 2040. may be electrically connected to each other.

Unlike shown, the controller 2002 and the semiconductor chips 2020 may be included in one package. The controller 2002 and the semiconductor chips 2020 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips 2020 may be connected to each other by wiring provided on the interposer substrate. have.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (5)

laminated structures extending in a horizontal direction on a substrate and including interlayer insulating films and gate electrodes alternately stacked in a vertical direction; and
Vertical channel structures penetrating each of the stacked structures and extending in the vertical direction - each of the vertical channel structures covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern, and the vertical channel structures extend in the vertical direction. and a vertical channel pattern extending in a direction, wherein the data storage pattern and the vertical channel pattern configure memory cells corresponding to the word lines-
including,
Each of the interlayer insulating films,
A three-dimensional flash memory characterized in that it is formed of metal oxide. According to claim 1,
Each of the interlayer insulating films,
A three-dimensional flash memory, characterized in that formed of an oxide of a metal material constituting the gate electrodes. According to claim 1,
In each of the interlayer insulating films,
A three-dimensional flash memory, characterized in that an insulating barrier film that is thinner than the thickness of each of the interlayer insulating films is embedded. preparing a semiconductor structure including interlayer insulating films and gate electrodes that are alternately stacked along a vertical direction while extending in a horizontal direction on a substrate;
forming channel holes penetrating the semiconductor structure in the vertical direction; and
forming vertical channel structures extending in the vertical direction inside the channel holes;
including,
Each of the interlayer insulating films,
A method of manufacturing a three-dimensional flash memory, characterized in that it is formed of metal oxide. According to claim 4,
In each of the interlayer insulating films,
A method of manufacturing a three-dimensional flash memory, characterized in that an insulating barrier film that is thinner than the thickness of each of the interlayer insulating films is embedded.

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