KR20220093983A - Storage device adjusting data rate and storage system including the same - Google Patents

Abstract

A method of operating a storage device according to the technical spirit of the present disclosure includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin, and receiving a response to the change request transmitting a second bit sequence including a second bit sequence to the host according to the first data rate through an output signal pin, and changing the data rate to a second data rate according to whether an end bit indicating the end of the second bit sequence is output includes steps.

Description

STORAGE DEVICE ADJUSTING DATA RATE AND STORAGE SYSTEM INCLUDING THE SAME

The technical idea of the present disclosure relates to a storage device, and more particularly, to a storage device for adjusting a data transfer rate and a storage system including the same.

A storage system consists of a host and a storage device. The host and the storage device are connected through various standard interfaces such as universal flash storage (UFS), serial ATA (SATA), small computer small interface (SCSI), serial attached SCSI (SAS), and embedded MMC (eMMC). When a storage system is used in a mobile device, high-speed operation between the host and the storage device is very important, and a rapid change in data transfer rate may be required.

SUMMARY The present disclosure provides a storage device capable of adjusting a data transfer rate while maintaining a high-speed mode, a method of operating the storage device, and a storage system including the storage device.

In order to achieve the above object, in a method of operating a storage device according to an aspect of the present disclosure, a first bit sequence including a data rate change request is received from a host according to the first data rate through an input signal pin transmitting a second bit sequence including a response to the change request to the host according to the first data rate through an output signal pin, and data according to whether an end bit indicating the end of the second bit sequence is output and changing the data rate to a second data rate.

According to another aspect of the present disclosure, a method of operating a storage system includes: transmitting, by a host, a first bit sequence including a data transfer rate change request to a storage device according to a first data transfer rate, by the storage device, to the host transmitting a second bit sequence including a response corresponding to a change request according to the first data rate, and based on an end bit indicating the end of the second bit sequence, the host and the storage device changing the data rate; includes

A storage device according to another aspect of the present disclosure includes a non-volatile memory in which data received from a host is stored, a device controller controlling the non-volatile memory, and an interconnect unit connected to the host through a plurality of pins, wherein the interconnect unit includes: Receive a first bit sequence including a request for changing the data rate according to the first data rate, transmit a second bit sequence including a response to the change request to the host according to the first data rate, and the second bit The data rate is changed to the second data rate according to whether the end bit indicating the end of the sequence is output.

According to the spirit of the present disclosure, the storage device may change the data transfer rate quickly by changing the data transfer rate while maintaining the high-speed mode.

In addition, according to the spirit of the present disclosure, since a receiver and a transmitter are driven using one clock generator, a chip size can be reduced.

1 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.
2 illustrates an interface between a host and a storage device according to an embodiment of the present disclosure.
3 is a block diagram illustrating a clock generator according to an exemplary embodiment of the present disclosure.
4 is a flowchart illustrating a link startup operation and a power mode change operation between a host and a storage device according to an exemplary embodiment of the present disclosure.
5 is a diagram for explaining adjustment of a data rate according to an embodiment of the present disclosure.
6 is a flowchart illustrating a method of operating a host according to an exemplary embodiment of the present disclosure.
7 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
8 is a diagram for explaining a data rate reset operation according to an exemplary embodiment of the present disclosure.
9 is a diagram for explaining adjustment of a data rate according to an exemplary embodiment of the present disclosure.
10 is a diagram for explaining adjustment of a data rate according to an exemplary embodiment of the present disclosure.
11 is a flowchart illustrating a method of operating a host according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure.
13 is a diagram for explaining the UFS system 1000 according to an embodiment of the present invention.
14A to 14C are diagrams for explaining a form factor of a UFS card.
15 is a block diagram illustrating a memory system 3000 according to an embodiment of the present disclosure.
16 is a diagram for explaining a 3D VNAND structure applicable to a UFS device according to an embodiment of the present invention.
17 is a diagram for explaining a B-VNAND structure applicable to a UFS device according to an embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a storage system according to an embodiment of the present disclosure. Referring to FIG. 1 , a storage system 10 includes a storage device 100 and a host 200 . For example, the storage device 100 and the host 200 may be connected according to an interface protocol defined in a UFS (Universal Flash Storage) standard, and accordingly, the storage device 100 may be a UFS device, and , the host 200 may be a UFS host. However, the present invention is not limited thereto, and the storage device 100 and the host 200 may be connected according to various standard interfaces.

The host 200 may include an interconnect unit 210 and a host controller 220 . The host 200 may control a data processing operation for the storage device 100 , for example, a data read operation or a data write operation. The host 200 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host 200 may execute an operating system (OS) and/or various applications. In an embodiment, the storage system 10 may be included in a mobile device, and the host 200 may be implemented as an application processor (AP). In an embodiment, the host 200 may be implemented as a system-on-a-chip (SoC), and accordingly, may be embedded in an electronic device.

The storage device 100 may include an interconnect unit 110 , a device controller 120 , and a nonvolatile memory 130 . The device controller 120 controls the nonvolatile memory 130 to write data to the nonvolatile memory 130 in response to a write request from the host 200 , or in response to a read request from the host 200 . The nonvolatile memory 130 may be controlled to read data stored in the nonvolatile memory 130 . The nonvolatile memory 130 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. In an embodiment, the plurality of memory cells may be NAND flash memory cells. However, the present invention is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

In addition, although the interconnect unit 110 and the device controller 120 are illustrated as having separate configurations in FIG. 1 , the device controller 120 may be a concept including the interconnect unit 110, and such a point is The same applies to other drawings that will be described later in addition to FIG. 1 . For example, when the device controller 120 is implemented as a single package chip, the interconnect unit 110 may also be implemented in the package chip.

The host 200 may include a first pin P1a, and the storage device 100 may include a first pin P1a' configured to be connected to the first pin P1a. The first pins P1a and P1a' may be referred to as clock signal pins. The storage device 100 may receive the reference clock signal REF_CLK from the host 200 through the first pin P1a ′.

The host 200 may include second pins P2a and P2b, and the storage device 100 includes second pins P2a' and P2b' configured to be respectively connected to the second pins P2a and P2b. can do. The storage device 100 may receive an input signal, eg, differential input signals DIN_t and DIN_c, from the host 200 through the second pins P2a' and P2b'. Accordingly, the second pins P2a' and P2b' may be referred to as "input signal pins", and signal lines through which the differential input signals DIN_t and DIN_c are transmitted may constitute a reception lane. For example, the second pin P2a' may be referred to as a "positive input signal pin", and the second pin P2b' may be referred to as a "negative input signal pin".

Also, the host 200 may further include third pins P3a and P3b, and the storage device 100 includes third pins P3a' and P3b' configured to be respectively connected to the third pins P3a and P3b. ) may be further included. The storage device 100 may transmit an output signal, for example, the differential output signals DOUT_t and DOUT_c, to the host 200 through the third pins P3a' and P3b'. Accordingly, the third pins P3a' and P3b' may be referred to as "output signal pins", and signal lines to which the differential output signals DOUT_t and DOUT_c are transmitted may constitute a transmission lane. For example, the third pin P3a' may be referred to as a "positive output signal pin", and the third pin P2b' may be referred to as a "negative output signal pin".

The host 200 may include a clock generator 213 . The clock generator 213 may generate a reference clock signal REF_CLK and generate an internal clock signal used for data transmission based on the reference clock signal REF_CLK. The clock generator 213 may adjust the data rate by changing the frequency of the reference clock signal or the internal clock signal. The clock generator 213 may be described in detail later with reference to FIG. 3 .

The host 200 may further include a tail-of-burst (TOB) detector 221 . In FIG. 1 , the end bit detector 221 is illustrated as being included in the host controller 220 , but the present invention is not limited thereto, and the end bit detector 221 may be included in the interconnect unit 210 . The end bit detector 221 may detect the end bit of the bit sequence received through the third pins P3a and P3b. A bit sequence may be referred to as a burst, and the end bit may be referred to as a Tail-Of-Burst (TOB). The host controller 220 may transmit a request to change the power mode to the storage device 100 . The request for power mode change may be referred to as a power mode change request (PWR_req). The power mode may include a high-speed mode and a low-speed mode, and a plurality of data rates may be set in the high-speed mode and the low-speed mode. The host controller 220 may request not only to change between the high-speed mode and the low-speed mode but also to change the data rate through the power mode change request PWR_req. The host controller 220 may receive a response to the power mode change from the storage device 100 . The response to the power mode change may be referred to as a power mode change response (PWR_cnf). When the end bit of the burst including the power mode change response PWR_cnf is received, the host controller 220 may control the clock generator 213 to adjust the data rate. The end bit of the burst including the power mode change response PWR_cnf may be detected by the end bit detector 221 .

The storage device 100 may include a clock generator 113 . The clock generator 113 may generate an internal clock signal used for data transmission based on the reference clock signal REF_CLK received through the clock signal pin P1a'. The clock generator 113 may adjust the data rate by changing the frequency of the internal clock signal. The clock generator 113 may be described later in detail with reference to FIG. 3 .

The storage device 100 may further include a tail-of-burst (TOB) detector 121 . In FIG. 1 , the end bit detector 121 is illustrated as being included in the device controller 120 , but the present invention is not limited thereto, and the end bit detector 121 may be included in the interconnect unit 110 . The end bit detector 121 may detect the end bit of the burst received through the second pins P2a' and P2b'. When the end bit of the burst including the power mode change request (PWR_req) is detected by the TOB detector 121, the interconnect unit 110 transmits the end bit of the burst including the power mode change response (PWR_cnf) to the third pins ( P3a', P3b'). When the end bit of the burst including the power mode change response PWR_cnf is transmitted, the interconnect unit 110 may control the clock generator 113 to adjust the data rate.

The interconnect units 110 and 210 may provide an interface for exchanging data between the host 200 and the storage device 100 . In an embodiment, the interconnect unit 110 may include a physical layer (PL) 111 and a link layer (LL) 112 , and the physical layer 111 includes first to second It may be connected to the 3 pins P1a', P2a', P2b', P3a', and P3b'. Similarly, the interconnect unit 210 may also include a physical layer 211 and a link layer 212 , and the physical layer 211 is to be connected to the first to third pins P1a, P2a, P2b, P3a, and P3b. can Each of the physical layers 111 and 211 may include physical components for exchanging data between the host 200 and the storage device 100 , for example, at least one transmitter and at least one receiver. (receiver) and the like. The host transmitter HOST TX may be configured to include second pins P2a and P2b, and the host receiver HOST RX may be configured to include third pins P3a and P3b. The device transmitter DEVICE TX may be configured to include third pins P3a' and P3b', and the device receiver DEVICE RX may be configured to include second pins P2a' and P2b'. Each of the link layers 112 and 212 may manage data transmission and composition, and may manage data integrity and error.

The transmitter TX and the receiver RX may receive a reference clock signal from the clock generators 213 and 113 and transmit/receive data according to the reference clock signal. The host 200 according to an exemplary embodiment of the present disclosure may prevent a situation in which an error occurs in the data being transmitted by adjusting the data rate after the end bit of the burst is received from the storage device 100 . In addition, since the host 200 according to an exemplary embodiment of the present disclosure can drive the host transmitter (HOST TX) and the host receiver (HOST RX) using one clock generator 213, clocks for each transmitter/receiver The size of the storage system 10 may be reduced compared to a case in which the generator is provided.

The storage device 100 according to an exemplary embodiment of the present disclosure may prevent an error in data being transmitted by adjusting the data transfer rate after outputting the burst end bit to the host 200 . In addition, since the storage device 100 according to an exemplary embodiment of the present disclosure may drive the device transmitter (DEVICE TX) and the device receiver (DEVICE RX) using one clock generator 113, each transmitter/receiver Compared to a case in which the clock generator is provided, the size of the storage system 10 may be reduced.

In one embodiment, where storage system 10 is a mobile device, link layers 112 and 212 may be defined by the "UniPro" specification, and physical layers 111 and 211 may be defined as "M-PHY". It can be defined by the specification. UniPro and M-PHY are interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance. In this case, the link layers 112 and 212 may include a Physical Adapted Layer, respectively. The physical adaptation layer may control the physical layers 111 and 211, such as managing data symbols or managing power.

In some embodiments, the storage device 100 may be implemented as a DRAMless device, and the DRAMless device may refer to a device that does not include a DRAM cache. In this case, the device controller 120 may not include a DRAM controller. For example, the storage device 100 may use a partial area of the nonvolatile memory 130 as a buffer memory.

In some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be an embedded UFS memory device, an embedded Multi-Media Card (eMMC), or a solid state drive (SSD). However, the present invention is not limited thereto, and the storage device 100 includes a non-volatile memory (eg, One Time Programmable ROM (OTPROM), Programmable ROM (PROM), Erasable and Programmable ROM (EPROM), and Electrically Erasable ROM (EEPROM)). and Programmable ROM), Mask ROM, Flash ROM, etc.). In some embodiments, the storage device 100 may be an external memory that is detachable from the electronic device. For example, the storage device 100 may include a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital) and It may include at least one of "Memory Stick".

The storage system 10 is, for example, a personal computer (PC), a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA). ), digital still camera, digital video camera, audio device, PMP (portable multimedia player), PND (personal navigation device or portable navigation device), MP3 player, portable game It may be implemented as an electronic device such as a handheld game console or an e-book. Also, the storage system 10 may be implemented as various types of electronic devices, such as a wrist watch or a wearable device such as a head-mounted display (HMD).

Hereinafter, an interface between the host 200 and the storage device 100 will be described in detail with reference to FIG. 2 .

2 illustrates an interface 20 between a host and a storage device according to an embodiment of the present disclosure.

Referring to FIG. 2 , the interface 20 may include a link 300 between the host controller 220 and the device controller 120 , and the link 300 includes a plurality of lanes ( 310, 320, 330) may be included. The link 300 may include at least one lane corresponding to each direction, and the number of lanes in each direction need not be symmetrical. For example, the link 300 includes two lanes 310 and 320 corresponding to a first direction from the host controller 220 to the device controller 120 and a second direction from the device controller 120 to the host controller 220 . One lane 330 corresponding to two directions may be included, but the present invention is not limited thereto. For example, two lanes 310 and 320 corresponding to the first direction may constitute a first sub-link, and one lane 330 corresponding to the second direction may constitute a second sub-link. .

The interface 20 may support a plurality of lanes. Each of the lanes 310 , 320 , and 330 is a unidirectional, single-signal, and a transmission channel carrying information. For example, the lane 320 may include a transmitter TX1 , a receiver RX1 , and a line LINE for point-to-point interconnection between the transmitter TX1 and the receiver RX1 . For example, the transmitter TX1 may be connected to a pin TXDP corresponding to a positive node of the differential signal and a pin TXDN corresponding to a negative node of the differential signal, and the receiver RX1 may be connected to a positive node of the differential signal. It may be connected to a corresponding pin RXDP and a pin RXDN corresponding to a negative node of the differential signal. Line LINE consists of two differentially routed wires connecting the pins TXDP and RXDP, TXDN and RXDN of transmitter TX1 and receiver RX1, these wires can correspond to transmission lines have.

The link 300 may further include lane managers 340 and 350 that provide a bidirectional data transmission function. Although FIG. 2 illustrates that the lane manager 350 and the host controller 220 are separated, the present invention is not limited thereto, and the lane manager 350 may be included in the host controller 220 . Similarly, although FIG. 2 illustrates that the lane manager 340 and the device controller 120 are separated, the present invention is not limited thereto, and the lane manager 340 may be included in the device controller 120 .

1 and 2 together, the transmitter included in the interconnect unit 210 of the host 200 and the receiver included in the interconnect unit 110 of the storage device 100 form one lane. However, the number of transmitters and receivers included in the interconnect unit 210 of the host 200 may be different from the number of transmitters and receivers included in the interconnect unit 110 of the storage device 100 . Also, the capability of the host 200 may be different from that of the storage device 100 . Accordingly, the host 200 and the storage device 100 recognize a physically connected lane and perform a process for receiving information from the counterpart device. Accordingly, the host 200 and the storage device 100 perform link startup processing before exchanging data. By performing link start-up processing, the host 200 and the storage device 100 exchange and recognize information on the number of transmitters and receivers, information on physically connected lanes, information on the performance of the counterpart device, etc. can After the link start-up process is completed, the host 200 and the storage device 100 are set to a linkup state in which data can be stably exchanged with each other. The link startup process may be performed during an initialization operation performed when the storage system 10 is used for the first time or a boot operation of the storage system 10 . Furthermore, the link start-up process may be performed during an operation of recovering an error in the link-up state. Link startup may be described later in detail with reference to FIG. 4 .

3 is a block diagram illustrating a clock generator according to an exemplary embodiment of the present disclosure. The clock generator 40 may be an implementation example of the clock generator 213 or 113 of FIG. 1 . The clock generator 40 may be a phase locked loop circuit. When the clock generator 40 is an implementation example of the clock generator 113 included in the storage device 100 , the oscillator 410 generating the reference clock signal REF_CLK may be omitted, and the reference clock signal REF_CLK may be omitted. may be understood to be received from the host 200 .

The clock generator 40 may generate an internal clock signal INT_CLK based on the reference clock signal REF_CLK. The transmitter (TX) 50 and the receiver (RX) 60 may transmit/receive data in synchronization with the internal clock signal INT_CLK. Transmitter (TX) 50 and receiver (RX) 60 may be an example of the transmitter (TX) and receiver (RX) shown in FIG. 2 . The clock generator 40 includes an oscillator 410 , a phase/frequency detector 420 , a charge pump 430 , a loop filter 440 , a voltage controlled oscillator (VCO) 450 , and a divider 460 . may include

The oscillator 410 may generate the reference clock signal REF_CLK having a constant frequency regardless of variations in process, voltage, and temperature. For example, the frequency of the reference clock signal REF_CLK may be one of four values of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto.

The phase/frequency detector 420 compares the reference clock signal REF_CLK and the feedback signal received from the divider 460, and based on the comparison result, a signal representing the phase difference between the reference clock signal REF_CLK and the feedback signal can be printed out.

The charge pump 430 may store or discharge charges based on a signal received from the phase/frequency detector 420 . The loop filter 440 may serve to remove noise frequencies by operating as a low pass filter.

The VCO 450 may control the frequency of the internal clock signal INT_CLK based on the voltage received from the loop filter 440 . For example, the VCO 450 may increase the frequency of the internal clock signal INT_CLK by receiving a positive voltage. The VCO 450 may decrease the frequency of the internal clock signal INT_CLK by receiving a negative voltage.

The divider 460 may count the internal clock signal INT_CLK according to the division ratio, and may provide the counted signal to the phase/frequency detector 420 as a feedback signal. 3 illustrates one divider 460, the clock generator 400 may include a plurality of dividers having different division ratios.

As will be described later with reference to the drawings, the storage system according to an embodiment of the present disclosure may adjust the data rate by changing the frequency of the internal clock signal. In order to change the frequency of the internal clock signal, the division ratio of the divider 460 may be changed or the frequency of the reference clock signal REF_CLK may be changed.

The storage system according to an exemplary embodiment of the present disclosure drives the transmitter TX and the receiver RX using a single clock generator 40, thereby generating clock generators for the transmitter TX and the receiver RX, respectively. Compared to a case in which , the size of the host and the storage device may be reduced.

4 is a flowchart illustrating a link startup operation and a power mode change operation between a host and a storage device according to an exemplary embodiment of the present disclosure. Specifically, FIG. 4 is a flowchart illustrating a link startup step ( S360 ) and a power mode change step ( S380 ) between the host 200a and the storage device 100a . When the link start-up step S360 is performed, in step S370 , the host 200a and the storage device 100a may operate in a link-up state.

The link startup phase S360 is a multi-phase handshake, exchanging UniPro trigger events to establish initial link communication in both directions, between the host 200a and the storage device 100a. can be done in this way. The link startup phase (S360) may be defined as predetermined phases (S361 to S365), a trigger event may be used for each phase, and each trigger event may be transmitted multiple times.

Step S361 is a data lane discovery step. In step S361 , lanes connected between the host 200a and the storage device 100a may be discovered. In step S361 , the host 200a and the storage device 100a may repeatedly send a first trigger event TRG_UPR0 to all available TX Lanes. The host 200 may continue to transmit the first trigger event TRG_UPR0 until it receives the first trigger event message from the storage device 100 . The first trigger event TRG_UPR0 transmitted from the host 200a may include a physical lane number of a transmission lane of the host 200a through which the corresponding trigger is transmitted. Also, the storage device 100a may continuously transmit the first trigger event TRG_UPR0 until it receives the first trigger event message from the host 200a. The first trigger event TRG_UPR0 transmitted from the storage device 100a may include a physical lane number of a transmission lane of the storage device 100 through which the corresponding trigger is transmitted.

Step S362 is a data lane realignment step. In step S362 , the host 200a and the storage device 100a may transmit a second trigger event TRG_UPR1 to all available transmission lanes. The host 200a may continue to transmit the second trigger event TRG_UPR1 until it receives the second trigger event message from the storage device 100a. The second trigger event TRG_UPR1 transmitted from the host 200a may include information on transmission lanes connected to the host 200a. Also, the storage device 100a may continuously transmit the second trigger event TRG_UPR1 until it receives the second trigger event message from the host 200 . The second trigger event TRG_UPR1 transmitted from the storage device 100a may include information on transmission lanes connected to the storage device 100a.

Step S363 is a link startup termination step. In step S363 , the host 200a and the storage device 100a may reflect how many connected lanes there are in the properties of the physical layers 111 and 211 . In step S363 , the host 200a and the storage device 100a may transmit a third trigger event TRG_UPR2 to all available transmission lanes. The host 200a may continue to transmit the third trigger event TRG_UPR2 until it receives a message corresponding to the third trigger event TRG_UPR2 from the storage device 100a. The third trigger event TRG_UPR2 transmitted from the host 200a may include logical lane numbers for transmission lanes connected to the host 200a. Also, the storage device 100a may continuously transmit the third trigger event TRG_UPR2 until it receives a third trigger event message corresponding to the third trigger event TRG_UPR2 from the host 200a. The third trigger event TRG_UPR2 transmitted from the storage device 100a may include logical lane numbers related to transmission lanes connected to the storage device 100a. As step S363 is performed, the host 200 and the storage device 100a may have identical logical lane numbers with respect to available lanes.

Operation S364 is a capability exchange operation. In operation S364 , the host 200a and the storage device 100a may exchange performance information CAP. Specifically, the host 200a and the storage device 100a may exchange and recognize the performance information CAP of the counterpart device in order to communicate the architectural requirements of the interconnect units 210 and 110 . Architectural requirements of interconnects 210 , 110 may include, for example, bandwidth, timers, speed gear, termination/untermination, scrambling, and the like. As step S364 is performed, information on the performance of the counterpart device (CAP) is collected in the interconnects 210 and 110, and properties of the physical layers of the interconnects 210 and 110 are changed according to the collected performance information (CAP). can be set. When step S364 is performed, in step S370 , the host 200a and the storage device 100a may operate in a link-up state. In the link-up state, the host 200a and the storage device 100a may operate in a default power mode. The default power mode may be a high speed mode (HS mode) or a low speed mode (LS mode). Also, in the link-up state, the host 200a and the storage device 100a may transmit/receive data at a default data rate. In some embodiments, the default data rate may be the first data rate DR1.

Step S380 is a power mode change step. The host 200a and the storage device 100a may perform a power mode change operation, and link configuration for a new power mode may be performed. Step S380 may include a plurality of steps S381 to S384.

In step S381 , the host 200a may transmit a power mode change request PWR_req to the storage device 100 . The power mode change request (PWR_req) may include a type of power mode to be changed, a speed gear, or a speed series. The power mode may be a high speed mode (HS mode) or a low speed mode (LS mode). The speed gear may mean a data rate, and the speed series may mean a group of a plurality of speed gears. For example, the speed series can be divided into A series and B series. The A series may include four speed gears corresponding to 1.25, 2.5, 5, and 10.0 Gbps. The B series may include speed gears having a higher frequency than the speed gears included in the A series. For example, speed gears included in the B series may correspond to 1.46, 2.92, 5.83, and 11.66 Gbps higher than speed gears included in the A series.

In operation S382 , the storage device 100a may transmit a power mode change response PWR_cnf to the host 200a. The power mode change response (PWR_cnf) may include status information, type of power mode, speed gear or speed series. The state information may refer to information on whether a power mode change is possible.

For convenience of explanation, it has been described that the host 200a transmits the power mode change request (PWR_req) and the storage device 100a transmits the power mode change response (PWR_cnf), but in some embodiments, the storage device ( 100a) may transmit a power mode change request PWR_req to the host 200a, and the host 200a may transmit a power mode change response PWR_cnf to the storage device 100a. Hereinafter, it is assumed that the host 200a transmits a power mode change request (PWR_req) and the storage device 100a transmits a power mode change response (PWR_cnf).

In operation S383 , the storage device 100a may adjust the data transfer rate after transmitting the power mode change response PWR_cnf. The data rate can be adjusted by changing the frequency of the internal clock signal. An error may occur if data is transmitted over a line while the frequency of the internal clock signal is changing. Accordingly, data may not be transmitted through the line LINE during the predetermined set time Config_time, and the frequency of the internal clock signal may be changed within the set time Config_time.

In step S384 , the host 200a may adjust the data rate after receiving the power mode change response PWR_cnf. That is, a power mode change response PWR_cnf including status information indicating that a power mode change is possible may be received from the storage device 100a, and the frequency of the internal clock signal may be changed during a set time Config_time.

The storage system according to an exemplary embodiment of the present disclosure may adjust the data transfer rate by changing the frequency of the internal clock signal during a set time (Config_time) during which data is not transmitted over a line. Also, the host 200a and the storage device 100a may stably exchange data by transmitting data after the set time Config_time has elapsed.

5 is a diagram for explaining adjustment of a data rate according to an embodiment of the present disclosure. Specifically, FIG. 5 shows data transmitted through a host transmitter (HOST TX) and a device transmitter (DEVICE TX) through a line (LINE) in order to adjust a data rate. Although not shown in FIG. 5, as described above with reference to FIG. 2, the host transmitter (HOST TX) may be connected to the device receiver (DEVICE RX) through a line (LINE), and the device transmitter (DEVICE TX) is the host It can be connected to the receiver (HOST RX) through a line (LINE). Accordingly, data received through the device receiver DEVICE RX may be the same as data transmitted through the host transmitter HOST TX, but a phase difference may occur by a line delay. Data received through the host receiver (HOST RX) may be the same as data transmitted through the device transmitter (DEVICE TX), but a phase difference may occur by a line delay. 5 may be described later with reference to at least one of FIGS. 1 to 4 .

Referring to FIG. 5 , the host 200 and the storage device 100 may adjust the data transfer rate while maintaining the HS mode. In the high-speed mode (HS mode), bits transmitted through a lane are expressed through a logic level, and even if a logic high interval is continuous, there is no need to have a logic low interval between intervals (non-return to zero NRZ). ) may be a power mode to which the method is applied. In the high-speed mode (HS mode), the data rate may be determined according to the frequency of the internal clock signal generated by dividing the reference clock signal.

The data rate may be divided into a plurality of speed series A and B according to the frequency of the reference clock signal. For example, data rates determined based on a first reference clock signal having a first frequency may be referred to as an A series, and data rates determined based on a second reference clock signal having a second frequency are B series. may be referred to as Each of the plurality of series A and B may include a plurality of speed gears. By dividing the reference clock signal, internal clock signals having various frequencies may be generated, and a data rate corresponding to each internal clock signal may be referred to as a speed gear.

The host transmitter (HOST TX) or the device transmitter (DEVICE TX) may be in at least one of a power saving state or a burst state. The power saving state is a state for minimizing power consumption, and may be a state in which the line LINE is driven with a negative differential line voltage DIF-N or a zero differential line voltage DIF-Z. The power saving state may be one of a STALL state, a SLEEP state, a hibernating state HIBERN8, a DISABLED state, or an UNPOWERED state. In embodiments of the present disclosure, it is assumed that a power saving state is a STALL state. The burst state is a state in which data is transmitted to a line, and may be a state in which the line LINE is driven with a positive differential line voltage DIF-P. The burst state may include a high-speed burst (HS-BURST) state in which data is transmitted in a high-speed mode and a low-speed burst (LS-BURST) state in which data is transmitted in a low-speed mode. Line LINE may have a DIF-Q state indicating a high impedance state, or a DIF-X state that is neither DIF-N nor DIF-P. Here, the differential line voltage may be defined as a value obtained by subtracting the voltage of the line connected to the negative node from the voltage of the line connected to the positive node.

The line LINE may correspond to any line included in the interface 20 illustrated in FIG. 2 . For example, the line LINE may correspond to a differential input signal line through which the differential input signals DIN_t and DIN_c of FIG. 1 are transmitted. For example, when the voltage level of the second pin P2a' to which the positive input signal DIN_t is applied is higher than the voltage level of the second pin P2b' to which the negative input signal DIN_c is applied, the line LINE ) can be DIF-P state or logic high. For example, when the voltage level of the second pin P2a' to which the positive input signal DIN_t is applied is lower than the voltage level of the second pin P2b' to which the negative input signal DIN_c is applied, the line LINE ) can be DIF-N state or logic low. For example, when the voltage level of the second pin P2a' to which the positive input signal DIN_t is applied is substantially the same as the voltage level of the second pin P2b' to which the negative input signal DIN_c is applied, the line (LINE) may be a DIF-Z state or a ground state.

Referring to FIG. 5 , a bit sequence transmitted through a line in a burst state may be referred to as a burst (BURST). The burst BURST may include a preparation period PREPARE, a dummy period DUMMY, a power mode change request (PWR_REQ) or a power mode change response (PWR_CNF), and an end bit (TOB, Tail-Of-Burst). The PREPARE section is a section indicating the start of a burst, and may be a section in which the line is driven by the positive differential line voltage DIF-P. The DUMMY section may be a section including at least one bit representing meaningless data. The host receiver (HOST RX) and the device receiver (DEVICE RX) may ignore data included in the dummy period in the received burst. The power mode change request (PWR_req) may include information requesting to change the data rate. The power mode change response RWR_cnf may include information in response to the power mode change request PWR_req. The end bit TOB may be at least one bit indicating the end of the burst. The end bit TOB may be a bit transmitted during a period in which the line is driven with the negative differential line voltage DIF-N. The end bit (TOB) may include an MK symbol or a filler symbol described in the UniPro specification.

Referring to FIG. 5 , the host 200 may transmit a first burst BURST 1 at a first data rate DR1 through the host transmitter HOST TX in the HS mode. The first burst BURST 1 may include a power mode change request PWR_req for requesting to change the data rate to the second data rate DR2.

The storage device 100 may transmit the second burst BURST 2 at the first data rate DR1 through the device transmitter DEVICE TX in the HS mode. The second burst BURST 2 may include a power mode change response PWR_cnf corresponding to the power mode change request PWR_req.

The storage device 100 may adjust the data rate to the second data rate DR2 when the end bit TOB of the second burst BURST 2 is output through the device transmitter DEVICE TX. Specifically, when the end bit TOB is output, the clock generator 113 may adjust the data rate to the second data rate DR2 by changing the frequency of the internal clock signal. Data may not be transmitted through the line LINE connected to the device transmitter DEVICE TX during the predetermined configuration time Config_time, and the data transmission rate may be adjusted within the configuration time Config_time.

In some embodiments, the clock generator 113 may be commonly used for a device transmitter (DEVICE TX) and a device receiver (DEVICE RX). Therefore, when the frequency of the internal clock signal is changed immediately after the device receiver (DEVICE RX) receives the power mode change request (PWR_req) from the host transmitter (HOST TX), the power mode transmitted through the device transmitter (DEVICE TX) The change response (PWR_cnf) may not reach the host receiver (HOST RX). The storage device 100 according to an exemplary embodiment of the present disclosure changes the frequency of the internal clock signal after the second burst BRUST 2 is output, so that the device transmitter DEVICE TX using a common internal clock signal ) and the data rate for the device receiver (DEVICE RX) can be changed. That is, since data rates for the device transmitter (DEVICE TX) and the device receiver (DEVICE RX) can be changed using one phase locked loop (PLL) circuit, the size of the storage system can be reduced.

When the end bit TOB of the second burst BURST 2 is received through the host receiver HOST RX, the host 200 may adjust the data rate to the second data rate DR2. Although not shown, the host receiver (HOST RX) may be connected to the device transmitter (DEVICE TX) through a line. Specifically, when the end bit TOB is received, the clock generator 213 may adjust the data rate to the second data rate DR2 by changing the frequency of the internal clock signal. During the predetermined set time Config_time, data may not be transmitted through the line LINE connected to the host transmitter HOST TX, and the data transfer rate may be adjusted within the set time Config_time.

In some embodiments, the clock generator 213 may be commonly used by a host transmitter (HOST TX) and a host receiver (HOST RX). Therefore, when the frequency of the internal clock signal is changed immediately after the host transmitter (HOST TX) transmits the power mode change request (PWR_req) to the device receiver (DEVICE RX), the power mode transmitted through the device transmitter (DEVICE TX) The change response (PWR_cnf) may not reach the host receiver (HOST RX). The host 200 according to an exemplary embodiment of the present disclosure changes the frequency of the internal clock signal after the second burst BRUST 2 is received, so that the host transmitter (HOST TX) using a common internal clock signal and a data rate for the host receiver (HOST RX) may be changed. That is, since data transmission rates for the host transmitter (HOST TX) and the host receiver (HOST RX) can be changed using one phase locked loop (PLL) circuit, the size of the storage system can be reduced.

When the data rate is adjusted while maintaining the HS mode, an error may occur in the data being transmitted while the frequency of the internal clock signal is changed. Accordingly, the frequency change of the internal clock signal may be performed in the low speed mode (LS mode). The low-speed mode (LS mode) may be a transmission mode that does not use a reference clock signal. For example, the low-speed mode may be a pulse width modulation (PWM) method. In the low-speed mode of the PWM method, a return to zero (RZ) method in which a logic low section must exist between each logic high section of a signal transmitted through a lane is applied. That is, since the low speed mode (LS mode) is a transmission mode that does not use an internal clock signal, even if the frequency of the internal clock signal is adjusted in the low speed mode (LS mode), an error may not occur in transmitted data.

However, in order to change the data rate of the high-speed mode, it may take a considerable amount of time to change the power mode to the low-speed mode, to change the frequency of the internal clock signal in the low-speed mode, and to change the power mode to the high-speed mode again.

In the storage system according to an exemplary embodiment of the present disclosure, even if the data transfer rate is changed while maintaining the high-speed mode by changing the frequency of the reference clock signal for a set time during which data is not transmitted through the lane, data error will not occur. can

6 is a flowchart illustrating a method of operating a host according to an exemplary embodiment of the present disclosure. Specifically, FIG. 6 shows a method of adjusting data rates for a host transmitter (HOST TX) and a host receiver (HOST RX). The method of operating the host may include a plurality of steps ( S610 to S640 ). 6 may be described later with reference to at least one of FIGS. 1 to 5 .

In operation S610 , the host 200 may transmit the first burst BURST 1 including the power mode change request PWR_req to the storage device 100 through the host transmitter HOST TX. The first burst BURST 1 may be a bit sequence transmitted to the storage device 100 through a line while the host transmitter HOST TX maintains the burst state. The power mode change request (PWR_req) may include a type of power mode to be changed, a speed gear, or a speed series. The power mode may be a high speed mode (HS mode) or a low speed mode (LS mode). The speed gear may mean a data rate, and the speed series may mean a group of a plurality of speed gears.

In operation S620 , the host 200 may receive the second burst BURST 2 including the power mode change response PWR_cnf from the storage device 100 through the host receiver HOST RX. The second burst BURST 2 may be a bit sequence transmitted to the host 200 through a line while the device transmitter DEVICE TX maintains the burst state. The power mode change response PWR_cnf corresponds to the power mode change request PWR_req and may include status information, a type of power mode, a speed gear, or a speed series. The state information may refer to information on whether a power mode change is possible.

In step S630 , the TOB detector 221 included in the host 200 may detect the end bit TOB of the second burst BURST 2 . The TOB detector 221 may detect the end bit TOB by identifying a predetermined bit sequence. When the end bit TOB is not detected, the TOB detector 221 may perform a detection operation until the end bit TOB is detected, and when the end bit TOB is detected, step S640 is performed. can

In operation S640 , the host 200 may adjust data rates for the host transmitter (HOST TX) and the host receiver (HOST RX). Specifically, the clock generator 213 changes the frequency of the reference clock signal or the frequency of the internal clock signal generated based on the reference clock signal, thereby changing the speed gear or speed series included in the power mode change request PWR_req. You can set the data rate corresponding to . In some embodiments, in step S640 , as described above with reference to FIG. 3 , the frequency of the internal clock signal is increased by the oscillator 410 changing the frequency of the reference clock signal or the frequency divider 460 changing the division ratio. can be changed.

The host according to an exemplary embodiment of the present disclosure may determine when all bursts are received from the storage device by detecting the end bit TOB. Accordingly, it is possible to adjust the data transfer rate when data is not transmitted on the lines connected to each of the host transmitter (HOST TX) and the host receiver (HOST RX), thereby preventing errors in transmitted data that may occur while the data transfer rate is being adjusted. can

In addition, a single clock generator 213 can be used to adjust the data rate for both the host transmitter (HOST TX) and the host receiver (HOST RX), so that the host transmitter (HOST TX) and host receiver (HOST RX) The size of the storage system may be reduced as compared to the case in which the clock generator is provided for the storage system.

7 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. Specifically, FIG. 7 shows a method of adjusting data rates for a device transmitter (DEVICE TX) and a device receiver (DEVICE RX). The method of operating the storage device may include a plurality of steps ( S710 to S740 ). 7 may be described later with reference to FIGS. 1 to 5 .

In step S710 , as described above with reference to FIG. 5 , the storage device 100 transmits the first burst BURST 1 including the power mode change request PWR_req through the device receiver DEVICE RX to the host 200 . can be received from

In step S720 , as described above with reference to FIG. 5 , the storage device 100 transmits the second burst BURST 2 including the power mode change response PWR_cnf through the device transmitter DEVICE RX to the host 200 . can be sent to The power mode change response PWR_cnf corresponds to the power mode change request PWR_req and may include status information, a type of power mode, a speed gear, or a speed series. The state information may refer to information on whether a power mode change is possible.

In operation S730 , the TOB detector 121 included in the storage device 100 may detect the end bit TOB of the first burst BUST 1 . The TOB detector 121 may detect the end bit TOB by identifying a predetermined bit sequence. When the end bit TOB is not detected, the TOB detector 121 may perform a detection operation until the end bit TOB is detected, and when the end bit TOB is detected, step S740 is performed. can

In operation S740 , the storage device 100 may transmit the end bit TOB of the second burst BURST 2 through the device transmitter DEVICE TX. Data may not be transmitted on the line LINE until the set time Config_time elapses after the end bit TOB is transmitted.

In operation S750 , the storage device 100 may adjust data rates for the device transmitter DEVICE TX and the device receiver DEVICE RX. Specifically, the clock generator 113 responds to the power mode change request (PWR_req) by receiving the reference clock signal having the changed frequency from the host 200 or changing the frequency of the internal clock signal generated based on the reference clock signal. You can set the data rate corresponding to the included speed gear or speed series. In some embodiments, in step S750 , as described above with reference to FIG. 3 , the frequency of the internal clock signal is increased by the oscillator 410 changing the frequency of the reference clock signal or the frequency divider 460 changing the division ratio. can be changed. The storage device 100 may change the frequency of the internal clock signal during the configuration time Config_time.

The storage device according to an exemplary embodiment of the present disclosure may determine when all bursts are received from the host by detecting the end bit TOB. The storage device may adjust the data transfer rate when the end bit TOB is detected. That is, the storage device adjusts the data rate for a set time (Config_time) in which data is not transmitted to the lines connected to each of the device transmitter (DEVICE TX) and the device receiver (DEVICE RX), which may occur while the data rate is adjusted. Errors in transmission data can be prevented.

In addition, one clock generator 113 can be used to adjust the data rate for both the device transmitter (DEVICE TX) and the device receiver (DEVICE RX), so that for each of the device transmitter (DEVICE TX) and the device receiver (DEVICE RX) The size of the storage system may be reduced as compared to the case in which the clock generator is provided.

8 is a diagram for explaining a data rate reset operation according to an exemplary embodiment of the present disclosure. Specifically, in FIG. 8 , data transmitted by the storage device 100b reaches the host 200b due to an error occurring in a lane configured by the host receiver HOST RX and the device transmitter DEVICE TX. Assume that you do not Also, it is assumed that the host 200b and the storage device 100b transmit/receive data at the first data rate DR1 until the data rate is adjusted or reset. The data rate reset operation may include a plurality of steps S801 to S819.

In step S801 , the host 200b may transmit the first burst BURST 1 including the first power mode change request PWR_req1 through the host transmitter HOST TX. The host 200b may transmit the first power mode change request PWR_req1 and monitor whether the first power mode change response PWR_cnf1 is received within the first timeout 1 . In step S803 , the storage device 100b transmits a second burst BURST 2 including the first power mode change response PWR_cnf1 through the device transmitter DEVICE TX in response to the first power mode change request PWR_req1 can be transmitted However, due to an error in the lane LANE including the device transmitter DEVICE, the first power mode change response PWR_cnf1 may not reach the host 200b.

In step S885, if the first power mode change response PWR_cnf1 is not received within the first timeout 1, the host 200b sends a second power mode change request PWR_req2 through the host transmitter HOST TX. can be transmitted The second power mode change request PWR_req2 may be included in the first burst BURST 1 . The host 200b may transmit a second power mode change request PWR_req2 and monitor whether a second power mode change response PWR_cnf2 is received within a second timeout 2 . The length of the second time-out (timeout 2) may be the same as or different from the length of the first time-out (time 1). In operation S807 , the storage device 100b may transmit a second power mode change response PWR_cnf2 through the device transmitter DEVICE TX in response to the second power mode change request PWR_req2 . The second power mode change response PWR_cnf2 may be included in the second burst BURST 2 . However, due to an error in the lane LANE including the device transmitter DEVICE, the second power mode change response PWR_cnf2 may not reach the host 200b.

In some embodiments, after step S807, step S820 of adjusting the data transfer rate of the storage device 100b may be performed. Step S820 may include a plurality of steps S809 to S813. In step S809 , the host 200b may transmit the end bit TOB of the first burst BURST 1 through the host transmitter HOST TX. In step S811 , the storage device 100b detects the end bit TOB of the first burst BURST 1 , and transmits the end bit TOB of the second burst BURST 2 through the device transmitter DEVICE TX. can However, due to an error in the lane LANE including the device transmitter DEVICE, the end bit TOB of the second burst BURST 2 may not reach the host 200b. In step S813 , as described above with reference to FIG. 7 , the storage device 100b transmits the end bit TOB of the second burst BURST 2 , and sets the data rate from the first data rate DR1 to the second You can adjust the data rate (DR2). In some embodiments, step S820 may be omitted.

In operation S815 , if the second power mode change response PWR_cnf2 is not received within a second timeout 2 , the host 200b may transmit a line reset signal to the storage device 100b. The line reset signal can be sent through a dedicated reset signal pin. The line reset signal may be a signal instructing reset of the physical layer 111 of the interconnect unit 110 in a malfunctioning situation. In operation S817 , the storage device 100b may reset data rates of the device receiver DEVICE RX and the device transmitter DEVICE TX included in the physical layer 111 . Since the host 200b does not adjust the data transfer rate, when a timeout occurs, the data transfer rate of the host 200b may be set to the first data transfer rate DR1.

In some embodiments, the storage device 100b may reset the data rate to the data rate before receiving the line reset signal, that is, the first data rate DR1 . Accordingly, even if only the data transfer rate of the storage device 100b is reset, the host 200b and the storage device 100b may communicate smoothly using the same data transfer rate.

In some embodiments, the storage device 100b may reset the data transfer rate to a default data transfer rate. The default data rate may be preset in the link startup step S360 of FIG. 4 . The default data rate may be selected from among a plurality of speed gears included in each of the plurality of speed series. In one example, the default data rate may be the first data rate DR1 or the second data rate DR2. In this case, the host 200b may perform step S819. In step S819 , the host 200b may reset the data rate to a default data rate. That is, since step S819 is performed, the host 200b and the storage device 100b are reset to the same default data rate, so that the host 200b and the storage device 100b can communicate smoothly using the same data rate. .

9 is a diagram for explaining adjustment of a data rate according to an exemplary embodiment of the present disclosure. Specifically, FIG. 9 is a diagram for explaining a case in which data transmitted from the device transmitter (DEVICE TX) does not reach the host receiver (HOST RX) due to a link error. Accordingly, FIG. 9 may be described later with reference to FIG. 8 , and the above description with reference to FIG. 5 may be omitted.

Referring to FIG. 9 , the host 200b may transmit a first burst BURST 1 at a first data rate DR1 through the host transmitter HOST TX in the HS mode. The first burst BURST 1 may include a first power mode change request PWR_req1 for requesting to change the data rate to the second data rate DR2. The host 200b may monitor whether the first power mode change response PWR_cnf1 corresponding to the first power mode change request PWR_req1 arrives within the first timeout TIMEOUT 1 . The storage device 100b may transmit the first power mode change response PWR_cnf1 in response to the first power mode change request PWR_req1, but due to a link error, the first power mode change response PWR_cnf1 may be transmitted to the host receiver ( HOST RX) may not be reached.

The host 200b may transmit a second power mode change request PWR_req2 when the first timeout TIMEOUT 1 has elapsed. The second power mode change request PWR_req2 may be included in the first burst BURST 1 . The host 200b may monitor whether the second power mode change response PWR_cnf2 corresponding to the second power mode change request PWR_req2 arrives within the second timeout TIMEOUT 2 . The storage device 100b may transmit the second power mode change response PWR_cnf2 in response to the second power mode change request PWR_req2, but due to a link error, the second power mode change response PWR_cnf2 may be transmitted to the host receiver ( HOST RX) may not be reached.

As described above in step S809 of FIG. 8 , the host 200b may transmit the burst end bit TOB of the first burst BURST 1 . As described above in step S811 of FIG. 8 , the storage device 100b receives the burst end bit TOB of the first burst BURST 1 and the burst end bit TOB of the second burst BURST 2 . can be printed out. As described above in step S813 of FIG. 8 , the storage device 100b may adjust the data rate from the first data rate DR1 to the second data rate DR2 .

The host 200b may transmit a line reset signal when the second timeout TIMEOUT 2 has elapsed. The storage device 100b may detect the line reset signal and reset the data transfer rate. In some embodiments, the data rate may be reset to the data rate prior to receiving the line reset signal, that is, the first data rate DR1. In some embodiments, the storage device 100b may reset the data transfer rate to a default data transfer rate. The default data rate may be preset in the link startup step S360 of FIG. 4 .

10 is a diagram for explaining adjustment of a data rate according to an exemplary embodiment of the present disclosure. Specifically, FIG. 10 is a diagram for explaining a situation in which the second burst BURST 2 is not terminated when the host 200b transmits a line reset signal. The contents described above with reference to FIG. 9 may be omitted.

Referring to FIG. 10 , unlike FIG. 9 , when the host 200b transmits a line reset signal, the second burst BURST 2 transmitted by the device transmitter DEVICE TX may not be terminated. That is, the end bit TOB of the second burst BURST 2 may not be transmitted.

Accordingly, the storage device 100b may detect the line reset signal and transmit the end bit TOB of the second burst BURST 2 to the host 200b. That is, by terminating the second burst BURST 2 before resetting the data rate, the storage device 100b may prevent an error that may be included in the second burst BURST 2 while the data rate is reset. .

As described above in step S819 of FIG. 8 , the host 200b may transmit a line reset signal and reset the data rate to the default data rate. The default data rate may correspond to a speed gear included in the high-speed mode (HS mode), but the embodiment is not limited thereto. That is, the default data rate may be a low-speed mode (LS mode) that does not use an internal clock signal.

The storage device 100b may reset the data rate to a default data rate after transmitting the end bit TOB of the second burst BURST 2 . Through the line reset operation, the data transfer rates of the host 200b and the storage device 100b are reset to the default data transfer rates, so that the host 200b and the storage device 100b can communicate smoothly using the same data transfer rate. .

11 is a flowchart illustrating a method of operating a host according to an exemplary embodiment of the present disclosure. Specifically, FIG. 11 is a flowchart illustrating an operation method of a host for resetting a data rate by outputting a line reset signal based on a timeout. The method of operating the host may include a plurality of steps ( S1110 to S1180 ). 11 may be described later with reference to at least one of FIGS. 1 to 10 .

In step S1110 , the host 200b may transmit a first burst BURST 1 including the power mode change request PWR_req. In operation S1120 , the host 200b may identify whether a power mode change response PWR_cnf included in the second burst BURST 2 is received from the storage device 100b. If the power mode change response PWR_cnf is received, step S1170 may be performed, and if the power mode change response PWR_cnf is not received, step S1130 may be performed.

In operation S1170 , the host 200b may detect the end bit TOB of the second burst BURST 2 . For example, the TOB detector 221 included in the host 200 of FIG. 1 may detect the end bit TOB by identifying a predetermined bit sequence. The host 200b may repeatedly perform the detection operation until the end bit TOB is detected, and when the end bit TOB is detected, step S1180 may be performed.

In step S1180 , the host 200b may adjust data rates for the host transmitter (HOST TX) and the host receiver (HOST RX). For example, as described above with reference to the drawings, the host 200b may adjust the data transfer rate from the first data transfer rate DR1 to the second data transfer rate DR2. The data rate can be adjusted by changing the frequency of the reference clock signal or by changing the frequency of the internal clock signal.

In step S1130 , the host 200b may determine whether a timeout has elapsed. If the timeout does not elapse, in step S1120 , the timeout may be monitored until a power mode change response PWR_cnf is received. When the timeout has elapsed, step S1140 may be performed.

In operation S1140 , the host 200b may determine whether the timeout number Timeout_count has reached a reference number ref_count. As described above with reference to FIG. 10 , the reference number of times may be two, but the embodiment is not limited thereto. When the timeout number Timeout_count does not reach the reference number ref_count, the host 200b may transmit a power mode change request PWR_req to the storage device 100b again in step S1110 . When the timeout count Timeout_count reaches the reference count ref_count, step S1150 may be performed.

In operation S1150 , the host 200b may output a line reset signal to the storage device 100b through a reset signal pin. The line reset signal may be a signal instructing reset of the physical layer 111 of the interconnect unit 110 shown in FIG. 1 in a malfunctioning situation.

In step S1160 , the host 200b may reset the data rate to a default data rate. The default data rate may be preset in the link startup step S360 of FIG. 4 .

The host according to an exemplary embodiment of the present disclosure may smoothly transmit/receive data to/from the storage device even when an error occurs in the line by outputting a line reset signal and resetting the data transfer rate when the timeout has elapsed.

12 is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure. Specifically, FIG. 12 is a flowchart illustrating an operation method of a storage device for resetting a data transfer rate based on a line reset signal. The method of operating the storage device may include a plurality of steps ( S1210 to S1260 ). 12 may be described later with reference to at least one of FIGS. 1 to 10 .

In operation S1210 , the storage device 100b may receive the power mode change request PWR_req included in the first burst BURST 1 through the device receiver DEVICE RX. In operation S1220 , the storage device 100b may transmit a power mode change response PWR_cnf included in the second burst BURST 2 through the device transmitter DEVICE TX. Although it is illustrated that the power mode change request (PWR_req) and the power mode change response (PWR_cnf) are transmitted/received once at a time, the embodiment is not limited thereto. For example, as described above with reference to FIG. 11 , a power mode change request PWR_req may be received a plurality of times from the host 200b due to a timeout, and in response, the storage device 100b performs a plurality of times A power mode change response (PWR_cnf) may be transmitted.

In operation S1230 , the storage device 100b may detect the end bit TOB of the first burst BURST 1 . For example, the TOB detector 121 included in the device controller 120 of FIG. 1 may detect the end bit TOB of the first burst BURST 1 . When the end bit TOB is detected, step S1240 may be performed, and if the end bit TOB is not detected, step S1260 may be performed.

In operation S1240 , the storage device 100b may end the second burst BURST 2 by transmitting the end bit TOB of the second burst BURST 2 . By terminating the burst before adjusting the data rate, an error that may be included in the second burst BURST 2 while the data rate is adjusted can be prevented in advance.

In operation S1250 , the storage device 100b may adjust the data transfer rate. For example, as shown in FIG. 9 , the storage device 100b may adjust the data transfer rate from the first data rate DR1 to the second data rate DR2. The first data rate DR1 and the second data rate DR2 may be data rates of a high speed mode (HS mode) determined based on a frequency of an internal clock signal. The data rate may be adjusted by changing the frequency of the reference clock signal or changing the frequency of the internal clock signal.

In operation S1260 , the storage device 100b may detect a line reset signal. When the line reset signal is detected, step S1270 may be performed, and if the line reset signal is not detected, step S1230 may be performed again.

In operation S1270 , the storage device 100b may reset the data transfer rate. Specifically, the storage device 100b may reset the data rate to the data rate before the line reset signal is detected, or reset the data rate to the default data rate. In some embodiments, when the data transfer rate is adjusted from the first data rate DR1 to the second data rate DR2 in operation S1250, in operation S1270, the storage device 100b sets the data transfer rate based on the line reset signal. It can be reset to the first data rate DR1. In some embodiments, the default data rate may be set in the link startup step S360 described above with reference to FIG. 4 . The default data rate may correspond to a speed gear included in the high-speed mode (HS mode), but the embodiment is not limited thereto. That is, the default data rate may be a low-speed mode (LS mode) that does not use an internal clock signal.

In some embodiments, as described above with reference to FIG. 10 , when the line reset signal is detected, the end bit TOB of the second burst BURST 2 may not be transmitted. Accordingly, in step S1270 , the storage device 100b transmits the end bit TOB of the second burst BURST 2 before resetting the data rate, thereby preventing a transmission error from occurring while the data rate is reset. .

13 is a diagram for explaining the UFS system 1000 according to an embodiment of the present invention. The UFS system 1000 is a system conforming to the UFS standard published by the Joint Electron Device Engineering Council (JEDEC), and may include a UFS host 1100 , a UFS device 1200 , and a UFS interface 1300 . The description of the storage system 10 described above with reference to the drawings may also be applied to the UFS system 1000 of FIG. 13 to the extent that it does not conflict with the description below with respect to FIG. 13 .

Referring to FIG. 13 , a UFS host 1100 and a UFS device 1200 may be interconnected through a UFS interface 1300 . When the host 200 of FIG. 1 is an application processor, the UFS host 1100 may be implemented as a part of the corresponding application processor. The UFS host controller 1110 may respectively correspond to the host controller 220 of FIG. 1 . The UFS device 1200 may correspond to the storage device 100 of FIG. 1 , and the UFS device controller 1210 and the non-volatile memory 1220 are connected to the device controller 120 and the non-volatile memory 130 of FIG. 1 . Each can be matched.

The UFS host 1100 may include a UFS host controller 1110 , an application 1120 , a UFS driver 1130 , a host memory 1140 , and a UFS interconnect (UIC) layer 1150 . The UFS device 1200 may include a UFS device controller 1210 , a non-volatile memory 1220 , a storage interface 1230 , a device memory 1240 , a UIC layer 1250 , and a regulator 1260 . The nonvolatile memory 1220 may include a plurality of memory units 1221 , and the memory unit 1221 may include a V-NAND flash memory having a 2D structure or a 3D structure, but PRAM and/or RRAM It may include other types of non-volatile memory such as The UFS device controller 1210 and the nonvolatile memory 1220 may be connected to each other through the storage interface 1230 . The storage interface 1230 may be implemented to comply with a standard protocol such as toggle or ONFI.

The application 1120 may mean a program that wants to communicate with the UFS device 1200 in order to use the function of the UFS device 1200 . The application 1120 may transmit an input-output request (IOR) to the UFS driver 1130 for input/output to the UFS device 1200 . The input/output request (IOR) may mean a read request, a write request, and/or a discard request of data, but is not limited thereto.

The UFS driver 1130 may manage the UFS host controller 1110 through a UFS-HCI (host controller interface). The UFS driver 1130 may convert an input/output request generated by the application 1120 into a UFS command defined by the UFS standard, and transmit the converted UFS command to the UFS host controller 1110 . One I/O request can be converted into multiple UFS commands. A UFS command may be basically a command defined by the SCSI standard, but it may also be a command dedicated to the UFS standard.

The UFS host controller 1110 may transmit the UFS command converted by the UFS driver 1130 to the UIC layer 1250 of the UFS device 1200 through the UIC layer 1150 and the UFS interface 1300 . In this process, the UFS host register 1111 of the UFS host controller 1110 may serve as a command queue (CQ).

The UIC layer 1150 on the UFS host 1100 side may include MIPI M-PHY 1151 and MIPI UniPro 1152 , and the UIC layer 1250 on the UFS device 1200 side also MIPI M-PHY ( 1251) and MIPI UniPro (1252).

The UFS interface 1300 includes a line transmitting a reference clock signal REF_CLK, a line transmitting a hardware reset signal RESET_n for the UFS device 1200, and a pair of differential input signal pairs DIN_t and DIN_c. It may include a pair of lines for transmitting a line and a differential output signal pair (DOUT_t and DOUT_c).

The frequency value of the reference clock provided from the UFS host 1100 to the UFS device 1200 may be one of four values of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 1100 may change the frequency value of the reference clock during operation, that is, while data transmission/reception is performed between the UFS host 1100 and the UFS device 1200 . The UFS device 1200 may generate clocks of various frequencies from the reference clock provided from the UFS host 1100 by using a phase-locked loop (PLL) or the like. Also, the UFS host 1100 may set a value of a data rate between the UFS host 1100 and the UFS device 1200 through the frequency value of the reference clock. That is, the value of the data rate may be determined depending on the frequency value of the reference clock.

The UFS interface 1300 may support a plurality of lanes, and each lane may be implemented as a differential pair. For example, the UFS interface may include one or more receive lanes and one or more transmit lanes. In FIG. 13 , a pair of lines for transmitting a differential input signal pair (DIN_T and DIN_C) may constitute a receive lane, and a pair of lines for transmitting a differential output signal pair (DOUT_T and DOUT_C) may constitute a transmit lane, respectively. . 13 illustrates one transmission lane and one reception lane, the number of transmission lanes and reception lanes may be changed.

The reception lane and the transmission lane may transmit data in a serial communication method, and a full-duplex between the UFS host 1100 and the UFS device 1200 by a structure in which the reception and transmission lanes are separated. communication is possible. That is, the UFS device 1200 may transmit data to the UFS host 1100 through the transmission lane while receiving data from the UFS host 1100 through the reception lane. In addition, control data such as a command from the UFS host 1100 to the UFS device 1200, and the UFS host 1100 to be stored in the non-volatile memory 1220 of the UFS device 1200 or from the non-volatile memory 1220 User data to be read may be transmitted through the same lane. Accordingly, there is no need to further provide a separate lane for data transmission between the UFS host 1100 and the UFS device 1200 in addition to the pair of reception lanes and the pair of transmission lanes.

The UFS device controller 1210 of the UFS device 1200 may control overall operation of the UFS device 1200 . The UFS device controller 1210 may manage the nonvolatile memory 1220 through a logical unit (LU) 1211 which is a logical data storage unit. The number of LUs 1211 may be 8, but is not limited thereto. The UFS device controller 1210 may include a flash translation layer (FTL), and a logical data address transmitted from the UFS host 1100 using address mapping information of the FTL, for example, LBA. (logical block address) may be converted into a physical data address, for example, into a physical block address (PBA). A logical block for storing user data in the UFS system 1000 may have a size within a predetermined range. For example, the minimum size of the logical block may be set to 4Kbyte.

When a command from the UFS host 1100 is input to the UFS device 1200 through the UIC layer 1250, the UFS device controller 1210 performs an operation according to the input command, and when the operation is completed, a completion response is returned. It can be transmitted to the UFS host 1100 .

As an example, when the UFS host 1100 intends to store user data in the UFS device 1200 , the UFS host 1100 may transmit a data storage command to the UFS device 1200 . When a response indicating that the user data is ready-to-transfer is received from the UFS device 1200 , the UFS host 1100 may transmit the user data to the UFS device 1200 . The UFS device controller 1210 temporarily stores the received user data in the device memory 1240 and transfers the user data temporarily stored in the device memory 1240 based on the address mapping information of the FTL to the non-volatile memory 1220 . You can save it to a location of your choice.

As another example, when the UFS host 1100 wants to read user data stored in the UFS device 1200 , the UFS host 1100 may transmit a data read command to the UFS device 1200 . Upon receiving the command, the UFS device controller 1210 may read user data from the nonvolatile memory 1220 based on the data read command and temporarily store the read user data in the device memory 1240 . In this reading process, the UFS device controller 1210 may detect and correct an error in the read user data using a built-in error correction code (ECC) engine (not shown). More specifically, the ECC engine may generate parity bits for write data to be written into the non-volatile memory 1220 , and the generated parity bits are stored in the non-volatile memory 1220 together with the write data. can be saved. When reading data from the non-volatile memory 1220 , the ECC engine corrects an error in the read data using parity bits read from the non-volatile memory 1220 together with the read data, and outputs the error-corrected read data. can

In addition, the UFS device controller 1210 may transmit user data temporarily stored in the device memory 1240 to the UFS host 1100 . In addition, the UFS device controller 1210 may further include an advanced encryption standard (AES) engine (not shown). The AES engine may perform at least one of an encryption operation and a decryption operation on data input to the UFS device controller 1210 using a symmetric-key algorithm.

The UFS host 1100 may sequentially store commands to be transmitted to the UFS device 1200 in the UFS host register 1111, which may function as a command queue, and may transmit the commands to the UFS device 1200 in this order. . At this time, even if the previously transmitted command is still being processed by the UFS device 1200 , that is, even before the UFS host 1100 receives a notification that the processing of the previously transmitted command is completed by the UFS device 1200 . The next command waiting in the command queue may be transmitted to the UFS device 1200 , and accordingly, the UFS device 1200 may also receive the next command from the UFS host 1100 while processing the previously transmitted command. The maximum number of commands (queue depth) that can be stored in such a command queue may be, for example, 32. In addition, the command queue may be implemented as a circular queue type indicating the start and end of the command sequence stored in the queue, respectively, through a head pointer and a tail pointer.

Each of the plurality of memory units 1221 may include a memory cell array (not shown) and a control circuit (not shown) for controlling an operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a cell (single level cell, SLC) storing one bit of information, but a multi level cell (MLC), a triple level cell (TLC), It may be a cell that stores information of 2 bits or more, such as a quadruple level cell (QLC). The three-dimensional memory cell array may include vertical NAND strings that are vertically oriented such that at least one memory cell is positioned on top of another memory cell.

VCC, VCCQ, VCCQ2, etc. may be input to the UFS device 1200 as a power voltage. VCC is a main power voltage for the UFS device 1200 and may have a value of 2.4 to 3.6V. VCCQ is a power supply voltage for supplying a low-range voltage, mainly for the UFS device controller 1210 . It can have a value of 1.14 to 1.26V. VCCQ2 is a power supply voltage for supplying a voltage lower than VCC but higher than VCCQ, mainly for an input/output interface such as the MIPI M-PHY 1251, and may have a value of 1.7 to 1.95V. The power voltages may be supplied for each component of the UFS device 1200 through the regulator 1260 . The regulator 1260 may be implemented as a set of unit regulators respectively connected to different ones of the above-described power voltages.

14A to 14C are diagrams for explaining a form factor of a UFS card. When the UFS device 1200 described with reference to FIG. 13 is implemented in the form of the UFS card 2000, the appearance of the UFS card 2000 may be as shown in FIGS. 14A to 14C.

14A exemplarily shows a top view of the UFS card 2000 . Referring to FIG. 14A , it can be seen that the UFS card 2000 follows a shark-shaped design as a whole. Referring to FIG. 14A , the UFS card 2000 may have dimension values as exemplarily shown in Table 1 below.

Item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

26B exemplarily shows a side view of the UFS card 2000 . Referring to FIG. 26B , the UFS card 2000 may have dimension values as exemplarily shown in Table 2 below.

Item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

26C exemplarily shows a bottom view of the UFS card 2000 . Referring to FIG. 26C , a plurality of pins for electrical contact with the UFS slot may be formed on the bottom surface of the UFS card 2000 , and the function of each pin will be described later. Based on the symmetry between the top and bottom surfaces of the UFS card 2000, some of the information regarding dimensions described with reference to FIG. 26A and Table 1 (eg, T1 to T5 and T9) is a UFS card as shown in FIG. 26C (2000). A plurality of pins may be formed on the bottom of the UFS card 2000 for electrical connection with the UFS host, and according to FIG. 26C, the total number of pins may be 12. Each pin may have a rectangular shape, and a signal name corresponding to the pin is as shown in FIG. 26C . For schematic information about each pin, you can refer to Table 3 below.

number signal name Explanation Dimensions (mm) One vss Ground (GND) 3.00 × 0.72±0.05 2 DIN_C Differential input signal input from host to UFS card (4000) (DIN_C is negative node, DIN_T is positive node) 1.50 × 0.72±0.05 3 DIN_T 4 vss same as 1 3.00 × 0.72±0.05 5 DOUT_C Differential output signal output from the UFS card (4000) to the host (DOUT_C is a negative node, DOUT_T is a positive node) 1.50 × 0.72±0.05 6 DOUT_T 7 vss same as 1 3.00 × 0.72±0.05 8 REF_CLK Reference clock provided from host to UFS card (4000) 1.50 × 0.72±0.05 9 VCCQ2 A supply voltage with a relatively low value relative to Vcc, mainly provided for a PHY interface or controller. 3.00 × 0.72±0.05 10 C/D (GND) Signals for Card Detection 1.50 × 0.72±0.05 11 vss same as 1 3.00 × 0.80±0.05 12 Vcc mains voltage

15 is a block diagram illustrating a memory system 3000 according to an embodiment of the present disclosure.

Referring to FIG. 15 , a memory system 3000 may include a memory device 3200 and a memory controller 3100 . The memory device 3200 may correspond to one of the nonvolatile memory devices communicating with the memory controller 3100 based on one of a plurality of channels. For example, the memory device 3200 may correspond to the nonvolatile memory 130 of FIG. 1 , and the memory controller 3100 may correspond to the device controller 120 of FIG. 1 .

The memory device 3200 may include first to eighth pins P11 to P18 , a memory interface circuit 3210 , a control logic circuit 3220 , and a memory cell array 3230 . The memory interface circuit 3210 may receive the chip enable signal nCE from the memory controller 3100 through the first pin P11 . The memory interface circuit 3210 may transmit/receive signals to and from the memory controller 3100 through the second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable state (eg, a low level), the memory interface circuit 3310 is configured to operate the memory controller 3100 through the second to eighth pins P12 to P18. ) and can transmit and receive signals.

The memory interface circuit 3210 receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal from the memory controller 3100 through the second to fourth pins P12 to P14. nWE) can be received. The memory interface circuit 3210 may receive the data signal DQ from the memory controller 3100 through the seventh pin P17 or transmit the data signal DQ to the memory controller 3100 . A command CMD, an address ADDR, and data DATA may be transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to a plurality of data signals.

The memory interface circuit 3210 receives the data signal DQ received in the enable period (eg, high level state) of the command latch enable signal CLE based on the toggle timings of the write enable signal nWE. A command (CMD) can be obtained from The memory interface circuit 3210 receives the data signal DQ received in the enable period (eg, high level state) of the address latch enable signal ALE based on the toggle timings of the write enable signal nWE. The address ADDR can be obtained from

In an exemplary embodiment, the write enable signal nWE may be toggled between a high level and a low level while maintaining a static state (eg, a high level or a low level). have. For example, the write enable signal nWE may be toggled in a period in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit 3210 may acquire the command CMD or the address ADDR based on the toggle timings of the write enable signal nWE.

The memory interface circuit 3210 may receive the read enable signal nRE from the memory controller 3100 through the fifth pin P15 . The memory interface circuit 3210 may receive the data strobe signal DQS from the memory controller 3100 through the sixth pin P16 or transmit the data strobe signal DQS to the memory controller 3100 .

In the data output operation of the memory device 3200 , the memory interface circuit 3210 may receive the read enable signal nRE toggling through the fifth pin P15 before outputting the data DATA. have. The memory interface circuit 3210 may generate a toggling data strobe signal DQS based on the toggling of the read enable signal nRE. For example, the memory interface circuit 3210 generates a data strobe signal DQS that starts toggling after a predetermined delay (eg, tDQSRE) based on a toggling start time of the read enable signal nRE. can do. The memory interface circuit 310 may transmit the data signal DQ including the data DATA based on the toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 3100 .

In the data input operation of the memory device 3200 , when the data signal DQ including the data DATA is received from the memory controller 3100 , the memory interface circuit 3210 receives the data from the memory controller 3100 . A data strobe signal DQS toggling together with the data DATA may be received. The memory interface circuit 3210 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 3210 may acquire the data DATA by sampling the data signal DQ at rising edges and falling edges of the data strobe signal DQS.

The memory interface circuit 3210 may transmit the ready/busy output signal nR/B to the memory controller 3100 through the eighth pin P18 . The memory interface circuit 3210 may transmit state information of the memory device 3200 to the memory controller 3100 through the ready/busy output signal nR/B. When the memory device 3200 is in a busy state (that is, when internal operations of the memory device 3200 are being performed), the memory interface circuit 3210 transmits a ready/busy output signal nR/B indicating the busy state to the memory controller It can be transmitted to (3100). When the memory device 3200 is in the ready state (that is, when internal operations of the memory device 3200 are not performed or completed), the memory interface circuit 3210 outputs a ready/busy output signal nR/B indicating the ready state. may be transmitted to the memory controller 3100 . For example, while the memory device 3200 reads data DATA from the memory cell array 3230 in response to a page read command, the memory interface circuit 3210 may be in a busy state (eg, a low level). A ready/busy output signal nR/B indicating nR/B may be transmitted to the memory controller 3100 . For example, while the memory device 3200 programs data DATA into the memory cell array 3230 in response to a program command, the memory interface circuit 3210 provides a ready/busy output signal nR/ B) may be transmitted to the memory controller 3100 .

The control logic circuit 3220 may generally control various operations of the memory device 3200 . The control logic circuit 3220 may receive the command/address CMD/ADDR obtained from the memory interface circuit 3210 . The control logic circuit 3220 may generate control signals for controlling other components of the memory device 3200 according to the received command/address CMD/ADDR. For example, the control logic circuit 3220 may generate various control signals for programming data DATA in the memory cell array 3230 or reading data DATA from the memory cell array 3230 . .

The memory cell array 3230 may store data DATA obtained from the memory interface circuit 3210 under the control of the control logic circuit 3220 . The memory cell array 3230 may output the stored data DATA to the memory interface circuit 3210 under the control of the control logic circuit 3220 .

The memory cell array 3230 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells include a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, They may be Magnetic Random Access Memory (MRAM) cells. Hereinafter, embodiments of the present invention will be described focusing on an embodiment in which the memory cells are NAND flash memory cells.

The memory controller 3100 may include first to eighth pins P21 to P28 and a controller interface circuit 3110 . The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the memory device 3200 . The controller interface circuit 3110 may transmit the chip enable signal nCE to the memory device 3200 through the first pin P21 . The controller interface circuit 3110 may transmit/receive signals to and from the memory device 3200 selected through the chip enable signal nCE and the second to eighth pins P22 to P28.

The controller interface circuit 3110 transmits the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device through the second to fourth pins P22 to P24. 3200) can be transmitted. The controller interface circuit 3110 may transmit the data signal DQ to the memory device 3200 or receive the data signal DQ from the memory device 3200 through the seventh pin P27 .

The controller interface circuit 3110 may transmit the data signal DQ including the command CMD or the address ADDR together with the toggling write enable signal nWE to the memory device 3200 . The controller interface circuit 3110 transmits the data signal DQ including the command CMD to the memory device 3200 as the command latch enable signal CLE having an enable state is transmitted, and sets the enable state to the memory device 3200 . As the branch transmits the address latch enable signal ALE, the data signal DQ including the address ADDR may be transmitted to the memory device 3200 .

The controller interface circuit 3110 may transmit the read enable signal nRE to the memory device 3200 through the fifth pin P25 . The controller interface circuit 3110 may receive the data strobe signal DQS from the memory device 3200 through the sixth pin P26 or transmit the data strobe signal DQS to the memory device 3200 .

In the data output operation of the memory device 3200 , the controller interface circuit 3110 may generate a toggle read enable signal nRE and transmit the read enable signal nRE to the memory device 3200 . have. For example, the controller interface circuit 3110 may generate a read enable signal nRE that is changed from a fixed state (eg, a high level or a low level) to a toggle state before the data DATA is output. have. Accordingly, the data strobe signal DQS toggling based on the read enable signal nRE in the memory device 3200 may be generated. The controller interface circuit 3110 may receive the data signal DQ including the data DATA together with the toggling data strobe signal DQS from the memory device 3200 . The controller interface circuit 3110 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device 3200 , the controller interface circuit 3110 may generate a toggle data strobe signal DQS. For example, the controller interface circuit 3110 may generate a data strobe signal DQS that is changed from a fixed state (eg, a high level or a low level) to a toggle state before transmitting the data DATA. . The controller interface circuit 3110 may transmit the data signal DQ including the data DATA to the memory device 3200 based on the toggle timings of the data strobe signal DQS.

The controller interface circuit 3110 may receive the ready/busy output signal nR/B from the memory device 3200 through the eighth pin P28 . The controller interface circuit 3110 may determine state information of the memory device 3200 based on the ready/busy output signal nR/B.

16 is a diagram for explaining a 3D VNAND structure applicable to a UFS device according to an embodiment of the present invention. When the storage module of the UFS device is implemented as a 3D VNAND (Vertical NAND) type flash memory, each of a plurality of memory blocks constituting the storage module may be represented by an equivalent circuit as shown in FIG. 16 . The memory block BLKi illustrated in FIG. 16 represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 16 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 , MC2 , ..., MC8 , and a ground select transistor GST. 28 , each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 , MC2 , ..., MC8 , but is not limited thereto.

The string select transistor SST may be connected to the corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be respectively connected to corresponding gate lines GTL1 , GTL2 , ..., GTL8 . The gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to the corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to the corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines of the same height (eg, WL1 ) may be commonly connected, and the ground selection lines GSL1 , GSL2 , and GSL3 and the string selection lines SSL1 , SSL2 , and SSL3 may be separated from each other. 28 shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. not.

17 is a diagram for explaining a B-VNAND structure applicable to a UFS device according to an embodiment of the present invention. When the nonvolatile memory included in the UFS device is implemented as a B-VNAND (Bonding Vertical NAND) type flash memory, the nonvolatile memory may have the structure shown in FIG. 17 .

Referring to FIG. 17 , the memory device 4000 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer different from the first wafer, and then the upper chip It may mean connecting the chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed in the uppermost metal layer of the upper chip and the bonding metal formed in the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten.

Each of the peripheral circuit area PERI and the cell area CELL of the memory device 4000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI includes a first substrate 4110 , an interlayer insulating layer 4115 , a plurality of circuit elements 4120a , 4120b , and 4120c formed on the first substrate 4110 , and a plurality of circuit elements 4120a . , 4120b, 4120c) The first metal layer (4130a, 4130b, 4130c) connected to each, the second metal layer (4140a, 4140b, 4140c) formed on the first metal layer (4130a, 4130b, 4130c) to include can In one embodiment, the first metal layers 4130a, 4130b, and 4130c may be formed of tungsten having a relatively high resistance, and the second metal layers 4140a, 4140b, or 4140c may be formed of copper having a relatively low resistance. can

In the present specification, only the first metal layers 4130a, 4130b, 4130c and the second metal layers 4140a, 4140b, and 4140c are shown and described, but not limited thereto, and the second metal layers 4140a, 4140b, 4140c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 4140a, 4140b, and 4140c are formed of aluminum having a lower resistance than copper forming the second metal layers 4140a, 4140b, and 4140c. can be

The interlayer insulating layer 4115 is a first substrate to cover the plurality of circuit elements 4120a, 4120b, and 4120c, the first metal layers 4130a, 4130b, and 4130c, and the second metal layers 4140a, 4140b, and 4140c. It is disposed on the 4110 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method. , the lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may be formed of aluminum, copper, tungsten, or the like.

The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 4210 and a common source line 4220 . A plurality of word lines 4231-4238; 4230 may be stacked on the second substrate 4210 in a direction (Z-axis direction) perpendicular to the top surface of the second substrate 4210 . String select lines and ground select lines may be disposed above and below the word lines 4230 , respectively, and a plurality of word lines 4230 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the top surface of the second substrate 4210 to pass through the word lines 4230 , the string selection lines, and the ground selection line. have. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may be a bit line contact, and the second metal layer 4260c may be a bit line. In an embodiment, the bit line 4260c may extend along a first direction (Y-axis direction) parallel to the top surface of the second substrate 4210 .

In the exemplary embodiment illustrated in FIG. 17 , a region in which the channel structure CH and the bit line 4260c are disposed may be defined as the bit line bonding area BLBA. The bit line 4260c may be electrically connected to the circuit elements 4120c providing the page buffer 4293 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 4260c is connected to the upper bonding metals 4271c and 4272c in the peripheral circuit region PERI, and the upper bonding metals 4271c and 4272c are connected to the circuit elements 4120c of the page buffer 4293. It may be connected to the lower bonding metals 4171c and 4172c to be connected.

In the word line bonding area WLBA, the word lines 4230 may extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 4210 , and include a plurality of cell contact plugs 4241 . -4247; 4240). The word lines 4230 and the cell contact plugs 4240 may be connected to each other through pads provided by at least some of the word lines 4230 extending in different lengths along the second direction. A first metal layer 4250b and a second metal layer 4260b may be sequentially connected to the upper portions of the cell contact plugs 4240 connected to the word lines 4230 . The cell contact plugs 4240 are formed in the word line bonding area WLBA through the upper bonding metals 4271b and 4272b of the cell area CELL and the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI through a peripheral circuit. It may be connected to the region PERI.

The cell contact plugs 4240 may be electrically connected to the circuit elements 4120b providing the row decoder 4294 in the peripheral circuit region PERI. In an embodiment, the operating voltages of the circuit elements 4120b providing the row decoder 4294 may be different from the operating voltages of the circuit elements 4120c providing the page buffer 4293 . For example, the operating voltages of the circuit elements 4120c providing the page buffer 4293 may be greater than the operating voltages of the circuit elements 4120b providing the row decoder 4294 .

A common source line contact plug 4280 may be disposed in the external pad bonding area PA. The common source line contact plug 4280 may be formed of a metal, a metal compound, or a conductive material such as polysilicon, and may be electrically connected to the common source line 4220 . A first metal layer 4250a and a second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280 . For example, an area in which the common source line contact plug 4280 , the first metal layer 4250a , and the second metal layer 4260a are disposed may be defined as the external pad bonding area PA.

Meanwhile, input/output pads 4105 and 4205 may be disposed in the external pad bonding area PA. Referring to FIG. 17 , a lower insulating film 4101 covering the lower surface of the first substrate 4110 may be formed on the lower portion of the first substrate 4110 , and first input/output pads 4105 on the lower insulating film 4101 . can be formed. The first input/output pad 4105 is connected to at least one of the plurality of circuit elements 4120a, 4120b, and 4120c disposed in the peripheral circuit region PERI through the first input/output contact plug 4103 , and the lower insulating layer 4101 ) may be separated from the first substrate 4110 by the In addition, a side insulating layer may be disposed between the first input/output contact plug 4103 and the first substrate 4110 to electrically separate the first input/output contact plug 4103 from the first substrate 4110 .

Referring to FIG. 17 , an upper insulating layer 4201 covering the upper surface of the second substrate 4210 may be formed on the second substrate 4210 , and second input/output pads 4205 on the upper insulating layer 4201 . can be placed. The second input/output pad 4205 may be connected to at least one of the plurality of circuit elements 4120a , 4120b , and 4120c disposed in the peripheral circuit area PERI through the second input/output contact plug 4203 .

In some embodiments, the second substrate 4210 and the common source line 4220 may not be disposed in the region where the second input/output contact plug 4203 is disposed. Also, the second input/output pad 4205 may not overlap the word lines 4230 in the third direction (Z-axis direction). Referring to FIG. 17 , the second input/output contact plug 4203 is separated from the second substrate 4210 in a direction parallel to the top surface of the second substrate 4210 , and an interlayer insulating layer 4215 of the cell region CELL. may be connected to the second input/output pad 4205 through the .

In some embodiments, the first input/output pad 4105 and the second input/output pad 4205 may be selectively formed. For example, the memory device 4000 includes only the first input/output pad 4105 disposed on the first substrate 4110 , or the second input/output pad 4205 disposed on the second substrate 4210 . can contain only Alternatively, the memory device 4000 may include both the first input/output pad 4105 and the second input/output pad 4205 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or The uppermost metal layer may be empty.

In the external pad bonding area PA, the memory device 4000 corresponds to the upper metal pattern 4272a formed on the uppermost metal layer of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI. ), a lower metal pattern 4176a having the same shape as the upper metal pattern 4272a may be formed. The lower metal pattern 4176a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, the lower metal pattern of the peripheral circuit area PERI on the upper metal layer of the cell area CELL to correspond to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI in the external pad bonding area PA An upper metal pattern having the same shape as the above may be formed.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the lower part of the peripheral circuit area PERI is formed on the uppermost metal layer of the cell area CELL corresponding to the lower metal pattern 4152 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 4292 having the same shape as the metal pattern 4152 may be formed. A contact may not be formed on the upper metal pattern 4292 formed on the uppermost metal layer of the cell region CELL.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although embodiments have been described using specific terms in the present specification, these are only used for the purpose of explaining the technical idea of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims . Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (10)

receiving a first bit sequence including a request for changing the data rate from the host according to the first data rate through an input signal pin;
transmitting a second bit sequence including a response to the change request to the host according to the first data rate through an output signal pin; and
and changing a data rate to a second data rate according to whether an end bit indicating an end of the second bit sequence is output. According to claim 1,
Changing the data rate to the second data rate comprises:
The method of operating a storage device, characterized in that it is performed during a time period during which data is not transmitted to the host. According to claim 1,
Changing the data rate to the second data rate comprises:
and changing the frequency of an internal clock signal synchronized with data based on a reference clock signal received from the host through a clock signal pin so that the data rate is changed to the second data rate. How the device works. According to claim 1,
receiving a line reset signal from the host through a reset signal pin; and
and changing the data rate to a third data rate in response to receiving the line reset signal. 5. The method of claim 4,
The third data rate is,
The operating method of the storage device, characterized in that the first data transfer rate or a predetermined default data transfer rate. A method of operating a storage system including a host and a storage device, the method comprising:
transmitting, by the host, a first bit sequence including a data transfer rate change request to the storage device according to a first data transfer rate;
transmitting, by the storage device, a second bit sequence including a response corresponding to the change request to the host according to the first data rate; and
and changing, by the host and the storage device, a data transfer rate based on an end bit indicating an end of the second bit sequence. 7. The method of claim 6,
The step of changing the data transfer rate by the host and the storage device includes:
changing, by the storage device, a data transfer rate to a second data transfer rate based on whether the end bit is output; and
and changing, by the host, the data rate to the second data rate based on whether the end bit is received. 7. The method of claim 6,
The step of changing the data transfer rate by the host and the storage device includes:
The method of operating a storage system, characterized in that the operation is performed during a time period in which the host and the storage device do not transmit/receive data. 7. The method of claim 6,
outputting, by the host, a line reset signal through a reset signal pin based on whether a response corresponding to the change request has been received; and
and changing, by the storage device, a data rate to a third data rate in response to the line reset signal. a non-volatile memory in which data received from the host is stored;
a device controller controlling the non-volatile memory; and
and an interconnect unit connected to the host through a plurality of pins;
The interconnect unit,
Receives a first bit sequence including a data rate change request from the host according to the first data rate, and transmits a second bit sequence including a response to the change request to the host according to the first data rate and changing the data rate to the second data rate according to whether an end bit indicating the end of the second bit sequence is output.

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