KR20220090739A - Display device - Google Patents

Abstract

The present specification relates to a display device, and more particularly, to a display device capable of reducing an exposure time of an abnormal image to a user when the display device does not normally display an image. A display device according to an exemplary embodiment of the present specification includes a display panel, a data driving circuit, a gate driving circuit, a timing controller, a power management circuit, and a second base voltage supply circuit. The timing controller determines whether the sensed value obtained by the data driving circuit is normal, and controls driving of the second base voltage supply circuit according to a result of determining whether the sensed value is normal.

Description

display device {DISPLAY DEVICE}

The present specification relates to a display device, and more particularly, to a display device capable of reducing an exposure time of an abnormal image to a user when the display device does not normally display an image.

Recently, a display device using a flat panel display such as a liquid crystal display device, an organic light emitting diode display device, a light emitting diode display device, and an electrophoretic display device has been widely used.

Among them, an organic light emitting diode display displays an image through sub-pixels including an organic light emitting element, which is a self-emissive element. Accordingly, the organic light emitting diode display has an advantage in that it has a smaller thickness than other display devices, a wide viewing angle, and a fast response speed. However, the sub-pixels of the organic light emitting diode display are deteriorated due to various causes. When the sub-pixel is deteriorated, it becomes difficult to display a normal image, and the lifespan of the organic light emitting diode display is shortened. Accordingly, various techniques for compensating for sub-pixel degradation of the organic light emitting diode display are being applied.

Some elements included in the sub-pixel, for example, a transistor or a light emitting element, gradually deteriorate as the driving time increases. The characteristic value of the light emitting device of the transistor changes according to deterioration of the transistor or the light emitting device. Since the display panel includes a plurality of sub-pixels, when the characteristic values of the elements included in each sub-pixel change, a characteristic value deviation between the elements included in the sub-pixels occurs. When the luminance of each sub-pixel becomes non-uniform due to a change or deviation in characteristic values of elements included in each sub-pixel, image display quality of the display device deteriorates.

In order to solve this problem, a sub-pixel compensation technique for sensing a change in characteristic values of devices included in each sub-pixel and compensating for characteristic values of devices included in each sub-pixel according to the sensing result is applied. When the sub-pixel compensation technology is applied, characteristic values of elements included in each sub-pixel are compensated according to a sensing value obtained from each sub-pixel, so that the image display quality of the display device is improved.

However, a case in which the sensed value obtained in the compensation process is abnormal may occur. When the sensing value is abnormal, compensation for each sub-pixel is abnormally performed, so that the image display quality of the display device is deteriorated.

Therefore, when an abnormal sensing value is obtained during the sub-pixel compensation process, it is necessary to block the image display operation by the display device to minimize the time the abnormal image is exposed to the user.

An object of the present specification is to minimize an abnormal image exposure time to a user by immediately stopping image display by a display device when an abnormal sensing value is obtained in the sub-pixel compensation process.

The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment of the present specification includes a display panel, a data driving circuit, a gate driving circuit, a timing controller, a power management circuit, and a second base voltage supply circuit.

The display panel includes a plurality of sub-pixels disposed at intersections of a plurality of data lines and a plurality of gate lines.

A data driving circuit drives the plurality of data lines.

A gate driving circuit drives the plurality of gate lines.

A timing controller controls driving of the data driving circuit and the gate driving circuit.

The power management circuit outputs a first base voltage or a second base voltage based on power supplied from the host system.

A second base voltage supply circuit supplies a second base voltage supplied from the power management circuit to the display panel.

In one embodiment of the present specification, the timing controller determines whether the sensed value obtained by the data driving circuit is normal. The timing controller controls the driving of the second base voltage supply circuit according to the determination result of whether the sensed value is normal.

A display device according to another exemplary embodiment of the present specification includes a display panel, a data driving circuit, a gate driving circuit, a timing controller, a power management circuit, and a second base voltage supply circuit.

The display panel includes a plurality of sub-pixels disposed at intersections of a plurality of data lines and a plurality of gate lines.

A data driving circuit drives the plurality of data lines.

A gate driving circuit drives the plurality of gate lines.

A timing controller controls driving of the data driving circuit and the gate driving circuit.

The power management circuit outputs a first base voltage or a second base voltage based on power supplied from the host system.

A second base voltage supply circuit supplies a second base voltage supplied from the power management circuit to the display panel.

In another exemplary embodiment of the present specification, the second base voltage supply circuit supplies the second base voltage to the display panel when the sensed value obtained by the data driving circuit is abnormal.

According to an exemplary embodiment of the present specification, when an abnormal sensing value is obtained in the sub-pixel compensation process, image display by the display device is immediately stopped. Accordingly, the time during which an abnormal image is unnecessarily exposed to the user can be minimized.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a block diagram illustrating an overall configuration of a display device according to an exemplary embodiment of the present specification.
2 illustrates a configuration of a sub-pixel array included in a display panel according to an exemplary embodiment of the present specification.
3 illustrates a circuit configuration of a sub-pixel, a timing controller, a data driving circuit, and a connection structure between the sub-pixels according to an exemplary embodiment of the present specification.
4 illustrates a configuration of a display device and a connection relationship with a host system according to an exemplary embodiment of the present specification.
5 illustrates a configuration of a display device and a connection relationship with a host system according to another exemplary embodiment of the present specification.

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform the possessor of the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, when the temporal relationship is described as 'after', 'following', 'after', 'before', etc., 'immediately' or 'directly' Unless ' is used, cases that are not continuous may be included.

In the case of a description of the signal flow relationship, for example, even in the case of 'a signal is transmitted from node A to node B', unless 'directly' or 'directly' is used, node A goes through another node. A case in which a signal is transmitted to node B may be included.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, each embodiment may be practiced independently with respect to each other, and two or more embodiments may be It may be carried out together.

In the present specification, the sub-pixel circuit and the gate driving circuit formed on the substrate of the display panel may be implemented as transistors of an n-type MOSFET structure, but is not limited thereto, and may be implemented as transistors of a p-type MOSFET structure. A transistor may include a gate, a source, and a drain. In a transistor, a carrier can flow from a source to a drain. In the case of an n-type transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. In the case of the p-type transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type transistor, since holes flow from the source to the drain, the current flows from the source to the drain. In a transistor having a MOSFET structure, the source and drain are not fixed, but can be changed according to an applied voltage. Accordingly, in this specification, any one of the source and the drain is referred to as a first source/drain electrode, and the other one of the source and the drain is referred to as a second source/drain electrode.

Hereinafter, a preferred example of a gate driving circuit according to the present specification and a display device including the same will be described in detail with reference to the accompanying drawings. Even if shown in different drawings, the same components may have the same reference numerals. And, since the scales of the components shown in the accompanying drawings have different scales from the actual for convenience of description, the scales shown in the drawings are not limited thereto.

1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment of the present specification. Also, FIG. 2 shows a configuration of a sub-pixel array included in a display panel according to an exemplary embodiment of the present specification.

1 and 2 , a display device 1 according to an exemplary embodiment of the present specification includes a display panel 10 , a data driving circuit 12 , a gate driving circuit 13 , and a timing controller 11 . do.

A plurality of data lines 14 and a plurality of gate lines 16 are disposed to cross each other on the display panel 10 . In addition, sub-pixels SP are arranged in a matrix form at each intersection of the data lines 14 and the gate lines 16 .

The data lines 14 include m (m is a positive integer) data voltage supply lines 14A_1 to 14A_m and m sensing voltage readout lines 14B_1 to 14B_m. In addition, the gate lines 15 include n (n is a positive integer) first gate lines 15A_1 to 15A_n and n second gate lines 15B_1 to 15B_n.

Each sub-pixel SP is connected to any one of the data voltage supply lines 14A_1 to 14A_m, any one of the sensing voltage readout lines 14B_1 to 14B_m, and any one of the first gate lines 15A_1 to 15A_n. to one, and to any one of the second gate lines 15B_1 to 15B_n. Each sub-pixel SP may display a different color, and a predetermined number of sub-pixels SP may be gathered to form one pixel P.

Each sub-pixel SP receives a data voltage through a data voltage supply line, receives a first gate signal through a first gate line, receives a second gate signal through a second gate line, and reads a sensing voltage. The sensed voltage is output through the outline.

That is, in the sub-pixel array shown in FIG. 2 , the sub-pixels SP include the first gate signal and the second gate lines 15B_1 to 15B_n supplied in units of horizontal lines from the first gate lines 15A_1 to 15A_n. ), in response to the second gate signal supplied in units of horizontal lines, operates by one horizontal line (L#1 to L#n). The sub-pixels SP on the same horizontal line on which the sensing operation is activated receive a threshold voltage sensing data voltage from the data voltage supply lines 14A_1 to 14A_m, and receive a sensing voltage from the sensing voltage readout lines 14B_1 to 14B_m. to output Each of the first gate signal and the second gate signal may be a gate signal for sensing a threshold voltage or a gate signal for displaying an image, but is not limited thereto.

Each sub-pixel SP receives a high potential voltage EVDD and a low potential voltage EVSS from the power management circuit 16 . The sub-pixel SP may include an OLED, a driving transistor, first and second switching transistors, and a storage capacitor. According to an embodiment, a light source other than the OLED may be included in the sub-pixel SP.

Transistors constituting the sub-pixel SP may be implemented as p-type or n-type transistors. In addition, the semiconductor layers of the transistors constituting the sub-pixel SP may include amorphous silicon, polysilicon, or oxide.

During the image display operation, the data driving circuit 12 uses the compensated image data MDATA input from the timing controller 11 based on the data control signal DDC as the data voltage for image display to connect the data voltage supply lines. (14A_1 to 14A_m) are supplied.

During the sensing operation for sensing the threshold voltage of the driving transistor, the data driving circuit 12 applies the threshold voltage sensing data voltage to the sub-pixels SP according to the first gate signal for threshold voltage sensing supplied in units of horizontal lines. and a sensing value generated based on digital values of sensing voltages input from the display panel 10 through sensing voltage readout lines 14B_1 to 14B_m is supplied to the timing controller 11 .

The gate driving circuit 13 generates a gate signal based on the gate control signal GDC. The gate signal may include a first gate signal for sensing a threshold voltage, a second gate signal for sensing a threshold voltage, a first gate signal for displaying an image, and a second gate signal for displaying an image.

During the sensing operation, the gate driving circuit 13 supplies the first gate signal for sensing the threshold voltage to the first gate lines 15A_1 to 15A_n in units of horizontal lines, and supplies the second gate signal for sensing the threshold voltage in units of horizontal lines. It may be supplied to the second gate lines 15B_1 to 15B_n. The gate driving circuit 13 supplies a first gate signal for image display to the first gate lines 15A_1 to 15A_n in units of horizontal lines during an image display operation for image display and supplies a second gate signal for image display It may be supplied to the second gate lines 15B_1 to 15B_n in units of horizontal lines. In an exemplary embodiment of the present specification, the gate driving circuit 13 may be disposed on the display panel 10 in a gate-driver in panel (GIP) method.

The timing controller 11 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE transmitted from the host system 2 . The data control signal DDC for controlling the operation timing of the data driving circuit 12 and the gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated. In addition, the timing controller 11 compensates for the image data DATA transmitted from the host system 2 using the sensed value supplied from the data driving circuit 12 , thereby compensating for a threshold voltage deviation of the driving transistor. The data MDATA is generated, and the compensated image data MDATA is supplied to the data driving circuit 12 .

The power management circuit 16 generates and supplies a voltage necessary for driving the display device 1 based on the power supplied from the host system 2 . In one embodiment of the present specification, the power management circuit 16 provides a driving voltage EVDD and a base voltage (EVDD) necessary for driving each sub-pixel SP based on the input voltage Vin supplied from the host system 2 . EVSS) and supply the driving voltage EVDD and the base voltage EVSS to the display panel 10 . As another example, the power management circuit 16 generates a gate driving voltage GVDD and a gate base voltage GVSS necessary for driving the gate driving circuit 13 , and a gate driving voltage GVDD and a gate base voltage GVSS ) may be supplied to the gate driving circuit 13 .

3 illustrates a circuit configuration of a sub-pixel, a timing controller, a data driving circuit, and a connection structure between the sub-pixels according to an exemplary embodiment of the present specification.

Referring to FIG. 3 , the sub-pixel SP includes an OLED, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST, and a second switching transistor ST2.

The OLED includes an anode electrode connected to the second node N2 , a cathode electrode connected to an input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode.

The driving transistor DT conducts according to the gate-source voltage Vgs to control the current Ioled flowing through the OLED. The driving transistor DT includes a gate electrode connected to the first node N1 , a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the second node N2 .

The storage capacitor Cst is connected between the first node N1 and the second node N2 .

During the sensing operation, the first switching transistor ST1 applies the threshold voltage sensing data voltage Vdata charged in the data voltage supply line 14A in response to the first gate signal SCAN for threshold voltage sensing to the first node N1. ) is approved.

During the image display operation, the first switching transistor ST1 applies the image display data voltage Vdata charged in the data voltage supply line 14A to the first node N1 in response to the image display first gate signal SCAN. accredit to The first switching transistor ST1 includes a gate electrode connected to the first gate line 15A, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1 .

During the sensing operation, the second switching transistor ST2 switches the current flow between the second node N2 and the sensing voltage readout line 14B in response to the second gate signal SEN for sensing the threshold voltage, thereby switching the first node The source voltage of the second node N2, which changes by following the gate voltage of N1, is stored in the sensing capacitor Cx of the sensing voltage readout line 14B.

During the image display operation, the second switching transistor ST2 switches the current flow between the second node N2 and the sensing voltage readout line 14B in response to the second gate signal SEN for displaying the image, so that the driving transistor ( DT) resets the source voltage to the initialization voltage Vpre. The gate electrode of the second switching transistor ST2 is connected to the second gate line 15B, the drain electrode of the second switching transistor ST2 is connected to the second node N2, and the second switching transistor ST2 is connected to the second node N2. A source electrode of , is connected to the sensing voltage readout line 14B.

The data driving circuit 12 is connected to the sub-pixel SP through a data voltage supply line 14A and a sensing voltage readout line 14B. A sensing capacitor Cx for storing the source voltage of the second node N2 as the sensing voltage Vsen is connected to the sensing voltage readout line 14B. The data driving circuit 12 includes a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), an initialization switch (SW1), and a sampling switch (SW2).

The DAC may generate the threshold voltage sensing data voltage Vdata at the same level or different levels in the first and second sections of the sensing section under the control of the timing controller 11 and output it to the data voltage supply line 14A. have. The DAC may output the image data MDATA compensated in the image display period under the control of the timing controller 11 as the data voltage Vdata for image display to the data voltage supply line 14A.

The initialization switch SW1 switches a current flow between the initialization voltage Vpre input terminal and the sensing voltage readout line 14B. The sampling switch SW2 switches the current flow between the sensing voltage readout line 14B and the ADC. The ADC supplies the analog sensing voltage Vsen stored in the sensing capacitor Cx to the timing controller 11 based on a sensing value that is a digital value.

The sensing operation process performed under the control of the timing controller 11 is as follows. When the first and second gate signals SCAN and SEN for threshold voltage sensing are applied to the sub-pixel SP at the on level Lon for the sensing operation, the first switching transistor ST1 and the second switching transistor ST2 ) is turned on. At this time, the initialization switch SW1 in the data driving circuit 12 is also turned on.

When the first switching transistor ST1 is turned on, the threshold voltage sensing data voltage Vdata is supplied to the first node N1. When the initialization switch SW1 and the second switching transistor ST2 are turned on, the initialization voltage Vpre is supplied to the second node N2. At this time, the gate-source voltage Vgs of the driving transistor DT is greater than the threshold voltage Vth, and a current Ioled flows between the drain and the source of the driving transistor DT. The source voltage VN2 of the driving transistor DT charged in the second node N2 by the current Ioled gradually increases, and accordingly, the gate-source voltage Vgs of the driving transistor DT decreases. The source voltage VN2 of the driving transistor DT tracks the gate voltage VN1 of the driving transistor DT until the threshold voltage Vth is reached.

The source voltage VN2 of the driving transistor DT increased at the second node N2 is applied to the sensing capacitor Cx formed in the sensing voltage readout line 14B via the second switching transistor ST2 to the sensing voltage ( Vsen). The sensing voltage Vsen is detected and supplied to the ADC when the sampling switch SW2 in the data driving circuit 12 is turned on within a sensing period in which the threshold voltage sensing second gate signal SEN is maintained at the on level. .

The ADC supplies the analog sensing voltage Vsen stored in the sensing capacitor Cx to the timing controller 11 based on a sensing value that is a digital value.

In one embodiment of the present specification, the timing controller 11 performs a data driving circuit 12 such that a sensing operation for one horizontal line is performed after one frame of image data is displayed by an image display operation and before the next frame is displayed. and the gate driving circuit 13 .

The timing controller 11 compensates the image data DATA based on the sensed value obtained by the data driving circuit 12 to generate the compensated image data MDATA. As the compensated image data MDATA is supplied to the data driving circuit 12 , a high-quality image based on the compensated image data MDATA is displayed on the display panel 10 .

Meanwhile, when the sensed value obtained by the data driving circuit 12 is an abnormal value, the deterioration state of the sub-pixel SP is not accurately reflected in the image data MDATA compensated based on the sensed value. When the image data MDATA in which the deterioration state of the sub-pixel SP is not accurately reflected is supplied to the data driving circuit 12 , a low-quality image is displayed on the display panel 10 . Hereinafter, embodiments for minimizing the time for which a low-quality image is displayed on the display panel 10 when the sensed value obtained by the data driving circuit 12 is an abnormal value will be described.

4 illustrates a configuration of a display device and a connection relationship with a host system according to an exemplary embodiment of the present specification.

Referring to FIG. 4 , a display device 1 according to an exemplary embodiment of the present specification includes a display panel 10 , a timing controller 11 , a data driving circuit 12 , a data line 14 , and a power management circuit 16 . ) is included. Although not shown, the display device 1 may further include a gate driving circuit and a gate line.

The display panel 10 includes a plurality of sub-pixels SP as shown in FIG. 3 .

The data driving circuit 12 performs an image display operation or a sensing operation of the display panel 10 according to the control of the timing controller 11 . The data driving circuit 12 acquires a sensing value Vsen of each sub-pixel SP included in the display panel 10 through a sensing operation. The data driving circuit 12 transmits the acquired sensing value Vsen of each sub-pixel SP to the timing controller 11 .

The timing controller 11 determines whether the sensed value Vsen obtained by the data driving circuit 12 is a normal value.

In one embodiment of the present specification, the timing controller 11 may compare the sensed value of each sub-pixel SP with a predetermined reference value, and determine whether the sensed value Vsen is a normal value according to the comparison result. .

For example, the timing controller 11 compares the maximum value of the threshold voltage of each sub-pixel SP with the sensed value of each sub-pixel SP, and the sub-pixel SP whose sensed value exceeds the maximum value of the threshold voltage. ) can be counted (k). When the number k of sub-pixels SP for which the sensed value exceeds the maximum value of the threshold voltage is greater than or equal to a predetermined reference number (eg, 10), the timing controller 11 obtains data obtained by the data driving circuit 12 . It may be determined that the sensed value Vsen is abnormal. Conversely, the timing controller 11 obtains by the data driving circuit 12 when the number k of the sub-pixels SP for which the sensed value exceeds the maximum value of the threshold voltage is less than a predetermined reference number (eg, 10). It can be determined that the sensed value Vsen is normal.

However, the method by which the timing controller 11 determines whether the sensed value Vsen is normal is not limited thereto, and it may be determined whether the sensed value Vsen is normal by other known methods. In addition, in another embodiment of the present specification, when it is determined whether the sensed value Vsen is normal, a reference value other than the maximum value of the threshold voltage may be used.

The timing controller 11 transmits the internal power control signal INBDP to the power management circuit 16 based on a result of determining whether the sensed value Vsen is normal. In one embodiment of the present specification, the internal power control signal INBDP includes an internal power-on signal and an internal power-off signal. For example, the internal power-on signal may be a high voltage level signal, and the internal power-off signal may be a low voltage level signal.

The power management circuit 16 supplies the first base voltage EVSS1 to the display panel 10 based on the input voltage Vin supplied from the host system 2 . Although not shown, the power management circuit 16 supplies the driving voltage EVDD together with the first base voltage EVSS1 to the display panel 10 based on the input voltage Vin supplied from the host system 2 . .

Here, the first base voltage EVSS1 refers to a voltage capable of emitting light from the light emitting device (eg, OLED) included in the sub-pixel SP together with the driving voltage EVDD. A ground voltage may be used as an example of the first base voltage EVSS1.

In addition, the power management circuit 16 transmits the external power control signal BDP to the host system 2 based on the internal power control signal INBDP transmitted from the timing controller 11 . In one embodiment of the present specification, the external power control signal BDP includes an external power on signal and an external power off signal. For example, the external power-on signal may be a low voltage level signal, and the external power-off signal may be a high voltage level signal.

The host system 2 supplies the input voltage Vin to the power management circuit 16 . In the exemplary embodiment of the present specification, whether to supply the input voltage Vin to the power management circuit 16 is determined based on the external power control signal BDP transmitted from the power management circuit 16 . For example, when an external power-on signal of a low voltage level is supplied, the host system 2 supplies the input voltage Vin to the power management circuit 16 . However, when an external power-off signal of a high voltage level is supplied, the host system 2 does not supply the input voltage Vin to the power management circuit 16 .

The operation process of the display device 1 shown in FIG. 4 is as follows.

When the input voltage Vin is supplied from the host system 2 to the power management circuit 16 , the display device 1 is driven. The sensing value Vsen of each sub-pixel SP included in the display panel 10 is obtained by the data driving circuit 12 . The data driving circuit 12 transmits the sensing value Vsen of each sub-pixel SP to the timing controller 11 .

The timing controller 11 determines whether the sensed value Vsen obtained by the data driving circuit 12 is a normal value.

When the sensed value Vsen obtained by the data driving circuit 12 is determined to be a normal value, the timing controller 11 transmits an internal power-on signal to the power management circuit 16 .

Upon receiving the internal power-on signal, the power management circuit 16 transmits an external power-on signal to the host system 2 .

Upon receiving the external power-on signal, the host system 2 continuously supplies the input voltage Vin to the power management circuit 16 . Accordingly, since the driving voltage EVDD and the first base voltage EVSS1 are supplied to the display panel 10 , an image is displayed on the display panel 10 .

Meanwhile, when it is determined that the sensed value Vsen obtained by the data driving circuit 12 is an abnormal value, the timing controller 11 transmits an internal power-off signal to the power management circuit 16 .

Upon receiving the internal power-off signal, the power management circuit 16 transmits an external power-off signal to the host system 2 .

Upon receiving the external power-off signal, the host system 2 stops supplying the input voltage Vin to the power management circuit 16 . Accordingly, since the driving voltage EVDD and the first base voltage EVSS1 are not supplied to the display panel 10 , an image is not displayed on the display panel 10 .

According to the above-described exemplary embodiment, when the sensed value Vsen obtained by the data driving circuit 12 is abnormal, the power supply from the host system 2 is stopped and the driving of the display panel 10 is stopped. Accordingly, the user does not view an abnormal image based on the abnormal sensing value Vsen.

Meanwhile, according to the above-described embodiment, after the timing controller 11 determines that the sensed value Vsen is abnormal, the power management circuit 16 receives the internal power-off signal and sends the external power to the host system 2 . The driving of the display panel 10 is stopped only when a power-off signal is transmitted. Accordingly, the display panel 10 is driven to expose an abnormal image to the user during a time during which an internal power-off signal is transmitted and a time during which an external power-off signal is transmitted.

Hereinafter, an embodiment in which an abnormal image is exposed to the user after a point in time when the sensed value Vsen is determined to be abnormal will be described.

5 illustrates a configuration of a display device and a connection relationship with a host system according to another exemplary embodiment of the present specification.

Referring to FIG. 5 , a display device 1 according to an exemplary embodiment of the present specification includes a display panel 10 , a timing controller 11 , a data driving circuit 12 , a data line 14 , and a power management circuit 16 . ), and a second base voltage supply circuit 17 . Although not shown, the display device 1 may further include a gate driving circuit and a gate line.

The display panel 10 includes a plurality of sub-pixels SP as shown in FIG. 3 .

The data driving circuit 12 performs an image display operation or a sensing operation of the display panel 10 according to the control of the timing controller 11 . The data driving circuit 12 acquires a sensing value Vsen of each sub-pixel SP included in the display panel 10 through a sensing operation. The data driving circuit 12 transmits the acquired sensing value Vsen of each sub-pixel SP to the timing controller 11 .

The timing controller 11 determines whether the sensed value Vsen obtained by the data driving circuit 12 is a normal value.

In one embodiment of the present specification, the timing controller 11 may compare the sensed value of each sub-pixel SP with a predetermined reference value, and determine whether the sensed value Vsen is a normal value according to the comparison result. .

For example, the timing controller 11 compares the maximum value of the threshold voltage of each sub-pixel SP with the sensed value of each sub-pixel SP, and the sub-pixel SP whose sensed value exceeds the maximum value of the threshold voltage. ) can be counted (k). When the number k of sub-pixels SP for which the sensed value exceeds the maximum value of the threshold voltage is greater than or equal to a predetermined reference number (eg, 10), the timing controller 11 obtains data obtained by the data driving circuit 12 . It may be determined that the sensed value Vsen is abnormal. Conversely, the timing controller 11 obtains by the data driving circuit 12 when the number k of the sub-pixels SP for which the sensed value exceeds the maximum value of the threshold voltage is less than a predetermined reference number (eg, 10). It can be determined that the sensed value Vsen is normal.

However, the method by which the timing controller 11 determines whether the sensed value Vsen is normal is not limited thereto, and it may be determined whether the sensed value Vsen is normal by other known methods. In addition, in another embodiment of the present specification, when it is determined whether the sensed value Vsen is normal, a reference value other than the maximum value of the threshold voltage may be used.

The timing controller 11 transmits the internal power control signal INBDP to the power management circuit 16 based on a result of determining whether the sensed value Vsen is normal.

As shown in FIG. 5 , the internal power control signal output from the timing controller 11 is supplied to the power management circuit 16 and the second base voltage supply circuit 17 through the internal power control signal supply node NC1 . .

The power management circuit 16 supplies the first base voltage EVSS1 or the second base voltage EVSS2 to the display panel 10 based on the input voltage Vin supplied from the host system 2 . The first base voltage EVSS1 is directly supplied to the display panel 10 , but the second base voltage EVSS2 is supplied to the display panel 10 through the second base voltage supply circuit 17 . Although not shown, the power management circuit 16 provides the display panel 10 with the first base voltage EVSS1 or the second base voltage EVSS2 based on the input voltage Vin supplied from the host system 2 . A driving voltage EVDD is supplied.

Here, the first base voltage EVSS1 refers to a voltage capable of emitting light from the light emitting device (eg, OLED) included in the sub-pixel SP together with the driving voltage EVDD. A ground voltage may be used as an example of the first base voltage EVSS1.

In addition, the second base voltage EVSS2 refers to a voltage at which the light emitting device (eg, OLED) included in the sub-pixel SP cannot emit light. The second base voltage EVSS2 may be set to a higher voltage value than the first base voltage EVSS1 , and may be set differently according to a threshold voltage value of the light emitting device (eg, OLED).

In addition, the power management circuit 16 transmits the external power control signal BDP to the host system 2 based on the internal power control signal INBDP transmitted from the timing controller 11 . In one embodiment of the present specification, the external power control signal BDP includes an external power on signal and an external power off signal. For example, the external power-on signal may be a low voltage level signal, and the external power-off signal may be a high voltage level signal.

The power management circuit 16 outputs the first base voltage EVSS1 or the second base voltage EVSS2 under the control of the timing controller 11 . In the exemplary embodiment of the present specification, the second base voltage supply circuit 17 outputs the first base voltage EVSS1 when the internal power-on signal is transmitted from the timing controller 11 , and the internal power supply from the timing controller 11 . When the off signal is transmitted, the second base voltage EVSS2 may be output. The first base voltage EVSS1 is directly supplied to the display panel 10 , and the second base voltage EVSS2 is supplied to the second base voltage supply node NC2 .

The second base voltage supply circuit 17 supplies the second base voltage EVSS2 to the display panel 10 according to the control of the timing controller 11 .

As shown in FIG. 5 , the second base voltage supply circuit 17 includes a resistor R, a diode D, a capacitor C, and a switching element SC.

The resistor R and the diode D are connected between the power management circuit 16 and the second base voltage supply node NC2. Also, the resistor R and the diode D are connected in series with each other.

The capacitor C is connected between the second base voltage supply node NC2 and the ground node.

The switching element SC is connected between the second base voltage supply node NC2 and the ground node. A first electrode (eg, a source electrode) of the switching element SC is connected to the second ground voltage supply node NC2 , and a second electrode (eg, a drain electrode) is connected to a ground node. A third electrode (eg, a gate electrode) of the switching element SC is connected to the internal power supply control signal supply node NC1 .

In the exemplary embodiment of the present specification, the switching element SC is turned on or off by the internal power control signal INBDP supplied to the third electrode. For example, when an internal power-on signal of a high voltage level is supplied to the third electrode of the switching element SC, the switching element SC is turned on. In addition, when an internal power-off signal of a low voltage level is supplied to the third electrode of the switching element SC, the switching element SC is turned off.

When the switching element SC is turned on, the second base voltage supply node NC2 is connected to the ground node, and thus the base voltage is not supplied to the display panel 10 . However, when the switching element SC is turned off, since the second base voltage supply node NC2 is electrically connected to the display panel 10 , the first base voltage supply node NC2 supplied to the display panel 10 is supplied to the display panel 10 . Two base voltage EVSS2 may be supplied.

The host system 2 supplies the input voltage Vin to the power management circuit 16 . In the exemplary embodiment of the present specification, whether to supply the input voltage Vin to the power management circuit 16 is determined based on the external power control signal BDP transmitted from the power management circuit 16 . In one embodiment of the present specification, the external power control signal BDP includes an external power on signal and an external power off signal. For example, the external power-on signal may be a low voltage level signal, and the external power-off signal may be a high voltage level signal.

For example, when an external power-on signal of a low voltage level is supplied, the host system 2 supplies the input voltage Vin to the power management circuit 16 . However, when an external power-off signal of a high voltage level is supplied, the host system 2 does not supply the input voltage Vin to the power management circuit 16 .

An operation process of the display device 1 shown in FIG. 5 is as follows.

The sensing value Vsen of each sub-pixel SP included in the display panel 10 is obtained by the data driving circuit 12 . The data driving circuit 12 transmits the sensing value Vsen of each sub-pixel SP to the timing controller 11 .

The timing controller 11 determines whether the sensed value Vsen obtained by the data driving circuit 12 is a normal value.

When the sensed value Vsen obtained by the data driving circuit 12 is determined to be a normal value, the timing controller 11 performs the power management circuit 16 and the second base voltage through the internal power control signal supply node NC1. An internal power-on signal is transmitted to each of the supply circuits 17 .

When receiving the internal power-on signal, the power management circuit 16 outputs the first base voltage EVSS1 and does not output the second base voltage EVSS2 .

Also, when an internal power-on signal is supplied to the third electrode (eg, the gate electrode) of the switching element SC of the second base voltage supply circuit 17 , the switching element SC is turned on. Accordingly, since the second base voltage supply node NC2 is connected to the ground node, the supply of the second base voltage EVSS2 to the display panel 10 is completely cut off.

When the internal power-on signal is supplied to the third electrode (eg, the gate electrode) of the switching element SC, the second base voltage EVSS2 is not output from the second base voltage supply circuit 17 , but the switching element SC By turning on , the second base voltage EVSS2 is not supplied to the panel more reliably.

That is, since the second base voltage output node of the second base voltage supply circuit 17 is always connected to the display panel 10 , the display panel 10 may be generated in an emergency by turning on the switching element SC. ) can be cut off even a weak current supply.

Also, upon receiving the internal power-on signal, the power management circuit 16 transmits an external power-on signal to the host system 2 .

Upon receiving the external power-on signal, the host system 2 supplies the input voltage Vin to the power management circuit 16 . Accordingly, since the driving voltage EVDD and the first base voltage EVSS1 are supplied to the display panel 10 , an image is displayed on the display panel 10 .

On the other hand, when it is determined that the sensed value Vsen obtained by the data driving circuit 12 is an abnormal value, the timing controller 11 performs the power management circuit 16 and the second control signal through the internal power control signal supply node NC1. An internal power-off signal is transmitted to each of the base voltage supply circuits 17 .

Upon receiving the internal power-off signal, the power management circuit 16 outputs the second base voltage EVSS2 and does not output the first base voltage EVSS1.

Also, when the internal power-off signal is supplied to the third electrode (eg, the gate electrode) of the switching element SC of the second base voltage supply circuit 17 , the switching element SC is turned off. Accordingly, since the second base voltage supply node NC2 is electrically connected to the display panel 10 , the second base voltage EVSS2 is supplied to the display panel 10 through the second base voltage supply node NC2 . .

When the second base voltage EVSS2 is supplied to the display panel 10 , the light-emitting operation of each sub-pixel SP included in the display panel 10 is immediately stopped. That is, according to another exemplary embodiment of the present specification, even when power is being supplied to the display device 1 from the host system 2 , the image display of the display panel 10 is immediately stopped by the supply of the second base voltage EVSS2 . .

Meanwhile, upon receiving the internal power-off signal, the power management circuit 16 transmits an external power-off signal to the host system 2 .

Upon receiving the external power-off signal, the host system 2 stops supplying the input voltage Vin to the power management circuit 16 . Accordingly, the supply of the driving voltage EVDD and the second base voltage EVSS2 to the display panel 10 is stopped.

According to the above-described embodiment, when the sensed value Vsen obtained by the data driving circuit 12 is abnormal, the second base voltage EVSS2 is transmitted to the display panel 10 by the second base voltage supply circuit 17 . When this is supplied, the image display on the display panel 10 is immediately stopped. Accordingly, the user does not view an abnormal image based on the abnormal sensing value Vsen.

Meanwhile, according to the embodiment of FIG. 4 , after the timing controller 11 determines that the sensed value Vsen is abnormal, the power management circuit 16 receives the internal power-off signal and sends it to the host system 2 . The driving of the display panel 10 is stopped only when an external power-off signal is transmitted. Accordingly, during the time during which the internal power-off signal is transmitted and the time during which the external power-off signal is transmitted, the display panel 10 is driven to expose an abnormal image to the user.

However, according to the embodiment of FIG. 5 , the internal power-off signal output from the timing controller 11 after a point in time when the sensed value Vsen is determined to be abnormal by the timing controller 11 is applied to the second base voltage supply circuit 17 . is supplied to the display panel 10 , the second base voltage EVSS2 is supplied to the display panel 10 , and the image display of the display panel 10 is immediately stopped. Accordingly, compared to the embodiment of FIG. 4 , the time taken from the point in time when the sensed value Vsen is determined to be abnormal by the timing controller 11 to the point in time when the image display of the display panel 10 is stopped is reduced. Accordingly, there is an advantage in that the time the abnormal image is exposed to the user is further shortened.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in the present specification are for explanation rather than limiting the technical spirit of the present specification, and the scope of the technical spirit of the present specification is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present specification should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present specification.

Claims (16)

A display panel comprising: a display panel including a plurality of sub-pixels disposed at intersections of a plurality of data lines and a plurality of gate lines;
a data driving circuit for driving the plurality of data lines;
a gate driving circuit for driving the plurality of gate lines;
a timing controller controlling driving of the data driving circuit and the gate driving circuit;
a power management circuit for outputting a first base voltage or a second base voltage based on power supplied from the host system; and
a second base voltage supply circuit supplying a second base voltage supplied from the power management circuit to the display panel;
the timing controller
determining whether the sensed value obtained by the data driving circuit is normal, and controlling the driving of the second base voltage supply circuit according to the determination result
display device.
According to claim 1,
the timing controller
When it is determined that the sensed value is normal, an internal power-on signal is transmitted to the second base voltage supply circuit,
When it is determined that the sensed value is abnormal, an internal power-off signal is transmitted to the second base voltage supply circuit.
display device.
The second base voltage supply circuit is
supplying the second base voltage to the display panel upon receiving the internal power-off signal
display device.
According to claim 1,
The second base voltage supply circuit is
A first electrode is connected to the second base voltage supply node, the second electrode is connected to the ground terminal, and the third electrode is connected to the internal power supply control signal supply node including a switching element
display device.
5. The method of claim 4,
The switching element is
Turned on by an internal power-on signal supplied to the third electrode or turned off by an internal power-off signal supplied to the third electrode
display device.
5. The method of claim 4,
When the switching element is turned on, the second base voltage is not supplied to the display panel;
When the switching element is turned off, the second base voltage is supplied to the display panel.
display device.
According to claim 1,
When the second base voltage is supplied to the display panel, light emission of the sub-pixels is stopped.
display device.
According to claim 1,
the timing controller
When it is determined that the sensed value is normal, an internal power-on signal is transmitted to the power management circuit,
When it is determined that the sensed value is abnormal, an internal power-off signal is transmitted to the power management circuit.
display device.
9. The method of claim 8,
The power management circuit is
supplying the second base voltage to the second base voltage supply circuit upon receiving the internal power-off signal
display device.
9. The method of claim 8,
The power management circuit is
When receiving the internal power-off signal, an external power-off signal is transmitted to the host system;
the host system
to stop supplying power to the power management circuit upon receiving the external power-off signal
display device.
A display panel comprising: a display panel including a plurality of sub-pixels disposed at intersections of a plurality of data lines and a plurality of gate lines;
a data driving circuit for driving the plurality of data lines;
a gate driving circuit for driving the plurality of gate lines;
a timing controller controlling driving of the data driving circuit and the gate driving circuit;
a power management circuit for outputting a first base voltage or a second base voltage based on power supplied from the host system; and
a second base voltage supply circuit configured to supply a second base voltage supplied from the power management circuit to the display panel under the control of the timing controller;
The second base voltage supply circuit is
supplying the second base voltage to the display panel when the sensed value obtained by the data driving circuit is abnormal
display device.
12. The method of claim 11,
When the second base voltage is supplied to the display panel, light emission of the sub-pixels is stopped.
display device.
12. The method of claim 11,
The second base voltage supply circuit is
A first electrode is connected to the second base voltage supply node, the second electrode is connected to the ground terminal, and the third electrode is connected to the internal power supply control signal supply node including a switching element
display device.
14. The method of claim 13,
When the sensed value is abnormal, an internal power-off signal is supplied through the third electrode to turn off the switching element,
When the switching element is turned off, the second base voltage is supplied to the display panel.
display device.
12. The method of claim 11,
The power management circuit is
supplying the second base voltage to the second base voltage supply circuit when the sensed value is abnormal
display device.
12. The method of claim 11,
The power management circuit is
When the sensed value is abnormal, an external power-off signal is transmitted to the host system,
the host system
to stop supplying power to the power management circuit upon receiving the external power-off signal
display device.

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