KR20220056592A - Display device - Google Patents

Abstract

According to an embodiment of the present specification, a display device comprises: a substrate including a plurality of sub-pixels and having a thin film transistor disposed for each sub-pixel; a protective layer disposed on the thin film transistor; an organic material layer disposed on the protective layer; an inorganic material layer disposed on the organic material layer and spaced apart from each other based on a first direction; a first electrode disposed on the inorganic material layer and positioned on a side inner than an end of the inorganic material layer; a bank disposed to cover an edge of the first electrode and protrude from the end of the inorganic material layer; a light emitting layer disposed on the bank and the first electrode and disconnected based on the first direction; and a second electrode disposed on the light emitting layer. Therefore, the display device can prevent a leakage current between a plurality of sub-pixels.

Description

display device {DISPLAY DEVICE}

The present specification relates to a display device for displaying an image.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, in recent years, quantum dot light emitting display (QLED: Quantum dot Light Emitting Display), inorganic light emitting display device, organic light emitting display device (OLED, Organic Light Emitting Display), and micro-LED display (Micro-LED Display) and The same various display devices are being used.

Among display devices, organic light emitting displays, quantum dot light emitting displays, inorganic light emitting displays, and micro LED displays are self-emissive and have superior viewing angles and contrast ratios compared to conventional liquid crystal displays (LCDs). It does not require a backlight, so it can be lightweight and thin, and has the advantage of advantageous power consumption. In addition, the self-emission type display device can be driven with a low direct current voltage, has a fast response speed, and has the advantages of low manufacturing cost.

Among self-emission type display devices, an organic light emitting display device may be formed in a tandem structure of two or more stacks in which two or more light emitting layers are stacked. In this case, the emission layer formed in the tandem structure may be extended to form a common layer in the plurality of sub-pixels. Current may leak due to the common emission layer extending from one sub-pixel to an adjacent sub-pixel. As described above, in the organic light emitting diode display including the light emitting layer formed as a common layer, color reproducibility may be deteriorated due to leakage current.

An object of the present specification is to provide a display device capable of preventing a leakage current from occurring between a plurality of sub-pixels.

A display device according to an exemplary embodiment of the present specification includes a substrate including a plurality of sub-pixels and on which a thin film transistor is disposed for each sub-pixel, a protective layer disposed on the thin film transistor, an organic material layer disposed on the protective layer, and an organic An inorganic material layer disposed on the material layer and spaced apart from each other in the first direction, a first electrode disposed on the inorganic material layer and positioned inside the end of the inorganic material layer, and covering the edges of the first electrode, The bank may include a bank disposed to protrude from an end of the inorganic material layer, an emission layer disposed on the bank and the first electrode and cut off in the first direction, and a second electrode disposed on the emission layer.

According to the present specification, by having the undercut structure on one side of the bank provided between the plurality of sub-pixels, the charge generating layer may be disconnected without being connected between the sub-pixels emitting light of different colors. Accordingly, according to the present specification, it is possible to prevent a leakage current from occurring between sub-pixels emitting light of different colors.

In the present specification, the inorganic material layer added to form the undercut structure of the bank may be formed under the first electrode of the light emitting device without using a separate mask. In addition, an undercut structure of the bank 118 may be formed using the inorganic material layer formed under the first electrode. Accordingly, in the present specification, there is an advantage that a separate mask process is not added in forming a bank having an undercut structure in order to prevent a leakage current from occurring between sub-pixels having different colors. Accordingly, the process can be simplified and the production cost can be reduced.

In addition to the effects of the present specification mentioned above, other features and advantages of the present specification will be described below or will be clearly understood by those of ordinary skill in the art to which this specification belongs from the description and description.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present specification.
FIG. 2 is a circuit diagram of any one sub-pixel among a plurality of sub-pixels included in the pixel P shown in FIG. 1 .
FIG. 3 is a plan view showing the structure in the pixel P shown in FIG. 1 .
4 is a cross-sectional view taken along line II′ of FIG. 3 .
5A to 5F are cross-sectional views taken along line II′ of FIG. 3 and are cross-sectional views illustrating a manufacturing process.

Advantages and features of the present specification, and a method of achieving them, will become apparent with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the examples disclosed below, but will be implemented in various different forms, and only these examples allow the disclosure of the present specification to be complete, and to those of ordinary skill in the art to which this specification belongs It is provided to fully indicate the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the examples of the present specification are illustrative and the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

In describing the components of the present specification, terms such as first and second may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

Each of the features of the various examples of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

Hereinafter, an example of a display device according to the present specification will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present specification.

As shown in FIG. 1 , the display device 100 according to an embodiment of the present specification may include a display panel 110 , a gate driver 120 , a data driver 130 , and a controller 140 . . Also, the display panel 110 may include a display area DA displaying information and a non-display area NDA not displaying information.

The display panel 110 may include gate lines GL, data lines DL, and a pixel P disposed in an area where the gate lines GL and the data lines DL intersect. The pixel P includes a display element and a pixel driver PDC for driving the display element. An image may be displayed on the display panel 110 by driving the pixel P

The controller 140 may control the gate driver 120 and the data driver 130 .

The controller 140 controls the gate control signal GCS and the data driver 130 for controlling the gate driver 120 using a vertical/horizontal synchronization signal and a clock signal supplied from an external system (not shown). It is possible to output a data control signal DCS for Also, the controller 140 may supply the image data RGB to the data driver 130 by sampling input image data input from an external system and rearranging it.

The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Also, the gate control signal GCS may include control signals for controlling the shift register.

The data control signal DCS may include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

The data driver 130 may supply a data voltage to the data lines DL1 to DLn of the display panel 110 . Specifically, the data driver 130 may convert the image data RGB input from the controller 140 into a data voltage and supply the data voltage to the data lines DL.

The gate driver 120 may sequentially supply the gate pulse GP to the gate lines GL1 to GLn: GL for one frame. Here, one frame refers to a period in which one image is output through the display panel 110 . Also, the gate driver 120 may supply a gate-off signal Goff capable of turning off the switching device to the gate line GL during the remaining period in which the gate pulse GP is not supplied during one frame. Hereinafter, the gate pulse GP and the gate-off signal Goff are collectively referred to as a scan signal SS.

According to an exemplary embodiment of the present specification, the gate driver 120 may be mounted on the display panel 110 . As described above, a structure in which the gate driver 120 is directly mounted on the display panel 110 is referred to as a gate in panel (GIP) structure.

FIG. 2 is a circuit diagram of any one sub-pixel among a plurality of sub-pixels included in the pixel P shown in FIG. 1 .

Referring to FIG. 2 , the display panel 110 of the display device 100 according to the exemplary embodiment of the present disclosure may include a pixel driver PDC and a light emitting device 400 connected to the pixel driver PDC. there is.

The circuit diagram of FIG. 2 is an equivalent circuit diagram of one sub-pixel SP disposed in one pixel P of the display device 100 including a light emitting diode (LED) as the light emitting element 400 .

The pixel driver PDC of FIG. 2 may include a switching transistor STr and a driving transistor DTr. As shown in FIG. 2 , the switching transistor STr may be connected to the gate line GL and the data line DL. In addition, the switching transistor STr may be turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL may provide the data voltage Vdata to the pixel driver PDC, and the switching thin film transistor STr may apply the data voltage Vdata.

The power wiring PL provides the driving voltage Vdd to the light emitting device 400 , and the driving thin film transistor DTr may control the driving voltage Vdd. Here, the driving voltage Vdd is a pixel driving voltage for driving the light emitting device 400 .

The data line DL and the power line PL are lines that transmit signals. Accordingly, according to an exemplary embodiment of the present specification, the data line DL and the power line PL are referred to as signal lines. In addition, since the gate line GL also transmits a signal, it may be referred to as a signal line.

When the switching thin film transistor STr is turned on, the data voltage Vdata supplied through the data line DL may be supplied to the gate electrode of the driving thin film transistor DTr connected to the light emitting device 400 . The data voltage Vdata may be charged in the storage capacitor Cst formed between the gate electrode G and the drain electrode D of the driving thin film transistor DTr.

The amount of current supplied to the light emitting device 400 through the driving thin film transistor DTr may be controlled by the data voltage Vdata. Also, the grayscale of the light output from the light emitting device 400 may be controlled by the data voltage Vdata.

FIG. 3 is a plan view schematically illustrating a structure in the pixel P shown in FIG. 1 . FIG. 3 is a plan view schematically illustrating the structure of a plurality of sub-pixels formed in the pixel P shown in FIG. 1 .

And, FIG. 4 is a cross-sectional view taken along line I-I' of FIG. 3 . FIG. 4 is a cross-sectional view schematically illustrating a structure of a pixel P of a display device according to an exemplary embodiment of the present specification, taken along the cut line II′ of FIG. 3 .

Referring to FIG. 3 , the display device 100 according to an exemplary embodiment of the present specification includes a pixel P, a data line DL, a gate line GL, a power supply line PL, and a first thin film transistor 200 . , a second thin film transistor 300 , and a light emitting device 400 may be included.

1 and 3 , a data line DL and a gate line GL crossing the data line DL may be disposed on the substrate 110 . In addition, a plurality of pixels P arranged in a matrix form and displaying an image may be disposed at the intersection of the data line DL and the gate line GL. The pixel P may include a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 . In addition, each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 may include an emission area EA and a non-emission area.

The first sub-pixel SP1 may be a red pixel, and the second sub-pixel SP2 may be a green pixel. And, the third sub-pixel SP3 may be a blue pixel. The first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 may be disposed adjacent to each other in the first direction (X-axis direction). In addition, sub-pixels of the same color may be disposed adjacent to each other in the second direction (Y-axis direction). Each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 is the light emitting device 400 according to the data voltage of the data line DL when the gate signal of the gate line GL is input. ) can be supplied with a predetermined current. Accordingly, each of the light emitting devices 400 of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 may emit light with a predetermined brightness according to a predetermined current. In addition, a power voltage may be supplied to the power line PL. In addition, the power line PL may supply a power voltage to each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 .

3 and 4 , the light emitting area EA may be an area from which the light emitting layer 412 of the light emitting device 400 emits light. In addition, the light emitting area EA may be defined by an open area of the bank 118 . The light emitting area EA will be described later in detail with reference to FIG. 4 .

In FIG. 3 , for convenience of explanation, each of the sub-pixels SP1, SP2, and SP3 is illustrated as being positioned side by side with the same width, but each of the sub-pixels SP1, SP2, and SP3 has various structures with different widths. can have

In addition, the first thin film transistor 200 and the second thin film transistor 300 may be disposed in the non-emission area NEA of the sub-pixels SP1 , SP2 , and SP3 . In addition, the light emitting device 400 including the first electrode 411 , the light emitting layer 412 , and the second electrode 412 may be disposed on the light emitting area EA of each of the sub-pixels SP1 , SP2 , and SP3 , respectively. there is.

The first thin film transistor 200 may be a switching thin film transistor STr. Also, the second thin film transistor 300 may be a driving thin film transistor DTr. The first thin film transistor 200 and the second thin film transistor 300 may be connected to each other, and the second thin film transistor 300 may be connected to the light emitting device 400 . For example, as shown in FIG. 3 , the first drain electrode 213 of the first thin film transistor 200 may be connected to the second gate electrode 311 of the second thin film transistor 300 . In addition, the second drain electrode 313 of the second thin film transistor 300 may be connected to the first electrode 411 of the light emitting device 400 .

Referring to FIG. 3 , each sub-pixel SP1 , SP2 , and SP3 may be defined by the gate line GL, the data line DL, and the power line PL disposed on the substrate of the display panel 110 . can

The first thin film transistor 200 may be formed in a region where the gate line GL and the data line DL intersect. In addition, the first thin film transistor 200 may serve as a switching for applying a signal to each of the sub-pixels SP1 , SP2 , and SP3 . The first thin film transistor 200 may include a first gate electrode 211 , a first semiconductor layer 214 , a first source electrode 212 , and a first drain electrode 214 . In addition, the first gate electrode 211 of the first thin film transistor 200 may be connected to the gate line GL. Also, the first source electrode 212 of the first thin film transistor 200 may be connected to the data line DL.

Also, one side of the first semiconductor layer 214 of the first thin film transistor 200 may be connected to the first source electrode 212 of the first thin film transistor 200 through the first contact hole CH1 . The other side of the first semiconductor layer 214 may be connected to the first drain electrode 213 of the first thin film transistor 200 through the second contact hole CH2 .

The second thin film transistor 300 may serve to drive the light emitting device 400 of each sub-pixel SP1 , SP2 , and SP3 based on the signal applied by the first thin film transistor 200 . The second thin film transistor 300 may include a second gate electrode 311 , a second semiconductor layer 314 , a second source electrode 312 , and a second drain electrode 313 . In addition, the second gate electrode 311 of the second thin film transistor 300 may be connected to the first drain electrode 213 of the first thin film transistor 200 through the third contact hole CH3 . Also, the second source electrode 312 of the second thin film transistor 300 may be connected to the power supply line PL. In addition, the second drain electrode 313 of the second thin film transistor 300 may be connected to the first electrode 411 of the light emitting device 400 through the sixth contact hole CH6.

One side of the second semiconductor layer 314 of the second thin film transistor 300 may be connected to the second source electrode 312 of the second thin film transistor 300 through the fourth contact hole CH4 . The other side of the second semiconductor layer 314 may be connected to the second drain electrode 313 of the second thin film transistor 300 through the fifth contact hole CH5 .

Referring to FIG. 4 , the display device 100 according to the embodiment of the present specification includes a second thin film transistor 300 , a light emitting device 400 , an encapsulation unit 500 , a first sub-pixel SP1 , and a second sub-pixel. The pixel SP2 , the third sub-pixel SP3 , the dummy pattern 600 , the power line PL, the data line DL, the substrate 110 , the buffer layer 111 , the gate insulating layer 112 , and the interlayer insulation It may include a layer 113 , a first passivation layer 114 , a second passivation layer 115 , an organic material layer 116 , an inorganic material layer 117 , and a bank 118 .

The substrate 110 may support various components of the display device 100 . The substrate 110 may be made of a plastic material having flexibility. When the substrate 110 is made of a plastic material, it may be made of, for example, polyimide (PI).

Referring to FIG. 4 , a buffer layer 111 having a single-layer or multi-layer structure may be disposed on the substrate 110 . The buffer layer 111 disposed on the substrate 110 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The buffer layer 111 may improve the adhesion between the layers formed on the buffer layer 111 and the substrate 110 , and may serve to block alkali components leaking from the substrate 110 , and the like. In addition, the buffer layer 111 is not an essential component, and may be omitted based on the type and material of the substrate 110 , the structure and type of the thin film transistor, and the like.

Referring to FIG. 4 , in the non-emission area NEA of the pixel P, the second thin film transistor 300 may be disposed on the buffer layer 111 . The second thin film transistor 300 may include a second semiconductor layer 314 , a second gate electrode 311 , a second source electrode 312 , and a second drain electrode 313 . Here, according to the design of the circuit in the pixel P, the second source electrode 312 may be a drain electrode, and the second drain electrode 313 may be a source electrode. A second semiconductor layer 314 of the second thin film transistor 300 may be disposed on the buffer layer 111 of the substrate 110 .

The second semiconductor layer 314 may include poly-silicon. Since the polysilicon material has high mobility (100 cm 2 /Vs or more), low energy consumption, and excellent reliability, it can be applied to a gate driver and/or a multiplexer (MUX) for driving devices that drive thin film transistors for display devices, etc. , may be applied to the active layer of the driving thin film transistor in the display device according to the embodiment of the present specification, but is not limited thereto. For example, it may be applied as an active layer of a switching thin film transistor according to characteristics of a display device. Depositing an amorphous silicon (a-Si) material on the buffer layer 111 , performing a dehydrogenation process and a crystallization process to form polysilicon, and patterning the polysilicon to form the second semiconductor layer 314 . can The second semiconductor layer 314 includes a second channel region 314c in which a channel is formed when the second thin film transistor 300 is driven, a second source region 314s on both sides of the second channel region 314c, and a second A drain region 314d may be included. The second source region 314s is a portion of the second semiconductor layer 314 connected to the second source electrode 312 , and the second drain region 314d is a second semiconductor connected to the second drain electrode 313 . part of the layer 314 . The second source region 314s and the second drain region 314d may be formed by ion doping (impurity doping) of the second semiconductor layer 314 . The second source region 314s and the second drain region 314d may be formed by ion doping the polysilicon material, and the second channel region 314c may refer to a portion that is not ion-doped and is left as a polysilicon material. there is.

Also, the second semiconductor layer 314 may be formed of an oxide semiconductor. Since the oxide semiconductor material has a larger bandgap compared to the polysilicon material, electrons cannot cross the bandgap in the off state, and thus the off-current is low. Accordingly, a thin film transistor including an active layer made of an oxide semiconductor may be suitable for a switching thin film transistor having a short on time and a long off time, but is not limited thereto. Depending on the characteristics of the display device, it may be applied as a driving thin film transistor. And, since the off-current is small, the size of the storage capacitor can be reduced, which is suitable for a high-resolution display device. For example, the second semiconductor layer 314 may be formed of a metal oxide, for example, various metal oxides such as indium-gallium-zinc-oxide (IGZO). The second semiconductor layer 314 of the second thin film transistor 300 has been described as being formed based on the IGZO layer on the assumption that it is made of IGZO among various metal oxides, but is not limited thereto and is not limited thereto. oxide), indium-gallium-tin-oxide (IGTO), or other metal oxides such as indium-gallium-oxide (IGO). The second semiconductor layer 314 may be formed by depositing a metal oxide on the buffer layer 111 , performing a heat treatment process for stabilization, and then patterning the metal oxide.

In the display area DA of the substrate 110 , a gate insulating layer 112 may be disposed on the second semiconductor layer 314 of the second thin film transistor 300 . The gate insulating layer 112 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. In the gate insulating layer 112 , each of the second source electrode 312 and the second drain electrode 313 of the second thin film transistor 300 is a second layer of the second semiconductor layer 314 of the second thin film transistor 300 . A contact hole may be formed to be connected to each of the source region 314s and the second drain region 314d. In addition, the gate insulating layer 112 may not be disposed in the bending area BA of the substrate 110 . Also, the gate insulating layer 112 may not be disposed in the non-display area NDA of the substrate 110 .

The second gate electrode 311 of the second thin film transistor 300 and the gate line GL connected to the second gate electrode 311 may be disposed on the gate insulating layer 112 . The second gate electrode 311 and the gate line GL may include molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and It may consist of a single layer or multiple layers made of any one of neodymium (Nd) or an alloy thereof, but is not limited thereto. The second gate electrode 311 may be formed on the gate insulating layer 112 to overlap the second channel region 314c of the second semiconductor layer 314 of the second thin film transistor 300 .

A first interlayer insulating layer 113 may be disposed on the gate insulating layer 112 to cover the second gate electrode 311 and the gate line GL. The interlayer insulating layer 113 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

Referring to FIG. 4 , a contact hole for exposing the second semiconductor layer 314 of the second thin film transistor 300 may be formed in the gate insulating layer 112 and the interlayer insulating layer 113 . For example, a fourth contact hole CH4 for exposing the second source region 314s of the second semiconductor layer 314 may be formed. In addition, a fifth contact hole CH5 for exposing the second drain region 314d of the second semiconductor layer 314 may be formed.

A second source electrode 312 and a second drain electrode 313 of the second thin film transistor 300 may be disposed on the interlayer insulating layer 113 . The second source electrode 312 and the second drain electrode 313 of the second thin film transistor 300 are connected to the second thin film transistor 300 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113 . may be connected to the second semiconductor layer 314 of Accordingly, the second source electrode 312 of the second thin film transistor 300 is connected to the second semiconductor layer 314 through the fourth contact hole CH4 formed in the gate insulating layer 112 and the interlayer insulating layer 113 . It may be connected to the second source region 314s. In addition, the second drain electrode 313 of the second thin film transistor 300 is formed through the fifth contact hole CH5 formed in the gate insulating layer 112 and the interlayer insulating layer 113 of the second semiconductor layer 314 . It may be connected to the second drain region 314d. In addition, a power line PL and a data line DL may be disposed on the interlayer insulating layer 113 .

The power wiring PL, the data line DL, the second source electrode 312 and the second drain electrode 313 are formed of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), and chromium ( Cr), gold (Au), nickel (Ni), and neodymium (Nd) may be formed of a single layer or a multi-layer made of any one or an alloy thereof, but is not limited thereto. For example, the power line PL, the data line DL, the second source electrode 312 , and the second drain electrode 313 may be formed of a conductive metal material such as titanium (Ti)/aluminum (Al)/titanium (Ti). ) may have a three-layer structure.

In the non-emission area NEA of the substrate 110 , a first passivation layer 114 is disposed on the power line PL, the data line DL, the second source electrode 312 , and the second drain electrode 313 . can be The first passivation layer 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

A second passivation layer 115 may be disposed on the first passivation layer 114 . The second passivation layer 115 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto. The second protective layer 115 is formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. can be In the display device 100 , the second passivation layer 115 may not be disposed and only the first passivation layer 114 may be disposed.

Referring to FIG. 4 , an organic material layer 116 may be disposed on the second passivation layer 115 . In addition, the organic material layer 116 may be a layer for planarizing and protecting the upper portion of the third thin film transistor 300 . For example, the organic material layer 116 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. It may be formed of a material.

4 , an inorganic material layer 117 may be formed on the organic material layer 116 . The inorganic material layer 117 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

The inorganic material layer 117 , the organic material layer 116 , the second passivation layer 115 , and the first passivation layer 114 have a second drain electrode 313 for exposing the second thin film transistor 300 . 6 contact holes CH6 may be formed.

As shown in FIG. 4 , the inorganic material layer 117 may be patterned and disposed on the organic material layer 116 for each sub-pixel SP1 , SP2 , and SP3 . For example, one inorganic material layer 117 is formed in the first sub-pixel SP1, another inorganic material layer 117 is formed in the second sub-pixel SP2, and the third sub-pixel (SP2) Another inorganic material layer 117 may be formed on SP3).

Referring to FIG. 4 , a first inorganic material layer 117a is formed on the first sub-pixel SP1 , a second inorganic material layer 117b is formed on the second sub-pixel SP2 , and a third sub-pixel A third inorganic material layer 117c may be disposed on SP3 .

The first inorganic material layer 117a is disposed to correspond to the emission area EA of the first sub-pixel SP1 , and the second inorganic material layer 117b is the emission area EA of the second sub-pixel SP2 . may be formed in response to In addition, the third inorganic material layer 117c may be formed to correspond to the emission area EA of the third sub-pixel SP3 . The first inorganic material layer 117a, the second inorganic material layer 117b, and the third inorganic material layer 117c may be disposed to be spaced apart from each other in the first direction (x-axis direction).

The first inorganic material layer 117a, the second inorganic material layer 117b, and the third inorganic material layer 117c may be disposed to be spaced apart from each other with respect to at least one of the data line DL and the power line PL. can In addition, the first inorganic material layer 117a, the second inorganic material layer 117b, and the third inorganic material layer 117c may be formed to extend in the second direction (y-axis direction). For example, the first inorganic material layer 117a , the second inorganic material layer 117b , and the third inorganic material layer 117c may be formed to extend in the same direction as the data line DL. Some regions of the first inorganic material layer 117a , the second inorganic material layer 117b , and the third inorganic material layer 117c formed to extend in the second “direction” are formed in the second thin film transistor 300 . It may be etched to form a sixth contact hole CH6 for exposing the drain electrode 313 .

As the first inorganic material layer 117a , the second inorganic material layer 117b , and the third inorganic material layer 117c are spaced apart from each other, an upper surface of the planarization layer 116 may be exposed. Accordingly, the first inorganic material layer 117a, the second inorganic material layer 117b, and the third inorganic material layer 117c are formed on the upper surface of the planarization layer 116 positioned in the region overlapping the data line DL. may not be placed.

Referring to FIG. 4 , the first electrode 411 of the light emitting device 400 may be disposed on the inorganic material layer 117 . The first electrode 411 is a second thin film through the inorganic material layer 117 , the organic material layer 116 , the second passivation layer 115 , and the sixth contact hole CH6 formed in the first passivation layer 114 . It may be electrically connected to the transistor 300 . For example, the first electrode 411 of the light emitting device 400 is electrically connected to the second drain electrode 313 of the second thin film transistor 300 through the sixth contact hole CH6 to form the light emitting device. A current for driving may be supplied.

The first electrode 411 may be formed of a transparent metal material, a transflective metal material, or a metal material having high reflectance. When the display device 100 is formed in a top emission type, the first electrode 411 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and an Ag alloy. , and a laminate structure of Ag alloy and ITO (ITO/Ag alloy/ITO) may be formed of a metal material having high reflectance. The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is formed in a bottom light-emitting type, the first electrode 411 is a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, or magnesium (Mg), silver ( Ag), or may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). The first electrode 411 may be an anode electrode.

The first electrode 411 may be patterned and disposed on the inorganic material layer 117 for each sub-pixel SP1 , SP2 , and SP3 . For example, one first electrode 411 is formed on the first inorganic material layer 117a disposed in the first sub-pixel SP1 , and a second inorganic material disposed in the second sub-pixel SP2 . Another first electrode 411 is formed on the layer 117b, and another first electrode 411 is formed on the third inorganic material layer 117c disposed in the third sub-pixel SP3. can be formed.

Referring to FIG. 4 , the first electrode 411 may be disposed to directly contact the upper surface of the inorganic material layer 117 . Based on the first direction (x-axis direction), the width of the first electrode 411 may be smaller than the width of the inorganic material layer 117 . For example, the width of the first electrode 411 disposed in the second sub-pixel SP2 may be smaller than the width of the second inorganic material layer 117b disposed in the second sub-pixel SP2 .

In addition, the distance between the first electrodes 411 and the spaced apart distance from each other may be greater than the distance the inorganic material layer 117 is spaced apart from each other. For example, referring to FIGS. 3 and 4 , the first electrode 411 disposed in the second subpixel SP2 and the first electrode 411 disposed in the third subpixel SP3 are spaced apart from each other. The distance may be greater than a distance between the second inorganic material layer 117b and the third inorganic non-material layer 117c.

Referring to FIG. 4 , the end of the first electrode 411 may be located inside the end of the inorganic material layer 117 . For example, as shown in FIG. 4 , the first electrode 411 disposed in the second sub-pixel SP2 may be positioned inside the end of the second inorganic material layer 117b. The first electrode 411 disposed in the third sub-pixel SP3 may be disposed inside the end of the third inorganic material layer 117c. In addition, the first electrode 411 disposed in the first sub-pixel SP1 may be disposed inside the end of the first inorganic material layer 117a.

Referring to FIG. 4 , the lower surface of the first electrode 411 corresponding to the emission area EA may directly contact the upper surface of the inorganic material layer 117 . For example, all lower surfaces of the first electrode 411 corresponding to the emission area EA may directly contact the upper surface of the inorganic material layer 117 .

The bank 118 may be disposed on the first electrode 411 and the inorganic insulating layer 117 . The bank 118 may be provided between the first electrodes 411 provided in each of the sub-pixels SP1 , SP2 , and SP3 . Also, the bank 118 may be formed to cover the ends of each of the first electrodes 411 and to expose a portion of each of the first electrodes 411 . Accordingly, in the bank 118 , a problem of a decrease in luminous efficiency due to current concentration at the end of the first electrode 411 can be prevented from occurring.

The bank 118 may define an emission area EA in each of the plurality of sub-pixels SP1 , SP2 , and SP3 . The bank 118 may define a light emitting area of the display device 100 and thus may be referred to as a pixel defining layer. For example, an area in which the bank 118 is not formed and the first electrode 411 is exposed in each of the sub-pixels SP1 , SP2 , and SP3 may be the emission area EA. In addition, an area excluding the light emitting area EA may be a non-emission area NEA.

Also, the bank 118 may include an organic material. For example, the bank 118 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. there is.

The bank 118 may include a plurality of bank patterns provided in each of the plurality of sub-pixels SP1 , SP2 , and SP3 . For example, the bank 118 includes a first bank pattern 118a , a second bank pattern 118b , and a third bank pattern provided between sub-pixels disposed adjacent to each other in the first direction (X-axis direction). (118c). The first bank pattern 118a may cover the edge of the first electrode 411 provided in any one of the two sub-pixels disposed adjacent to each other in the first direction (X-axis direction). The second bank pattern 118b may cover the edge of the first electrode 411 provided in the other one of the two sub-pixels disposed adjacent to each other in the first direction (X-axis direction). In addition, the third bank pattern 118c may cover the edge of the first electrode 411 provided in the other one of the two sub-pixels disposed adjacent to each other in the first direction (X-axis direction).

For example, referring to FIG. 4 , the first bank pattern 118a may cover the edge of the first electrode 411 disposed in the first sub-pixel SP1 . The second bank pattern 118b may cover an edge of the first electrode 411 disposed in the second sub-pixel SP2 . The third bank pattern 118c may cover an edge of the first electrode 411 disposed in the third sub-pixel SP3 . In addition, openings may be formed in each of the first bank pattern 118a , the second bank pattern 118b , and the third bank pattern 118c to expose the first electrode 411 .

4 , the bank 118 may cover both sides of the first electrode 411 . Also, the bank 118 may cover upper surfaces of both sides of the inorganic material layer 117 . For example, as shown in FIG. 4 , the lower surface of the bank 118 may directly contact side surfaces and upper surfaces of both sides of the first electrode 411 . In addition, the lower surface of the bank 118 may directly contact the exposed upper surface of the inorganic insulating layer 117 without overlapping the first electrode 411 . Also, the lower surface of the bank 118 may be spaced apart from the upper surface of the organic material layer 116 in the second direction (y-axis direction). Hereinafter, the second bank pattern 118b of the bank 118 will be described in detail as an example. Since the first bank pattern 118a and the third bank pattern 118c are substantially the same as the second bank pattern 118b, a detailed description thereof will be omitted.

The second bank pattern 118b disposed in the second sub-pixel SP2 may extend in the second direction (Y-axis direction). The second bank pattern 118b may cover an edge of the first electrode 411 disposed in the second sub-pixel SP2 . In addition, the second bank pattern 118b covering one side of the first electrode 411 disposed in the second sub-pixel SP2 is spaced apart from the first bank pattern 118a in the first direction (x-axis direction). can face In addition, the second bank pattern 118b covering the other side of the first electrode 411 disposed in the second sub-pixel SP2 is spaced apart from the third bank pattern 118c in the first direction (x-axis direction). can face

The bank 118 may extend to sub-pixels adjacent in the second direction (y-axis direction) and may not extend to sub-pixels adjacent to each other in the first direction (x-axis direction).

Referring to FIG. 4 , the second inorganic material layer 117b may protrude beyond the end of the first electrode 411 disposed in the second sub-pixel SP2 . In addition, the second bank pattern 118b may be provided to protrude from the end of the second inorganic material layer 117b. Accordingly, side surfaces of both sides of the second inorganic material layer 117b may not contact the lower surface of the second bank pattern 118b.

The separation distance between the second bank pattern 118b and the third bank pattern 118c may be smaller than the separation distance between the second inorganic material layer 117b and the third inorganic material layer 117c. In addition, the separation distance between the second inorganic material layer 117b and the third inorganic material layer 117c is the first electrode 411 disposed in the second sub-pixel SP2 and the first electrode 411 disposed in the third sub-pixel SP3 . It may be smaller than the separation distance of one electrode 411 .

Referring to FIG. 4 , the light emitting layer 412 of the light emitting device 400 may be disposed on the bank 118 and the first electrode 411 . In addition, a first dummy pattern 611 of the dummy pattern 600 may be formed on the organic material layer 116 . The first dummy pattern 611 and the emission layer 412 may have the same stacked structure and may be made of the same material. The first dummy patterns 611 of the dummy pattern 600 may be disposed between the inorganic material layers 117 spaced apart from each other. For example, the first dummy pattern 611 may be disposed between the first inorganic material layer 117a and the second inorganic material layer 117b. Also, the first dummy pattern 611 may be disposed between the second inorganic material layer 117b and the third inorganic material layer 117c.

The emission layer 412 may include a first emission layer and a second emission layer that face each other with a charge generation layer (CGL) interposed therebetween. In this case, one light emitting layer of the first and second light emitting layers generates blue light, and the other light emitting layer of the first and second light emitting layers generates yellow-green light, so that white light is generated through the first and second light emitting layers can be White light generated in the emission layer 412 may be incident on a color filter positioned above or below the emission layer to be implemented as a color image.

For example, it may include a first stack emitting light of a first color, a second stack emitting light of a second color, and a charge generation layer (CGL) provided between the first stack and the second stack. there is.

The first stack may be disposed on the first electrode 411 . In the first stack, a hole injection layer (HIL), a hole transport layer (HTL), a first light emitting layer that emits light of a first color, and an electron transport layer (ETL) are sequentially stacked. It may be formed of a single structure, but is not necessarily limited thereto. The first light emitting layer may be at least one of a red light emitting layer emitting red light, a green light emitting layer emitting green light, a blue light emitting layer emitting blue light, and a yellow light emitting layer emitting yellow light, but is not limited thereto.

The first stack may be cut without extending in the first direction (x-axis direction). For example, the first stack may be disconnected between the plurality of sub-pixels SP1 , SP2 , and SP3 adjacent in the first direction (x-axis direction). Specifically, the first stack may be disconnected between the first sub-pixel SP1 and the second sub-pixel SP2 , and between the second sub-pixel SP2 and the third sub-pixel SP3 . As an example, the first stack may be disconnected by the bank 118 having an undercut structure, as shown in FIG. 4 .

On the other hand, the first stack may not be disconnected in the second direction (y-axis direction), but may be connected between a plurality of sub-pixels adjacent in the second direction (y-axis direction). The charge generation layer CGL may have a stacked structure in which an N-type charge generation layer for providing electrons to the first stack and a P-type charge generation layer for providing holes to the second stack are stacked. .

A second stack may be disposed on the charge generation layer. The second stack may have a structure in which a hole transport layer (HTL), a second light emitting layer that emits light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked, but it must be It is not limited. The second light emitting layer may be at least one of a red light emitting layer emitting red light, a green light emitting layer emitting green light, a blue light emitting layer emitting blue light, and a yellow light emitting layer emitting yellow light, but is not limited thereto.

However, the second light emitting layer may emit light of a different color from that of the first light emitting layer. For example, the first emission layer may include a blue emission layer emitting blue light, and the second emission layer may include a yellow emission layer emitting yellow light. As another example, the first emission layer may include a blue emission layer emitting blue light, and the second emission layer may include a red emission layer emitting red light and a green emission layer emitting green light.

The second stack may be cut without extending in the first direction (x-axis direction). For example, the first stack may be disconnected between the plurality of sub-pixels SP1 , SP2 , and SP3 adjacent in the first direction (x-axis direction). Specifically, the first stack may be disconnected between the first sub-pixel SP1 and the second sub-pixel SP2 , and between the second sub-pixel SP2 and the third sub-pixel SP3 . For example, as shown in FIG. 4 , the second stack may be disconnected by the bank 118 having an undercut structure.

On the other hand, the second stack may not be disconnected in the second direction (y-axis direction), but may be connected between a plurality of sub-pixels adjacent in the second direction (y-axis direction).

Referring to FIG. 4 , a second electrode 413 may be disposed on the emission layer 412 . When a voltage is applied to the first electrode 411 and the second electrode 413, holes and electrons move to the light emitting layer 412 through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light emitting layer 412 to emit light. .

The emission layer 412 may be cut off without extending in the first direction (x-axis direction). For example, the emission layer 412 may be cut off between the plurality of sub-pixels SP1 , SP2 , and SP3 adjacent in the first direction (x-axis direction). For example, the emission layer 412 may be disconnected between the first sub-pixel SP1 and the second sub-pixel SP2 and between the second sub-pixel SP2 and the third sub-pixel SP3 . Referring to FIG. 4 , the light emitting layer 412 may be cut off by the bank 118 having an undercut structure.

On the other hand, the emission layer 412 is not disconnected in the second direction (y-axis direction), but may be connected between a plurality of sub-pixels adjacent in the second direction (y-axis direction).

Specifically, the light emitting layer 412 and the second electrode 413 are formed by the first bank pattern 118a and the second bank pattern 118b having an undercut structure to form the first sub-pixel SP1 and the second sub-pixel SP2. ) can be broken without being connected between them. In addition, the light emitting layer 412 and the second electrode 413 are connected to the second sub-pixel SP2 and the third sub-pixel SP3 by the second bank pattern 118b and the third bank pattern 118c having an undercut structure. It can be broken without being connected between them.

In addition, the first dummy pattern 611 may be disposed between the plurality of sub-pixels SP1 , SP2 , and SP3 . Referring to FIG. 4 , the first dummy pattern 611 may be disposed between the first bank pattern 118a and the second bank pattern 118b. In addition, the first dummy pattern 611 may be disposed between the second bank pattern 118b and the third bank pattern 118c.

Also, the first dummy pattern 611 may directly contact the upper surface of the organic material layer 116 . The first dummy pattern 611 and the inorganic material layer 117 may be disposed on the same layer. For example, the first dummy pattern 611 and the inorganic material layer 117 may be disposed on the organic material layer 116 . Accordingly, both the lower surface of the first dummy pattern 611 and the lower surface of the inorganic material layer 117 may directly contact the upper surface of the organic material layer 116 .

The first dummy pattern 611 may be formed to extend without being interrupted in the second direction (y-axis direction). Accordingly, the first dummy pattern 611 may be connected between a plurality of sub-pixels adjacent in the second direction (y-axis direction).

Referring to FIG. 4 , a second electrode 413 may be disposed on the emission layer 412 . In addition, a second dummy pattern 612 may be disposed on the first dummy pattern 611 . The second dummy pattern 612 and the second electrode 413 have the same stacked structure and may be made of the same material.

The second electrode 413 may be disconnected between the sub-pixels SP1 , SP2 , and SP3 having different colors. Specifically, the second electrode 413 may be disconnected between the first sub-pixel SP1 and the second sub-pixel SP2 . In addition, the second electrode 413 may be disconnected between the second sub-pixel SP2 and the third sub-pixel SP3 . Although the second electrode 413 is disconnected between the sub-pixels SP1 , SP2 , and SP3 , they may be electrically connected to each other in the edge region of the display panel 110 . Specifically, the first bank pattern 118a , the second bank pattern 118b , and the third bank pattern 118c may extend to the non-display area NDA in the second direction (Y-axis direction). The second electrode 413 and the emission layer 412 may be formed up to a portion of the non-display area NDA while covering the display area DA. In this case, the second electrode 413 may have a larger formation area than the emission layer 412 .

Accordingly, the second electrodes 413 may be electrically connected to each other in the outer region of the display panel 110 .

The second electrode 413 may not be disconnected in the second direction (y-axis direction), but may be connected between a plurality of sub-pixels adjacent to each other in the second direction (y-axis direction).

The second electrode 413 may be made of a transparent metal material, a transflective metal material, or a metal material having high reflectance. When the display device 100 is formed in a top emission type, the second electrode 413 is a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, or magnesium (Mg), silver ( Ag), or may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is formed in a bottom light emission type, the second electrode 413 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and an Ag alloy. , and a laminate structure of Ag alloy and ITO (ITO/Ag alloy/ITO) may be formed of a metal material having high reflectance. The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The second electrode 413 may be a cathode electrode.

In addition, the second dummy pattern 612 may be disposed between the plurality of sub-pixels SP1 , SP2 , and SP3 . Referring to FIG. 4 , the second dummy pattern 612 may be disposed between the first bank pattern 118a and the second bank pattern 118b. In addition, the second dummy pattern 612 may be disposed between the second bank pattern 118b and the third bank pattern 118c.

The second dummy pattern 612 may be formed to extend without being interrupted in the second direction (y-axis direction). Accordingly, the second dummy pattern 612 may be connected between a plurality of sub-pixels adjacent in the second direction (y-axis direction).

As described above, in the display device 100 according to the exemplary embodiment of the present specification, the first electrode 411 and the organic insulating layer 116 may have an undercut structure in the bank 118 . An inorganic insulating layer 117 may be formed therebetween. Also, by the bank 118 having an undercut structure, the emission layer 412 and the second electrode 413 may be disconnected between sub-pixels having different colors. Through this, the display device 100 according to the exemplary embodiment of the present specification may prevent a leakage current from occurring between sub-pixels having different colors.

As a result, the display device 100 according to the exemplary embodiment of the present specification may prevent leakage current by using the bank 118 having an undercut structure.

The encapsulation unit 500 may be disposed on the light emitting device 400 and the dummy pattern 600 . For example, an encapsulant 500 for suppressing penetration of moisture may be further disposed on the second electrode 413 and the second dummy pattern 612 .

The encapsulation unit 500 may include a first inorganic encapsulation layer 511 , a second organic encapsulation layer 512 , and a third inorganic encapsulation layer 513 . The first inorganic encapsulation layer 511 of the encapsulation unit 500 may be disposed on the second electrode 412 . In addition, the second organic encapsulation layer 512 may be disposed on the first inorganic encapsulation layer 511 . Also, the third inorganic encapsulation layer 513 may be disposed on the second inorganic encapsulation layer 512 . The first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 153 of the encapsulation unit 500 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second organic encapsulation layer 512 of the encapsulation unit 500 is formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. It can be formed of organic materials such as resin).

The color filter may be formed on the encapsulation film, but is not limited thereto. For example, the color filter may be disposed in a region between the light emitting device 400 and the thin film transistors 200 and 300 . The color filter may be disposed to correspond to each of the plurality of sub-pixels SP1 , SP2 , and SP3 . The color filter disposed to correspond to the first sub-pixel SP1 may be a red color filter. The color filter disposed to correspond to the second sub-pixel SP2 may be a green color filter. The color filter disposed to correspond to the third sub-pixel SP3 may be a blue color filter.

5A to 5F are cross-sectional views taken along line I-I' of FIG. 3 and are cross-sectional views illustrating a manufacturing process. Descriptions of the components substantially the same as those of the components shown in FIG. 4 will be simplified or omitted.

Referring to FIG. 5A , a first passivation layer 114 , a second passivation layer 115 , an organic material layer 116 on the second thin film transistor 300 , the power line PL and the data line DL; and an inorganic material layer 117 may be formed. Although the inorganic material layer 117 is added to form the undercut structure of the bank 118 , an etching process using a separate mask is not added.

5B, the inorganic material layer 117, the organic material layer 116, the second passivation layer 115, and the first passivation layer 114 are formed on the second drain electrode ( A sixth contact hole CH6 for exposing 313 may be formed.

Also, referring to FIG. 5C , a first electrode 411 may be disposed on each of the plurality of sub-pixels SP1 , SP2 , and SP3 by forming a metal layer on the inorganic material layer 117 and then patterning it. For example, one first electrode 411 is formed in the first sub-pixel SP1 , the other first electrode 411 is formed in the second sub-pixel SP2 , and the third sub-pixel SP2 Another first electrode 411 may be formed in SP3).

Referring to FIG. 5D , a bank 118 may be formed on the inorganic material layer 117 and the first electrode 411 . The bank 118 may be formed to cover the edge of the first electrode 411 patterned for each sub-pixel SP1 , SP2 , and SP3 . For example, the bank 118 may be formed to cover the ends of each of the first electrodes 411 , and a portion of each of the first electrodes 411 may be exposed.

The bank 118 may include a first bank pattern 118a, a second bank pattern 118b, and a third bank pattern 118c. The first bank pattern 118a may cover an edge of the first electrode 411 disposed in the first sub-pixel SP1 . The second bank pattern 118b may cover an edge of the first electrode 411 disposed in the second sub-pixel SP2 . The third bank pattern 118c may cover an edge of the first electrode 411 disposed in the third sub-pixel SP3 . In addition, openings may be formed in each of the first bank pattern 118a , the second bank pattern 118b , and the third bank pattern 118c to expose the first electrode 411 .

In addition, the first bank pattern 118a may be formed to extend to the sub-pixel adjacent to the first sub-pixel SP1 in the second direction (y-axis direction). The second bank pattern 118b may be formed to extend to a sub-pixel adjacent to the second sub-pixel SP2 in the second direction (y-axis direction). In addition, the third bank pattern 118c may be formed to extend to a sub-pixel adjacent to the third sub-pixel SP3 in the second direction (y-axis direction).

In addition, the inorganic material layer 117 may be exposed by the first bank pattern 118a and the second bank pattern 118b spaced apart from each other. In addition, the inorganic material layer 117 may be exposed by the second bank pattern 118b and the third bank pattern 118c spaced apart from each other.

Referring to FIG. 5E , an etching process using a mask may be performed to form an undercut structure of the bank 118 . An etching process may be used to remove the exposed inorganic material layer 117 to be patterned. In the etching process for patterning the inorganic material layer 117 , the inorganic material positioned on the lower surface of the bank 118 due to the difference in etching rates between the inorganic material layer 117 made of the inorganic material and the bank 118 made of the organic material. A portion of the layer 117 may be removed by etching. In addition, a lower surface of the bank 118 may be exposed. Also, a lower surface of the bank 118 may be spaced apart from the organic material layer 116 .

Accordingly, the bank 118 may have an undercut structure that protrudes from the end of the inorganic material layer 117 .

The inorganic material layer 117 patterned by the etching process may include a first inorganic material layer 117a, a second inorganic material layer 117b, and a third inorganic material layer 117c. The first inorganic material layer 117a and the second inorganic material layer 117b may be formed to be spaced apart from each other. In addition, the second inorganic material layer 117b and the third inorganic material layer 117c may be disposed to be spaced apart from each other.

Accordingly, the separation distance between the first inorganic material layer 117a and the second inorganic material layer 117b may be greater than the separation distance between the first bank pattern 118a and the second bank pattern 118b. Also, the separation distance between the second inorganic material layer 117b and the third inorganic material layer 117c may be greater than the separation distance between the second bank pattern 118b and the third bank pattern 118c.

In this way, the inorganic material layer 117 added to form the undercut structure of the bank 118 may be formed under the first electrode 411 without using a separate mask. In addition, an undercut structure of the bank 118 may be formed using the inorganic material layer 117 formed under the first electrode 411 . Accordingly, in the display device 100 according to the exemplary embodiment of the present specification, in forming the bank 118 having an undercut structure to prevent leakage current from occurring between sub-pixels having different colors, a separate The advantage is that no mask process is added.

Referring to FIG. 5F , an emission layer 412 and a second electrode 413 may be formed on the bank 118 and the first electrode 411 . In this case, the light emitting layer 412 and the second electrode 413 may be formed to be disconnected without being connected.

The emission layer 412 and the second electrode 413 may be cut off without extending in the first direction (x-axis direction). For example, the emission layer 412 and the second electrode 413 may be disconnected between the plurality of sub-pixels SP1 , SP2 , and SP3 adjacent in the first direction (x-axis direction). The sub-pixels SP1 , SP2 , and SP3 adjacent in the first direction (x-axis direction) may have different colors.

The emission layer 412 and the second electrode 413 may be disconnected between the first sub-pixel SP1 and the second sub-pixel SP2 . Also, the emission layer 412 and the second electrode 413 may be disconnected between the second sub-pixel SP2 and the third sub-pixel SP3 . In this way, the light emitting layer 412 and the second electrode 413 may be disconnected by the bank 118 having an undercut structure.

On the other hand, the emission layer 412 and the second electrode 413 may not be disconnected in the second direction (y-axis direction), but may be connected between a plurality of sub-pixels adjacent to each other in the second direction (y-axis direction). A plurality of sub-pixels adjacent in the second direction (y-axis direction) may have the same color. For example, sub-pixels adjacent to the first sub-pixel SP1 in the second direction (y-axis direction) may have the same color as the first sub-pixel SP1 . Sub-pixels adjacent to the second sub-pixel SP2 in the second direction (y-axis direction) may have the same color as the second sub-pixel SP2 . In addition, sub-pixels adjacent to the third sub-pixel SP3 in the second direction (y-axis direction) may have the same color as the third sub-pixel SP3 .

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in the present specification are for explanation rather than limiting the technical spirit of the present specification, and the scope of the technical spirit of the present specification is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present specification should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present specification.

100: display device
110: substrate
200: first thin film transistor
300: second thin film transistor
400: light emitting element
500: encapsulation unit
P: pixel
SP1, SP2, SP3: sub-pixel
111: buffer layer
112: gate insulating layer
113: interlayer insulating layer
114: first protective layer
115: second protective layer
116: organic material layer
117: inorganic material layer
118: bank

Claims (10)

a substrate including a plurality of sub-pixels, on which a thin film transistor is disposed for each sub-pixel;
a protective layer disposed on the thin film transistor;
an organic material layer disposed on the passivation layer;
an inorganic material layer disposed on the organic material layer and spaced apart from each other in a first direction;
a first electrode disposed on the inorganic material layer and positioned inside the end of the inorganic material layer;
a bank covering an edge of the first electrode and disposed to protrude from an end of the inorganic material layer;
a light emitting layer disposed on the bank and the first electrode and cut off in the first direction; and
and a second electrode disposed on the light emitting layer. According to claim 1,
The sub-pixel may include a first sub-pixel, a second sub-pixel disposed adjacent to the first sub-pixel in the first direction, and a second sub-pixel disposed adjacent to the second sub-pixel in the first direction A display device including a third sub-pixel. 3. The method of claim 2,
The inorganic material layer,
a first inorganic material layer disposed on the first sub-pixel;
a second inorganic material layer disposed on the second sub-pixel and spaced apart from the first inorganic material layer; and
and a third inorganic material layer disposed on the third sub-pixel and spaced apart from the second inorganic material layer. 4. The method of claim 3,
The bank is
a first bank pattern disposed on the first sub-pixel;
a second bank pattern disposed on the second sub-pixel; and
a third bank pattern disposed on the third sub-pixel;
A distance between the first bank pattern and the second bank pattern is smaller than a distance between the first inorganic material layer and the second inorganic material layer, and the second bank pattern and the third bank pattern are spaced apart. The distance between the second inorganic material layer and the third inorganic material layer is smaller than the distance between them. According to claim 1,
The light emitting layer is not disconnected in a second direction perpendicular to the first direction, but is connected between a plurality of sub-pixels disposed in the second direction. According to claim 1,
The second electrode is cut off in the first direction. 7. The method of claim 6,
It is on the organic material layer, further comprising a dummy pattern disposed between the inorganic material layer disposed spaced apart from each other,
The dummy pattern includes a first dummy pattern and a second dummy pattern disposed on the first dummy pattern. 8. The method of claim 7,
The first dummy pattern has the same stacked structure as the light emitting layer and is made of the same material,
The second dummy pattern has the same stacked structure as the second electrode and is made of the same material. 8. The method of claim 7,
A lower surface of the first dummy pattern and a lower surface of the inorganic material layer are in direct contact with an upper surface of the organic material layer. 4. The method of claim 3,
One first electrode is disposed on the first inorganic material layer disposed on the first sub-pixel, and another first electrode is disposed on the second inorganic material layer disposed on the second sub-pixel; A display device in which another first electrode is disposed on the third inorganic material layer disposed in a third sub-pixel.

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