KR20210043013A - Passivation of light-receiving surfaces of solar cells - Google Patents

Abstract

A method of passivating a light-receiving surface of a solar cell, and a resulting solar cell are described. In one example, the solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer. In another embodiment, the solar cell includes a silicon substrate having a light-receiving surface. A tunneling dielectric layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the tunneling dielectric layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer.

Description

Passivation of the light-receiving surface of a solar cell {PASSIVATION OF LIGHT-RECEIVING SURFACES OF SOLAR CELLS}

Embodiments of the present disclosure are in the field of renewable energy, in particular a method of passivating a light-receiving surface of a solar cell, and a solar cell that is produced.

Photovoltaic cells, commonly known as solar cells, are well-known devices for the direct conversion of solar radiation into electrical energy. In general, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near the surface of the substrate. Solar radiation impinging on the surface of the substrate and entering the substrate creates pairs of electrons and holes in most of the substrate. The electron and hole pairs migrate to the p-doped and n-doped regions in the substrate, thereby creating a voltage difference between the doped regions. The doped regions are connected to the conductive regions on the solar cell to direct current from the cell to an external circuit coupled to the cell.

Efficiency is an important characteristic of a solar cell, as it is directly related to the solar cell's power generation capacity. Likewise, the efficiency in manufacturing solar cells is directly related to the cost effectiveness of such solar cells. Therefore, in general, a technique for increasing the efficiency of a solar cell or a technique for increasing the efficiency in manufacturing a solar cell is desirable. Some embodiments of the present disclosure allow for increased solar cell manufacturing efficiency by providing a novel process for manufacturing solar cell structures. Some embodiments of the present disclosure allow for increased solar cell efficiency by providing a novel solar cell structure.

The following detailed description is merely exemplary in nature and is not intended to limit the subject matter or embodiments of the application and the use of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration”. Any embodiment described herein as illustrative is not necessarily to be construed as preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any explicit or implied theory presented in the foregoing technical field, background, brief summary, or specific content for carrying out the following invention.

This specification includes reference to “one embodiment” or “one embodiment”. The appearances of the phrases “in one embodiment” or “in one embodiment” are not necessarily referring to the same embodiment. Certain features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

Terms. The following paragraphs provide definitions and/or context for terms shown in this disclosure (including the appended claims):

"Included". This term is open-ended. As used in the appended claims, this term does not exclude additional structures or steps.

"Configured to". Various units or components may be described or claimed as being “configured” to perform an operation or tasks. In that context, “configured to” is used to imply a structure by indicating that units/components include a structure that performs these tasks or tasks during operation. As such, a unit/component may be said to be configured to perform a task even when the specified unit/component is not currently operating (eg, not in an on/active state). To state that a unit/circuit/component is "configured to perform one or more tasks" means that 35 U.S.C. It is expressly intended that §112, section 6 does not apply.

"First", "second", etc. As used herein, these terms are used as adjectives for the nouns that follow them and do not imply any type of order (eg, spatial, temporal, logical, etc.). For example, a reference to a "first" solar cell does not necessarily imply that this solar cell is the first solar cell in sequence; Instead, the term “first” is used to distinguish this solar cell from other solar cells (eg, “second” solar cells).

“Combined”-The following description refers to elements or nodes or features that are “coupled” together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly or indirectly to another element/node/feature, not necessarily mechanically. It means to be joined (or directly or indirectly communicated with it).

In addition, certain terms may also be used in the following description for purposes of reference only, and thus are not intended to be limiting. For example, terms such as “top”, “bottom”, “top” and “bottom” refer to directions in the referenced figures. Terms such as "front", "back", "rear", "side", "outside" and "inside" are within a coherent, but arbitrary coordinate system, as clarified by reference to the text and associated drawings describing the component under discussion. Describe the orientation and/or position of the parts of the component. Such terms may include words specifically mentioned above, derivatives thereof, and words of similar meaning.

A method of passivating the light-receiving surface of a solar cell, and the resulting solar cell, are described herein. In the following description, a number of specific details are set forth, such as specific process flow operations, to provide a thorough understanding of an embodiment of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known manufacturing techniques such as lithography and patterning techniques have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

A solar cell is disclosed herein. In one embodiment, the solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer.

In another embodiment, the solar cell includes a silicon substrate having a light-receiving surface. A tunneling dielectric layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the tunneling dielectric layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer.

Also disclosed herein is a method of manufacturing a solar cell. In one embodiment, a method of manufacturing a solar cell involves forming a tunneling dielectric layer on the light-receiving surface of a silicon substrate. The method also involves forming a layer of amorphous silicon on the tunneling dielectric layer at a temperature of less than approximately 300 degrees Celsius.

One or more embodiments described herein relate to a low temperature passivation approach for improved light induced degradation (LID) (mitigation of light induced degradation). More specifically, for example, in cases where an amorphous silicon (aSi) material is used to passivate the crystalline silicon (c-Si) substrate surface, improving the ultraviolet (UV) stability of the front surface of the low-temperature passivated cell. Several approaches for doing are described. For example, by modifying the structure and employing novel passivation material stacks, improvements in the stability of such employing cells can be achieved as being related to long-term energy generation.

To provide context, light-induced degradation is a major problem for aSi passivated c-Si surfaces, especially when exposed to high energy photons (eg UV photons). Rapid degradation can occur even under the best conditions due to the unstable nature of the c-Si/aSi interface. 8 is an energy band diagram 800 for a light-receiving surface of a prior art solar cell c-Si/a-Si interface that is a heterojunction. Referring to Figure 8, it was found that the N-type hydrogenated amorphous silicon (n a-Si) and crystalline silicon (c-Si) interface on the light-receiving surface of the solar cell provides poor passivation, causing instability and rapid deterioration. Became. It is understood that the presented poor passivation is derived from large recombination sites introduced by the phosphorus (P) dopant source at the interface. Attempts to provide a stable solar cell front surface (light-receiving surface) without the use of high-temperature operations have proven difficult. For example, previous attempts have included a thermal oxidation process after the use of thermal diffusion and subsequent high temperature plasma-enhanced chemical vapor deposition (PECVD) processes above 380 degrees Celsius. Under such conditions, poor passivation was achieved. In contrast, if thin silicon (Si) processes can be performed at temperatures below 300 degrees Celsius, the material of the carrier of the wafer used to support the base cell can be tolerated.

According to one or more embodiments described herein, passivation approaches for the light-receiving surface of a solar cell include one of the following: (1) a thin oxide material (e.g., a thin oxide material formed at low temperature for improved stability) , Using chemical oxides, PECVD-forming oxides, low temperature thermal oxides, or ultraviolet/ozone (UV/O ₃ )-forming oxides); (2) An intrinsically hydrogenated amorphous silicon/N-type amorphous silicon (a-Si:i/a-Si:n) stack is employed as the passivation layer, and an electronic band for improved shielding of recombination sites on the surface Using the electronic properties of the phosphorus-doped a-Si layer to bend them; (3) depositing a phosphorus-diffused epitaxial layer on the textured surface to help improve stability by repelling minority carriers from the c-Si/a-Si interface; (4) a burn-in method of exposing the front surface to UV dose and then low temperature annealing to cure the interface; And (5) a simplified cleaning procedure _{of diluted hydrofluoric acid/ozone (HF/O 3} ) in deionized water (DI) to provide a manufacturing friendly process. One or more, or all of the approaches listed above may be combined for use on a suitable front surface stack for maximum transparency (Jsc) and suitable and stable passivation (Voc).

In a particular exemplary embodiment, _{a simplified cleaning process is employed followed by a DI rinse and HW dryer after using 0.3% HF/O 3} to allow for structures (e.g., aSi) deposited at 200 degrees Celsius on textured substrates. :i/SiN aSi:i/aSi:n/SiN structures), a good passivation of less than approximately 10 fA/cm 2 was obtained. In other examples, more aggressive chemicals, such as HF/Piranha (sulfuric acid and hydrogen peroxide)/HF mixtures or HF-only, also exhibited similar passivation values. When tested with exposure to high intensity UV, the simplified cleaning procedure samples performed better. While not being limited by theory, it is now understood that the improvements due to the formation of the formed thin chemical oxide reduced degradation without inhibiting the initial passivation by stabilizing the resulting interface passivation. It has been discovered that such oxide materials can be deposited in a variety of ways, as mentioned above.

More generally, in accordance with one or more embodiments, intrinsic (possibly hydrogenated) amorphous silicon:N type amorphous silicon (represented as i:n) structures are fabricated with or without thin oxides for improved passivation. In another embodiment, the N-type amorphous silicon layer may be used alone, as long as the thin oxide has a sufficiently high quality to maintain good passivation. In cases where intrinsic amorphous silicon is implemented, the material provides additional passivation protection in case of defective oxide. In another embodiment, including a phosphorus-doped amorphous silicon layer in addition to the intrinsic layer improves stability against UV degradation. The phosphorus-doped layer can be implemented to enable band-bending, which helps shield the interface by repelling minority carriers, which reduces the amount of recombination.

1A-1E are cross-sectional views of various steps in manufacturing a solar cell, according to one embodiment of the present disclosure.
1A is a diagram illustrating a starting substrate of a solar cell.
1B is a diagram illustrating the structure of FIG. 1A after formation of a tunneling dielectric layer on the light-receiving surface of the substrate.
1C illustrates the structure of FIG. 1B after formation of an intrinsic silicon layer on a tunneling dielectric layer.
1D illustrates the structure of FIG. 1C after formation of an N-type silicon layer on an intrinsic silicon layer.
1E illustrates the structure of FIG. 1D after formation of a layer of a non-conductive anti-reflective coating (ARC) on an N-type silicon layer.
FIG. 2 is a flow diagram listing operations in a method of manufacturing a solar cell as corresponding to FIGS. 1A-1E, according to an embodiment of the present disclosure.
3 is a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a first exemplary stack of layers on the light-receiving surface of the substrate, in accordance with one embodiment of the present disclosure.
4 is a cross-sectional view of a back-contact solar cell having emitter regions formed within the back surface of the substrate and having a first exemplary stack of layers on the light receiving surface of the substrate, in accordance with one embodiment of the present disclosure.
5 is an energy band diagram for a first exemplary stack of layers disposed on a light receiving surface of a solar cell described in connection with FIGS. 3 and 4, according to an embodiment of the present disclosure.
6A is a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a second exemplary stack of layers on the light-receiving surface of the substrate, in accordance with one embodiment of the present disclosure.
6B is an energy band diagram for a second exemplary stack of layers disposed on the light-receiving surface of the solar cell described in connection with FIG. 6A, according to an embodiment of the present disclosure.
7A is a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a third exemplary stack of layers on the light receiving surface of the substrate, according to one embodiment of the present disclosure.
7B is an energy band diagram for a third exemplary stack of layers disposed on the light-receiving surface of the solar cell described in connection with FIG. 7A, according to an embodiment of the present disclosure.
8 is an energy band diagram for a light-receiving surface of a prior art solar cell.

1A-1E illustrate cross-sectional views of various steps in manufacturing a solar cell, according to one embodiment of the present disclosure. 2 is a flow chart listing operations in a method of manufacturing a solar cell as corresponding to FIGS. 1A-1E, according to one embodiment of the present disclosure.

1A illustrates a starting substrate for a solar cell. Referring to FIG. 1A, the substrate 100 has a light-receiving surface 102 and a back surface 104. In one embodiment, the substrate 100 is a single crystal silicon substrate, such as a bulk single crystal N-type doped silicon substrate. However, it will be appreciated that the substrate 100 may be a layer, such as a multi-crystalline silicon layer, disposed on the entire solar cell substrate. In one embodiment, the light-receiving surface 102 has a textured topography 106. In one such embodiment, a hydroxide-based wet etchant is employed to texturize the front surface of the substrate 100. It will be appreciated that the textured surface may be one having a regular or irregularly shaped surface for scattering incident light and thereby reducing the amount of light reflected from the light receiving surface of the solar cell.

1B illustrates the structure of FIG. 1A after formation of a tunneling dielectric layer on the light-receiving surface of the substrate. Referring to FIG. 1B and the corresponding operation 202 of the flowchart 200, a tunneling dielectric layer 108 is formed on the light-receiving surface 102 of the substrate 100. In one embodiment, as shown in FIG. 1B, the light-receiving surface 102 has a textured surface shape 106 and the tunneling dielectric layer 108 conforms to the textured surface shape 106. do.

In one embodiment, tunneling dielectric layer 108 is a silicon dioxide (SiO ₂ ) layer. In one such embodiment, the silicon dioxide (SiO ₂ ) layer has a thickness in the range of approximately 1 to 10 nanometers, preferably less than 1.5 nanometers. In one embodiment, tunneling dielectric layer 108 is hydrophilic. In one embodiment, the tunneling dielectric layer 108 comprises chemical oxidation of a portion of the light-receiving surface of the silicon substrate _{, plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide (SiO 2} ), and thermal oxidation of a portion of the light-receiving surface of the silicon substrate. , Or exposure of the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation in an _{O 2} or O _{3 environment.}

1C illustrates the structure of FIG. 1B after formation of an intrinsic silicon layer on the tunneling dielectric layer. Referring to FIG. 1C and the corresponding operation 204 of the flowchart 200, an intrinsic silicon layer 110 is formed over the tunneling dielectric layer 108.

In one embodiment, the intrinsic silicon layer 110 is an intrinsic amorphous silicon layer. In one such embodiment, the intrinsic amorphous silicon layer has a thickness in the range of approximately 1-5 nanometers. In one embodiment, forming the intrinsic amorphous silicon layer on the tunneling dielectric layer 108 is performed at a temperature of less than approximately 300 degrees Celsius. In one embodiment, the intrinsic amorphous silicon layer is formed using plasma enhanced chemical vapor deposition (PECVD) and is represented by a-Si:H, including Si-H covalent bonds throughout the layer.

1D illustrates the structure of FIG. 1C after formation of an N-type silicon layer on the intrinsic silicon layer. Referring to FIG. 1D and the corresponding operation 206 of the flow chart 200, an N-type silicon layer 112 is formed on the intrinsic silicon layer 110.

In one embodiment, the N-type silicon layer 112 is an N-type amorphous silicon layer. In one embodiment, forming the N-type amorphous silicon layer on the intrinsic silicon layer 110 is performed at a temperature of less than approximately 300 degrees Celsius. In one embodiment, the N-type amorphous silicon layer is formed using plasma enhanced chemical vapor deposition (PECVD) and is represented by phosphorus-doped a-Si:H, including Si-H covalent bonds throughout the layer. In one embodiment, the N-type silicon layer 112 includes an impurity such as a phosphorus dopant. In one embodiment, the phosphorus dopant is incorporated during film deposition or during post implantation operations.

1E illustrates the structure of FIG. 1D after formation of a non-conductive anti-reflective coating (ARC) layer on an N-type silicon layer. Referring to FIG. 1E and corresponding operation 208 of flowchart 200, a non-conductive anti-reflective coating (ARC) layer 114 is formed on the N-type silicon layer 112. In one embodiment, the non-conductive ARC layer comprises silicon nitride. In one such embodiment, the silicon nitride is formed at a temperature of less than approximately 300 degrees Celsius.

3 illustrates a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a first exemplary stack of layers on the light-receiving surface of the substrate, according to one embodiment of the present disclosure.

Referring to FIG. 3, a solar cell includes a silicon substrate 100 having a light-receiving surface 102. A tunneling dielectric layer 108 is disposed on the light-receiving surface of the silicon substrate 100. An intrinsic silicon layer 110 is disposed on the tunneling dielectric layer 108. An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. A non-conductive anti-reflective coating (ARC) layer 114 is disposed on the N-type silicon layer 112. As such, the stack of layers on the light-receiving surface of the solar cell of FIG. 3 is the same as described in connection with FIGS. 1A-1E.

Referring again to FIG. 3, on the rear surface of the substrate 100, alternating P-type 120 and N-type 122 emitter regions are formed. In one such embodiment, trenches 121 are disposed between alternating P-type 120 and N-type 122 emitter regions. More specifically, in one embodiment, first polycrystalline silicon emitter regions 122 are formed on the first portion of the thin dielectric layer 124 and doped with an N-type impurity. Second polycrystalline silicon emitter regions 120 are formed on the second portion of the thin dielectric layer 124 and doped with P-type impurities. In one embodiment, tunnel dielectric 124 is a silicon oxide layer having a thickness of approximately 2 nanometers or less.

Referring again to FIG. 3, conductive contact structures 128/130 are manufactured by first depositing an insulating layer 126 and patterning the insulating layer to have openings and then forming one or more conductive layers within the openings. do. In one embodiment, the conductive contact structures 128/130 comprise metal and are formed by a deposition, lithography and etching approach, or alternatively a printing or plating process, or alternatively a foil adhesion process.

4 illustrates a cross-sectional view of a back-contact solar cell having emitter regions formed within the back surface of the substrate and having a first exemplary stack of layers on the light receiving surface of the substrate, according to one embodiment of the present disclosure.

Referring to FIG. 4, a solar cell includes a silicon substrate 100 having a light-receiving surface 102. A tunneling dielectric layer 108 is disposed on the light-receiving surface of the silicon substrate 100. An intrinsic silicon layer 110 is disposed on the tunneling dielectric layer 108. An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. A non-conductive anti-reflective coating (ARC) layer 114 is disposed on the N-type silicon layer 112. As such, the stack of layers on the light-receiving surface of the solar cell of FIG. 4 is the same as described in connection with FIGS. 1A-1E.

Referring again to FIG. 4, in the rear surface of the substrate 100, alternating P-type 150 and N-type 152 emitter regions are formed. More specifically, in one embodiment, the first emitter regions 152 are formed in the first portion of the substrate 100 and doped with an N-type impurity. Second emitter regions 150 are formed in the second portion of the substrate 100 and doped with P-type impurities. Referring again to Figure 4, conductive contact structures 158/160 are fabricated by first depositing an insulating layer 156 and patterning the insulating layer to have openings and then forming one or more conductive layers within the openings. do. In one embodiment, the conductive contact structures 158/160 comprise metal and are formed by a deposition, lithography and etching approach, or alternatively a printing or plating process, or alternatively a foil adhesion process.

5 is an energy band diagram 500 for a first exemplary stack of layers disposed on the light-receiving surface of the solar cell described in connection with FIGS. 3 and 4, according to an embodiment of the present disclosure. Referring to the energy band diagram 500, the band structure is a material stack including N-type doped silicon (n), intrinsic silicon (i), a thin oxide layer (Tox), and a crystalline silicon substrate (c-Si). Is provided for. The Fermi level is shown as 502 and indicates good passivation of the light-receiving surface of the substrate with this material stack.

6A illustrates a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a second exemplary stack of layers on the light-receiving surface of the substrate, according to one embodiment of the present disclosure.

Referring to FIG. 6A, a solar cell includes a silicon substrate 100 having a light-receiving surface 102. An intrinsic silicon layer 110 is disposed on the light-receiving surface 102 of the silicon substrate 100 (in this case, the growth may be epitaxial). An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. A non-conductive anti-reflective coating (ARC) layer 114 is disposed on the N-type silicon layer 112. As such, the stack of layers on the light-receiving surface of the solar cell of FIG. 6A does not include the tunneling dielectric layer 108 described in connection with FIG. 3. However, the other features described in connection with FIG. 3 are similar. It will also be appreciated that emitter regions may be formed in the substrate as described in connection with FIG. 4.

6B is an energy band diagram 600 for a second exemplary stack of layers disposed on the light-receiving surface of the solar cell described in connection with FIG. 6A, according to an embodiment of the present disclosure. Referring to the energy band diagram 600, a band structure is provided for a material stack comprising N-type doped silicon (n), intrinsic silicon (i), and a crystalline silicon substrate (c-Si). The Fermi level is shown as 602, indicating good passivation of the light-receiving surface of the substrate with this material stack even if the oxide layer is not in place to block the path 604.

7A illustrates a cross-sectional view of a back-contact solar cell having emitter regions formed over the back surface of the substrate and having a third exemplary stack of layers on the light-receiving surface of the substrate, according to one embodiment of the present disclosure.

Referring to FIG. 7A, a solar cell includes a silicon substrate 100 having a light-receiving surface 102. A tunneling dielectric layer 108 is disposed on the light-receiving surface 102 of the silicon substrate 100. An N-type silicon layer 112 is disposed on the tunneling dielectric layer 108. A non-conductive anti-reflective coating (ARC) layer 114 is disposed on the N-type silicon layer 112. As such, the stack of layers on the light-receiving surface of the solar cell of FIG. 7A does not include the intrinsic silicon layer 110 described in connection with FIG. 3. However, the other features described in connection with FIG. 3 are similar. It will also be appreciated that emitter regions may be formed in the substrate as described in connection with FIG. 4.

7B is an energy band diagram 700 for a third exemplary stack of layers disposed on the light-receiving surface of the solar cell described in connection with FIG. 7A, according to an embodiment of the present disclosure. Referring to the energy band diagram 700, a band structure is provided for a material stack comprising an N-type doped silicon (n), a thin oxide layer (Tox), and a crystalline silicon substrate (c-Si). The Fermi level is shown as 702 and indicates good passivation of the light-receiving surface of the substrate with this material stack.

Overall, although certain materials have been specifically described above, some materials can be easily replaced with other materials of the present disclosure, with other such embodiments being within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, a substrate of a different material, such as a substrate of a III-V material, may be used in place of the silicon substrate. In addition, when the N+ and P+ type doping is specifically described for the emitter region on the back surface of the solar cell, it will be understood that other embodiments contemplated include opposite conductivity types, such as P+ and N+ type doping, respectively. .

Thus, a method of passivating a light-receiving surface of a solar cell, and a solar cell to be generated have been disclosed.

Although specific embodiments have been described above, even if only a single embodiment has been described for a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Examples of features provided in this disclosure are intended to be illustrative rather than restrictive, unless stated otherwise. The above description is intended to cover such alternatives, modifications and equivalents, as will become apparent to those skilled in the art having the benefit of this disclosure.

The scope of the present disclosure is, whether or not alleviating any or all of the problems addressed herein, any feature or combination of features disclosed herein (expressly or implicitly), Or any generalizations thereof. Thus, for any such combination of features, new claims may be made during the course of this application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from dependent claims may be combined with features of independent claims, and features from each independent claim are arbitrary and not only within the specific combinations recited within the appended claims. Can be combined in any suitable way.

In one embodiment, the solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer.

In one embodiment, the silicon substrate is a single crystal silicon substrate, the intrinsic silicon layer is an intrinsic amorphous silicon layer, and the N-type silicon layer is an N-type amorphous silicon layer.

In one embodiment, the solar cell further comprises a tunneling dielectric layer disposed on the light-receiving surface of the silicon substrate, the intrinsic silicon layer disposed on the tunneling dielectric layer.

In one embodiment, the tunneling dielectric layer is a silicon dioxide (SiO ₂ ) layer.

In one embodiment, the silicon substrate is a single crystal silicon substrate, the intrinsic silicon layer is an intrinsic amorphous silicon layer, and the N-type silicon layer is an N-type amorphous silicon layer.

In one embodiment, the silicon dioxide (SiO ₂ ) layer has a thickness in the range of approximately 1 to 10 nanometers, and the intrinsic amorphous silicon layer has a thickness in the range of approximately 1 to 5 nanometers.

In one embodiment, the non-conductive anti-reflective coating (ARC) layer comprises silicon nitride.

In one embodiment, the light-receiving surface has a textured surface shape and the intrinsic silicon layer matches the textured surface shape of the light-receiving surface.

In one embodiment, the substrate further comprises a back surface opposite the light-receiving surface, and the solar cell comprises a plurality of alternating N-type and P-type semiconductor regions on or on the back surface of the substrate, and a plurality of alternating N-type semiconductor regions. It further includes a conductive contact structure coupled to the P-type and P-type semiconductor regions.

In one embodiment, the solar cell includes a silicon substrate having a light-receiving surface. A tunneling dielectric layer is disposed on the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the tunneling dielectric layer. A non-conductive anti-reflective coating (ARC) layer is disposed on the N-type silicon layer.

In one embodiment, the silicon substrate is a single crystal silicon substrate, and the N-type silicon layer is an N-type amorphous silicon layer.

In one embodiment, the tunneling dielectric layer is a silicon dioxide (SiO ₂ ) layer having a thickness in the range of approximately 1-10 nanometers.

In one embodiment, the non-conductive anti-reflective coating (ARC) layer comprises silicon nitride.

In one embodiment, the light-receiving surface of the substrate has a textured surface morphology, and the N-type silicon layer matches the textured surface morphology of the light-receiving surface.

In one embodiment, the substrate further comprises a back surface opposite the light-receiving surface, and the solar cell comprises a plurality of alternating N-type and P-type semiconductor regions on or on the back surface of the substrate, and a plurality of alternating N-type semiconductor regions. It further includes a conductive contact structure coupled to the P-type and P-type semiconductor regions.

In one embodiment, a method of manufacturing a solar cell comprises forming a tunneling dielectric layer on the light-receiving surface of a silicon substrate, and forming an amorphous silicon layer on the tunneling dielectric layer at a temperature of less than approximately 300 degrees Celsius. do.

In one embodiment, the tunneling dielectric layer comprises chemical oxidation of a portion of the light-receiving surface of the silicon substrate, _{plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide (SiO 2} ), thermal oxidation of a portion of the light-receiving surface of the silicon substrate, and O. _{It is} formed using a technique selected from the group consisting of exposure of the light-receiving surface of a silicon substrate to ultraviolet (UV) radiation in a 2 or O _{3 environment.}

In one embodiment, forming the amorphous silicon layer involves forming an intrinsic amorphous silicon layer, the method comprising forming an N-type amorphous silicon layer on the amorphous silicon layer at a temperature of less than approximately 300 degrees Celsius. , And forming an antireflective coating (ARC) layer on the N-type amorphous silicon layer at a temperature of less than approximately 300 degrees Celsius.

In one embodiment, forming the amorphous silicon layer comprises forming an N-type amorphous silicon layer, the method comprising an antireflection coating (ARC) on the N-type amorphous silicon layer at a temperature of less than approximately 300 degrees Celsius. It further comprises forming a layer.

100: substrate
102: light-receiving surface
104: back surface

Claims (22)

Forming a tunneling dielectric layer on the light-receiving surface of the silicon substrate,
Forming an intrinsic amorphous silicon layer directly on the tunneling dielectric layer,
Forming an N-type amorphous silicon layer on the intrinsic amorphous silicon layer,
Forming an anti-reflective coating (ARC) layer on the N-type amorphous silicon layer,
Solar cell manufacturing method. The method of claim 1,
Forming the N-type amorphous silicon layer comprises forming an N-type amorphous silicon layer at a temperature of less than approximately 300 degrees Celsius,
Solar cell manufacturing method. The method of claim 1,
Forming the anti-reflective coating (ARC) layer comprises forming an anti-reflective coating (ARC) layer at a temperature of less than approximately 300 degrees Celsius,
Solar cell manufacturing method. The method of claim 1,
Forming the anti-reflective coating (ARC) layer comprises forming silicon nitride on the N-type amorphous silicon layer,
Solar cell manufacturing method. The method of claim 1,
The step of forming the intrinsic amorphous silicon layer comprises forming an intrinsic hydrogenated amorphous silicon layer,
Solar cell manufacturing method. The method of claim 1,
Forming the N-type amorphous silicon layer comprises forming a phosphorus-doped amorphous silicon layer,
Solar cell manufacturing method. The method of claim 1,
Further comprising the step of exposing the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation,
Solar cell manufacturing method. The method of claim 1,
Further comprising performing a cleaning procedure using a combination of HF and O _3,
Solar cell manufacturing method. The method of claim 1,
The forming of the tunneling dielectric layer includes chemical oxidation of a portion of the light-receiving surface of the silicon substrate, _{plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide (SiO 2} ), and the light-receiving surface of the silicon substrate. And thermal oxidation of a portion of the O ₂ or O ₃ environment, comprising using a technique selected from the group consisting of exposure of the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation,
Solar cell manufacturing method. Forming a tunneling dielectric layer on the light-receiving surface of the silicon substrate,
Forming an intrinsic amorphous silicon layer directly on the tunneling dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) technique, and
Forming an N-type amorphous silicon layer on the intrinsic amorphous silicon layer,
Forming an anti-reflective coating (ARC) layer on the N-type amorphous silicon layer,
Solar cell manufacturing method. The method of claim 10,
The step of forming the N-type amorphous silicon layer comprises forming the N-type amorphous silicon layer using a plasma-enhanced chemical vapor deposition (PECVD) technique.
Solar cell manufacturing method. The method of claim 10,
Forming the anti-reflective coating (ARC) layer comprises forming an anti-reflective coating (ARC) layer at a temperature of less than approximately 300 degrees Celsius,
Solar cell manufacturing method. The method of claim 10,
Forming the anti-reflective coating (ARC) layer comprises forming silicon nitride on the N-type amorphous silicon layer,
Solar cell manufacturing method. The method of claim 10,
The step of forming the intrinsic amorphous silicon layer comprises forming an intrinsic hydrogenated amorphous silicon layer,
Solar cell manufacturing method. The method of claim 10,
Forming the N-type amorphous silicon layer comprises forming a phosphorus-doped amorphous silicon layer,
Solar cell manufacturing method. The method of claim 10, further comprising exposing the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation. The method of claim 10,
Further comprising performing a cleaning procedure using a combination of HF and O _3,
Solar cell manufacturing method. The method of claim 10,
The steps of forming the tunneling dielectric layer include chemical oxidation of a portion of the light-receiving surface of the silicon substrate, _{plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide (SiO 2} ), thermal oxidation of a portion of the light-receiving surface of the silicon substrate, and O _2. Or using a technique selected from the group consisting of exposure of the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation in an _{O 3 environment,}
Solar cell manufacturing method. The method of claim 1,
Prior to forming the tunneling dielectric layer, further comprising depositing a phosphorus-diffused epitaxial layer on the light-receiving surface of the silicon substrate,
Forming the tunneling dielectric layer comprises forming a tunneling dielectric layer on the phosphorus-diffused epitaxial layer on the light-receiving surface of the silicon substrate,
Solar cell manufacturing method. The method of claim 1,
The forming of the tunneling dielectric layer on the light-receiving surface of the silicon substrate comprises exposing the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation and then annealing to form a tunneling dielectric layer on the light-receiving surface of the silicon substrate. ,
Solar cell manufacturing method. The method of claim 10,
Before forming the tunneling dielectric layer, further comprising depositing a phosphorus-diffused epitaxial layer on the light-receiving surface of the silicon substrate,
Forming the tunneling dielectric layer comprises forming a tunneling dielectric layer on the phosphorus-diffused epitaxial layer on the light-receiving surface of the silicon substrate,
Solar cell manufacturing method. The method of claim 10,
The forming of the tunneling dielectric layer on the light-receiving surface of the silicon substrate comprises exposing the light-receiving surface of the silicon substrate to ultraviolet (UV) radiation and then annealing to form a tunneling dielectric layer on the light-receiving surface of the silicon substrate. ,
Solar cell manufacturing method.

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