KR20200139294A - Delayed Reset for Code Execution from memory Device - Google Patents

Abstract

The memory device includes nonvolatile memory (NVM) and circuitry. This circuit prepares and initializes the NVM to perform memory access operations for the processor, and prevents the processor from bootstrapping during at least part of the preparation and initialization of the NVM, so that memory access operations are received from the processor before the NVM is ready. It is structured to ensure that it doesn't work.

Description

Delayed Reset for Code Execution from memory Device}

The present invention relates to a general digital system, and more particularly to an apparatus and method for a reset system comprising a microcontroller and a non-volatile memory.

Digital systems typically include one or more processors (e.g., CPU, MCU, GPU, DSP, and others), and non-volatile memory (e.g., flash memory devices) for storing software or firmware code as well as data. Use.

Various techniques are known in the art for resetting and initializing the processor and its peripherals, for example at power-up. For example, Le et al., "A Long Reset-Time Power-On Reset Circuit with Brown-Out Detection Capability," (A Long Reset-Time Power- On Reset Circuit with Brown-Out Detection Capability), describe the power-on-reset (POR) circuit.

Another POR circuit is described by Tanzawa as "A process and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage." "(IEEE International Symposium on Circuits and Systems (ISCAS), June, 2008). This paper describes the operating principle of a power-on-reset circuit based on a bandgap reference voltage, and a design output voltage higher than a bandgap voltage of 1.25V can be implemented.

Embodiments of the present invention described herein provide a memory device including a non-volatile memory (NVM) and circuitry. The circuitry prepares and initializes the NVM to perform a memory access operation for a processor; And preventing the processor from bootstrapping during at least part of the preparation and initialization of the NVM, thereby ensuring that no memory access operations are received from the processor before the NVM is ready.

In some embodiments, the circuit is configured to prevent the processor from bootstrapping by holding the processor in a reset state during at least some of the initialization and preparation of the NVM. In one embodiment, the NVM is configured to store a boot-code of the processor, and the circuit is configured to release the processor from the reset state after at least part of the initialization and preparation of the NVM, and subsequently boot-code (boot code) is provided to the processor.

In another embodiment, the NVM is configured to store the boot-code of the processor, and (i) an alternative code that prevents the processor from being bootstrapped during at least part of initialization and preparation of the NVM Respond to a request from the processor for the boot-code by providing; And (ii) after at least some of the initialization and preparation of the NVM, by responding to a subsequent request from the processor for the boot-code by providing the boot-code, the circuit prevents the processor from bootstrap. Is configured to

In one embodiment, the replacement code causes the processor to iterate until at least part of the initialization and preparation of the NVM is complete. In another embodiment, the replacement code includes a first part that is executed once, and a second part that is repeatedly executed until at least part of the initialization and preparation of the NVM is completed. In another embodiment, the first part includes an instruction to load a register of the processor.

In some embodiments, the NVM and the circuit are packaged in the same integrated circuit (IC) package.

A method of a memory device is additionally provided with an embodiment of the present invention. The method includes the steps of using a circuit in the memory device, initializing and preparing a non-volatile memory (NVM) in the memory device to perform a memory access operation for a processor, and preparing an NVM, and Preventing the processor from bootstrapping during at least part of the initialization, thereby ensuring that no memory access operation is received from the processor before the NVM is ready by the circuit of the memory device.

The invention will be better understood in conjunction with the drawings from the following detailed description of its embodiments:

1 is a block diagram schematically showing a computer system with a processor-reset generated by a flash device having a system-reset input, according to an embodiment of the present invention.
2 is a block diagram schematically showing a computer system having a processor-reset output generated by a flash device having an internal POR circuit, according to another embodiment of the present invention.
3 is a timing diagram schematically showing a boot sequence of a computer system having a processor-reset generated by a flash-device according to an embodiment of the present invention.
4 is a block diagram schematically showing a computer system having a modified boot instruction generated by a flash device, according to an embodiment of the present invention.
5 is a block diagram schematically showing a computer system having a modified boot sequence generated by a flash device, according to another embodiment of the present invention. And
6 is a timing diagram schematically illustrating a boot sequence of a computer system having a processor-stall in accordance with some embodiments of the present invention.

In a computer system including a processor (eg, a central processing unit (CPU)) and a memory device, the initialization time of the memory device may be longer than the initialization time of the processor. In this case, after a reset or power-up, the processor is ready for execution before the memory device is ready to provide the necessary code or data, which can prevent successful booting of the computer system.

Specifically, in this scenario, the boot-code of the processor is a flash device-the flash device determines the time required to complete some analog tasks, the built-in-self-test (BIST) execution time, and/or the time required to perform security-related tasks. It is common when stored in-which can take a long time to prepare, including.

Thus, in a computer system that boots with code stored in a flash device, it may be necessary to provide a processor with a delayed reset such that the processor attempts to boot only when the flash device is ready.

One way to create a properly delayed reset for the processor is to use a reset circuit with a time delay that is longer than the maximum expected time the flash device should prepare. However, this requires the addition of special circuitry; The fluctuations and uncertainties in the time required for the flash device to be ready can take longer than necessary to further delay the startup of the computer system.

Embodiments of the invention described herein provide an improved method and apparatus for allowing a processor to initiate a boot sequence immediately after (and never before) a memory device is ready. The following description mainly refers to a CPU and a flash device by way of example, but the disclosed technology is applicable to other suitable types of processors and memory/storage devices.

In some embodiments, a memory device (eg, a flash device) includes both a nonvolatile memory (NVM) array and circuitry packaged together within the same integrated circuit (IC) package. Among other tasks, the circuit is configured to initialize and prepare the NVM to execute a memory access operation for the processor (e.g., CPU), and to ensure that no memory access operation has been received from the processor before the NVM is ready. do. The circuit ensures the condition by preventing the processor from bootstrapped during at least part of the initialization and preparation of the NVM.

The circuitry of the memory device can use a variety of techniques to prevent the processor from bootstrapping until the NVM is ready. Some examples are detailed below. The techniques described herein are provided purely by way of example, and any other suitable technique may be used in alternative embodiments.

In one example, the circuit keeps the processor in a reset state until the NVM is ready, and then releases the processor from the reset state. In another example, the processor's boot code is stored in the NVM. The circuit responds differently to the processor's request for boot-code depending on whether the NVM is ready. When the NVM is ready, the circuit provides the requested boot-code to the processor. If the NVM is not ready, the circuit provides the processor with alternative code that prevents the processor from bootstrapping until the NVM is ready.

In one embodiment, the memory device includes a processor-reset output pin coupled to the reset input of the processor. The memory device further includes a processor-reset circuit for releasing a reset input of the processor only after the memory device is prepared. Alternatively, the reset input to the processor may be released slightly before the memory is ready, taking into account the time required for the processor to release the reset and start the boot process.

In another embodiment of the present invention, the memory device does not include an extra reset-out pin, and the processor can access the memory device for booting before the memory device is ready (e.g. , The processor and the memory device can share the same reset input). However, if the processor accesses the memory device while the memory device is not yet ready, the memory device will present an instruction or sequence of instructions to the processor that will cause the processor to stop instead of providing the requested boot-code. For example, a processor can repeatedly obtain a branch-to-self instruction. Only when the memory device is ready the processor gets the actual boot-code stored in the memory device.

Thus, in an embodiment according to the present invention, by applying an appropriate time reset to the processor until the memory device is ready, or by stopping the processor using a stop command or a stop command sequence, the memory device Ensures that the boot sequence does not start. No additional reset circuit is required and the boot delay time is short.

SYSTEM DESCRIPTION

In the computer system according to the embodiment of the present invention, the boot-code of the CPU may be stored in a nonvolatile memory. In the following description, the nonvolatile memory will be referred to as flash. Flash is one of the technologies that can store the boot-code of a computer system, but the disclosed technology is not limited to flash. Embodiments in accordance with the present invention may include any other type of non-volatile memory.

Various elements of a computer system, such as flash devices, may take different times to escape from reset (for example, when power is applied to the system), and care must be taken to ensure that the CPU does not start the boot sequence before the flash memory is ready. . For example, a flash memory typically executes an initialization sequence (eg, built-in-self-test (BIST) or security policy enforcement) when terminating a reset; And after enough time the CPU is ready to access the flash, the CPU can be ready to access it. Thus, the CPU will have to start the boot sequence after the flash is ready; Therefore, the CPU and flash reset sources are usually separate.

Flash-Device-Driven Processor Reset

In the embodiment illustrated in Figures 1 and 2, in Figures 1 and 2 below, the flash device includes a processor-reset output signal coupled to a CPU reset input. The flash device activates the processor-reset when the flash is not ready for access, so that the CPU only boots from the flash when the flash is ready.

1 is a block diagram schematically showing a computer system 100 with a processor-reset generated by a flash device having a system-reset input, according to an embodiment of the present invention.

This system includes a CPU 102, a RAM 104, a peripheral device 106 and a flash device 108. CPU 102 communicates with RAM 104, Peripherals 106 and Flash 108 via bus 110 (bus 110 is, for example, a modern microprocessor bus structure (Advanced Microprocessor Bus Architecture); in some embodiments, the bus 110 is a serial-processor-interface (SPI) or inter-integrated circuit-bus that interfaces between the AMBA and the AMBA bus and the flash device. It includes an interface module such as Inter-Integrated-Circuit-Bus) (I2C); other buses may be used in other embodiments).

The flash device 108 is a non-volatile storage array configured to store data/code (e.g., boot-code) and retain the stored data/code when power is not supplied to the flash device. A storage-array 112, an initialization circuit 114, and a processor-reset circuit 116 are included. Array 112 and circuits 114 and 116 are typically packaged together in the same integrated circuit (IC) package.

Computer system 100 further includes an External Reset source 118 connected to the flash device. In some embodiments, the external reset source generates the reset output when the power applied to the system is below a preset level (and, in some embodiments, for a preset time after the power reaches a preset level). It includes a power-on reset (POR) that activates the power-on reset (reaching a preset level) and activates the reset output.

In the exemplary embodiment of FIG. 1, when the external reset source 118 deactivates its reset output, the initialization circuit 114 is a flash initialization sequence (eg, BIST). Start. When the initialization sequence is completed, the initialization circuit signals the processor-reset circuit 116 that the flash device is ready.

The processor-reset circuit 116 transmits the processor-reset output of the flash device only when the external reset signal is not activated and the ready input generated by the initialization circuit 114 is activated. It is configured to be disabled.

In some embodiments of the invention, there is no external reset source, and the flash device includes a Power-On reset circuit.

2 is a block diagram schematically showing a computer system 200 having a processor-reset output generated by a flash device having an internal POR circuit, according to an embodiment of the present invention. Like system 100 (FIG. 1 ), system 200 includes CPU 102, RAM 104, peripherals 106 and bus 110. However, unlike system 100, system 200 does not include an external reset source. Instead, the flash device 208 includes a Power-On-Reset (POR) circuit 202 (flash 208 is the same as the flash 108 in FIG. 1).

The POR circuit 202 is configured to disable the reset output when the supply voltage of the flash reaches a preset level. The reset output of the POR circuit 202 is used to reset the flash device 208 instead of the reset output from the external reset source 118 (FIG. 1). In all other respects, flash 208 is identical to flash 108: when POR circuit 202 deactivates its reset output, initialization circuit 114 initiates a flash initialization sequence; Upon completion of the initialization sequence, the initialization circuit notifies that the flash device is ready. The processor-reset circuit 116 disables the processor-reset output of the flash device, allowing the CPU 102 to start the boot process.

Thus, according to the exemplary embodiment of Figs. 1 and 2, the CPU accesses the flash only when the flash is ready, and the boot-code executed by the CPU is not damaged. By connecting the CPU's reset input to the flash, you can accurately match the CPU's boot sequence. Booting does not start before the flash is ready and there is no needless delay.

The configurations of computer systems 100 and 200, and flash devices 108 and 208 are examples of configurations shown for clarity conceptually. Any other suitable configuration may be used in other embodiments. For example, the flash memories 108 and 208 may be replaced with Electrically Erasable Programmable Read-Only Memory (EEPROM) or Read-Only Memory (ROM) and any other type of nonvolatile memory or storage device such as a hard disk. have. The CPU 102 may include a plurality of CPU units of the same or various types. There may be more than one flash memory and more than one bus in the system.

Because it may take some time for the CPU to complete the reset, in some embodiments the processor-reset output is disabled for a predetermined amount of time before the initialization circuit 114 completes initialization so that booting is not unnecessarily delayed. In some embodiments, processor-reset output deactivation may be delayed by a pre-set amount of time after the flash is ready, and in other embodiments, flash 108 (or 208) may include multiple processor-reset outputs. , It can be coupled to multiple processors and other system components, and the external reset input (or POR reset) and reset-deactivation of each output for the time the flash is ready can be configured individually. .

In this specification, the initialization circuit 114, the processor-reset circuit 116, and the POR circuit 202 (if used) are collectively referred to as the "circuitry" of the flash device. In other embodiments, any other suitable circuit configuration may be used.

3 is a timing diagram schematically illustrating a boot sequence of a computer system with a processor-reset generated by a flash device, for example the system of FIGS. 1 and 2 according to an embodiment of the present invention. This figure describes the activity in the form of a graph along the time axis 302: a supply voltage graph 304, a power-on reset graph 306, and a flash. Flash Activity graph 308, CPU Reset graph 310, and CPU Activity graph 312. Five important time events are displayed along the time axis from T0 to T4.

The time axis starts at time-event T0 314. The supply voltage level is 0V and the system is inactive. At time-event T1 316, the power supply voltage starts ramping and powers the system; At time-event T2 318, the supply voltage reaches a predetermined level (90% of VCC in the embodiment illustrated in FIG. 3). The POR unit maintains a reset state until a time-event T2 318. When the POR leaves the reset, flash initialization starts and ends at time-event T3 (320).

The CPU Reset (graph 310) is held from T0 to T3 (by flash unit). At T3, the flash device releases the CPU reset. After a while, at time-event T4 322, the CPU accesses the flash device to execute the flash sequence (some post-reset pre-boot operations by the CPU may require time from T3 to T4).

Thus, according to the timing diagram shown in Fig. 3, the CPU will access the flash with a short delay only when the flash device is ready.

The timing diagram 300 illustrated in FIG. 3 is not drawn at a constant ratio, and a longer horizontal distance does not necessarily mean a longer time period. Further, the timing diagram 300 is an exemplary diagram shown for conceptual clarity only. Any other suitable timing diagram may be used in other embodiments of the present invention. For example, in some embodiments, CPU reset 310 may be terminated just before flash initialization is complete to shorten the delay from the time flash initialization completes at T4 322.

Boot-Code Manipulation

In some applications, adding a processor-reset pin to a flash device may be undesirable or impractical. For example, the pins of the flash must conform to the pinout standard, or the flash must be pin compatible with other flash devices. According to the embodiments of the present invention presented herein, the CPU may start the boot process before the flash is ready, but the flash device effectively waits until the flash is ready by modifying the boot-code read by the CPU. .

4 is a block diagram schematically illustrating a computer system 400 having a modified boot instruction generated by a flash device in accordance with an embodiment of the present invention. The system is a CPU 102, RAM 104, Peripherals 106, Bus 110, and External Reset Source, which may all be identical to each unit of system 100 (FIG. 1). ) (118).

The flash device 408 includes a storage array 112 and an initialization circuit 114; These may be the same as the corresponding units of system 100. The flash 408 also includes a Stall-code unit 402 and a multiplexer (MUX) 404.

The stop-code unit 402 is configured to output computer instructions that cause the CPU to stop. For example, the instruction may be a branch-to-self ("b") instruction that causes the CPU to read the instruction indefinitely at the same location. The code of the stop command may be hard-wired or stored in a nonvolatile cell of the flash 408.

The initialization circuit 114 transmits data output by the stop-code 402 when the initialization circuit indicates that the flash is not ready, and when the bus 110 or the initialization circuit indicates that the flash is ready, the storage array 112 is It is combined with a multiplexer 404 configured to route the output data.

Thus, according to the exemplary configuration shown in Fig. 4, the CPU can start the boot sequence when the flash is not ready, but an instruction to be read by the CPU stops the CPU. When the flash is ready, as indicated by the initialization circuit 114, the CPU will read the correct boot sequence from the storage-array 112.

5 is a block diagram schematically illustrating a computer system 500 having a modified boot sequence generated by a flash device, according to an embodiment of the present invention. The system 500 is the same as the system 400 of FIG. 4, and the flash 508 is a Stall Sequence unit 502 instead of the Stall Instruction unit 402 of the flash 408. It is the same as the flash 408 except that it includes.

The Stall Sequence unit 508 contains a sequence of instructions that the CPU executes when the flash is not ready (a detailed example of the instruction set of the ARM processor will be described below). The stop sequence unit tracks the accesses performed by the CPU and transmits the data corresponding to the multiplexer 404 (in an alternative embodiment, the address part of the bus 110 is input to the stop sequence unit 502 and the stop sequence The unit sends data to the corresponding input address).

The code for the sequence of commands may be hard-wired, or may be stored in a non-volatile cell of flash 508 (in some embodiments, the code for the sequence of commands is different from the boot-code. It is stored in a bank, and in other embodiments the sequence of commands is transferred from the flash cell to the volatile memory (e.g., flip flop or SRAM memory) immediately after reset and then read from the volatile memory). The multiplexer transfers data from the stop sequence unit 503 when the flash is not ready (indicated by the initialization circuit 114), and from the storage array 112 when the flash is ready.

Accordingly, according to the exemplary configuration of FIG. 5, the CPU may execute a preset command sequence when the flash is not ready, and execute the boot sequence stored in the storage array 112 when the flash is ready.

In some embodiments, the switching from execution of the stop sequence to execution of the boot sequence must be performed in a known CPU state (not in any instruction in the instruction sequence) to ensure consistency. Flash 508 may include circuitry configured to delay a ready indication until the sequence reaches a pre-set stage (e.g., a pre-set address input from bus 110). And ensure that the transition from the stop sequence to the boot sequence is performed in the correct CPU state.

As can be seen, the configurations of the flashes 408 and 508, multiplexer (mux) 404, initialization circuit 114, and storage array 112 shown in FIGS. 4 and 5 are shown for conceptual clarity only. This is an example configuration. Any other suitable configuration may be used in other embodiments. For example, the multiplexer 404 may be embedded in the bank-select logic of the flash array. In other embodiments, in some embodiments, a subset of the address wires of bus 110 is input to a stop sequence unit.

In this specification, the initialization circuit 114, the stop-code unit 402 or 502, and the MUX 404 are collectively referred to as "circuits" of the flash device. In other embodiments, any other suitable circuit configuration may be used.

6 is a timing diagram 600 schematically illustrating the boot sequence of a computer system with a processor-stop in accordance with some embodiments of the present invention. This diagram describes the operation in the form of a graph along the time axis 602: a supply voltage graph 604, a power-on reset graph 606, and a flash operation graph. (Flash Activity graph) 608, CPU Reset graph 610, and CPU Activity graph 612 (graphs 604, 606 and 608 are of the timing diagram 300 shown in FIG. Same as graphs 304, 306 and 308 respectively).

Four important time-events are displayed along the time axis (T0-T3).

The time axis starts at time-event T0 (614). The supply voltage level is 0V and the system is inactive. At time-event T1 616, the supply voltage starts ramping and starts powering up the system. At time-event T2 618, the supply voltage reaches a predetermined level (eg, 90% of VCC in the embodiment illustrated in FIG. 3). The POR unit maintains a reset state until a time-event T2 618. Flash initialization begins when POR is present in reset and ends at time-event T3 (620).

At T2 618, the CPU Reset (graph 610) is released, and the CPU attempts to boot while reading data from the flash device. However, while the flash device is being initialized (from T2 to T3), the CPU reads a stop-code from the flash. Only when flash initialization is complete, the CPU reads the actual boot data from the flash and executes the boot sequence.

Thus, according to the timing diagram 600 shown in Fig. 6, the CPU is released from reset when the flash is initialized, but will read a stop-code from the flash until the initialization is complete. The CPU reads the actual boot-code from flash only when the flash is ready.

The timing diagram 600 shown in FIG. 6 is not drawn at a constant rate, and a longer horizontal distance does not necessarily mean longer each time period. Further, timing diagram 600 is an exemplary diagram shown for conceptual clarity only. Any other suitable timing diagram may be used in other embodiments of the present invention.

Stall-Instruction Example

In some processor architectures, the processor boot sequence can read the boot-code at address 0x00000000.

If the flash device is not ready, the stop-instruction unit 402 (Figure 4) will send a loop of "branch-to-self" instructions ('b.') to the CPU.

The stop sequence to be executed by the CPU is as follows.

● 'b .' // branch instruction

● 'b .' // branch instruction

● 'b .' // branch instruction

● ....

● 'b .' // branch instruction

The boot-code is stored in a storage array 112 starting at address 0x0000.

Stall Sequence Example

In some processor architectures, the processor boot sequence first loads some data or configuration from a memory device (eg, instruction pointer, stack pointer, etc.) and then begins executing the main boot-code.

The boot sequence may include the following sequence, for example.

1. Load a word into the stack pointer (SP) register at address 0;

2. Load a word into the program counter (PC) register at address 4

3. Start code execution at the address pointed to by the PC.

In order for the memory device to complete the internal reset sequence, the stall sequence unit 502 returns values for PC and SP when address 0 or 4 is accessed, and when address 0 or 4 is accessed. It is stored at address position 0. The CPU reads addresses 0 and 4 only once, then continues reading the branch-to-self instruction until the flash device is ready.

For example, if the boot vector contains:

0x000: 0x20001000 // SP value

0x004: 0x00000100 // PC value

...

0x100: [boot-code starts here]

When the flash device is not ready, it sends the next sequence to the CPU.

First access-0x20001000 // SP initialization

On second access-0x00000100 // PC initialization

On further access-"b." // branch to own code

The configuration of computer systems 100, 200, 400, 500; Configuration of flash devices 108, 208, 408 and 508; And the configuration of another unit described above with respect to FIGS. 1 and 2. 1, 2, 4, and 5 are examples of configurations shown purely for conceptual clarity.

For example, in other embodiments including a system configuration having a plurality of flash devices and/or a plurality of CPU units, any other suitable configuration may be used, some or all of which have separate reset inputs.

Some of the elements described in FIGS. 2 and 3 may include an Application-Specific Integrated Circuit (ASIC) using software, hardware, or a combination of hardware and software elements, or It can be implemented using suitable hardware, such as a Field-Programmable Gate Array (FPGA).

Although the embodiments described herein primarily deal with computer systems incorporating non-volatile memory, the methods and systems described herein can also be used in other applications, such as computer systems having other storage devices such as hard disks. Accordingly, it will be appreciated that the above-described embodiments have been cited by way of example, and that the invention is not limited to those specifically shown and described above. Rather, the scope of the invention includes combinations and subcombinations of the various features described above, as well as variations and modifications that may occur to those skilled in the art upon reading the foregoing description and are not disclosed in the prior art. Documents incorporated by reference in this patent application are the definitions of the present specification, except where any term is defined in these consolidated documents in a manner contrary to the definitions made expressly or implicitly herein. Only to be considered.

Claims (16)

In the memory device,
Nonvolatile memory (NVM); And
Circuit,
Prepare and initialize the NVM to perform a memory access operation for the processor; And
By preventing the processor from bootstrapping during at least part of the NVM's preparation and initialization,
The memory access operation is not received from the processor before the NVM is ready.
Configured to make sure
Device.
The method of claim 1,
The circuit,
During at least some of the initialization and preparation of the NVM,
Keeping the processor in a reset state prevents the processor from being bootstrapped.
Configured to prevent
Device.
The method of claim 2,
The NVM is configured to store the boot-code of the processor,
The circuit is configured to release the processor from the reset state after at least some of the initialization and preparation of the NVM,
Subsequently providing the boot-code to the processor
Device.
The method of claim 1,
The NVM is configured to store the boot-code of the processor,
Responding to a request from the processor for the boot-code by providing replacement code that prevents the processor from being bootstrapped during at least some of the initialization and preparation of the NVM; And after at least some of the initialization and preparation of the NVM, by responding to a subsequent request from the processor for the boot-code by providing the boot-code,
The circuit is configured to prevent the processor from bootstrap
Device.
The method of claim 4,
The replacement code,
Causing the processor to repeat until at least part of the initialization and preparation of the NVM is completed.
Device.
The method of claim 4,
The replacement code,
The first part executed once, and the second part repeatedly executed until at least part of the initialization and preparation of the NVM is completed.
Including
Device.
The method of claim 6,
The first part,
Instruction to load the register of the processor
Containing
Device.
The method of claim 1,
The NVM and the circuit,
Packaged in the same integrated circuit (IC) package
Device.
In the method of a memory device,
Using a circuit in the memory device,
Initializing and preparing a nonvolatile memory (NVM) in the memory device to perform a memory access operation for a processor; And
Preventing the processor from bootstrap during at least part of the preparation and initialization of the NVM, thereby ensuring that no memory access operation is received from the processor before the NVM is ready by the circuit of the memory device.
Including
Way.
The method of claim 9,
Preventing the processor from being bootstrapped,
Maintaining the processor in a reset state during at least some of the initialization and preparation of the NVM
Including
Way.
The method of claim 10,
Storing the boot-code of the processor in the NVM,
Releasing the processor from the reset state after at least part of the initialization and preparation of the NVM, and
Then providing the boot-code to the processor
Including
Way.
The method of claim 9,
Including the step of storing the boot-code of the processor in the NVM,
Preventing the processor from being bootstrapped,
Responding to a request from the processor for the boot-code by providing replacement code that prevents the processor from being bootstrapped during at least some of the initialization and preparation of the NVM; And
After at least part of the initialization and preparation of the NVM, responding to a subsequent request from the processor for the boot-code by providing the boot-code
Further comprising
Way.
The method of claim 12,
The replacement code,
Causing the processor to repeat until at least part of the initialization and preparation of the NVM is completed.
Way.
The method of claim 12,
The replacement code is,
The first part executed once, and the second part repeatedly executed until at least part of the initialization and preparation of the NVM is completed.
Including
Way.
The method of claim 14,
The first part,
Instruction to load the register of the processor
Containing
Way.
The method of claim 9,
The NVM and the circuit,
Packaged in the same integrated circuit (IC) package
Way.

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