KR20200067218A - Methods and devices for increasing reactor processing batch size - Google Patents

Abstract

A method of increasing the reaction chamber batch size and a plasma processing apparatus using the method are provided. The method includes: (a) processing a portion of the batch of wafers within the reaction chamber, the processing processing a portion of the batch of wafers, which results in deposition of at least some off-target material on the inner surfaces of the reaction chamber. To do; (b) performing center-batch reaction chamber processing to stabilize the off-target deposition material accumulated on the inner surfaces of the reaction chamber; And (c) processing another portion of the batch of wafers within the reaction chamber.

Description

Methods and devices for increasing reactor processing batch size

Cross reference to related applications

This application claims the benefit of U.S. patent application no. It is incorporated herein by reference.

Semiconductor processing typically occurs in specialized processing devices where it is often desirable to achieve optimized and efficient throughput. Such an apparatus may include a reaction chamber housing a batch of wafers during processing. The reaction chamber may also include hardware (eg, substrate support pieces, showerheads, etc.) of various pieces used in semiconductor manufacturing. In some cases, the reaction chamber may be processed or seasoned before being used to process substrates. Reaction chamber processing may take a number of different forms, and may be performed for a variety of reasons. Also, in some cases, the total number of wafers that can be processed between the reaction chambers is on various internal components of the reaction chamber, where processing is interrupted for cleaning and the chamber needs to be shut down. It may be limited due to the accumulation of the off-target film deposited on.

Certain embodiments herein relate to a method of increasing the reaction chamber batch size, the method comprising: (a) processing a portion of a batch of wafers within the reaction chamber, the processing on the inner surfaces of the reaction chamber. Processing a portion of the batch of wafers that results in deposition of at least some off-target material; (b) performing center-batch reaction chamber processing to stabilize off-target deposition materials accumulated on the inner surfaces of the reaction chamber; And (c) processing another portion of the batch of wafers within the reaction chamber.

The methods may further involve repeating steps (b) and (c) until processing of the batch of wafers is complete.

In some embodiments, the reaction chamber batch size is the number of wafers that can be processed in the reaction chamber between reaction chamber cleaning cycles.

The methods may further involve seasoning the interior surfaces of the reaction chamber prior to batch processing inside the reaction chamber.

In some embodiments, the step of seasoning the interior surfaces of the reaction chamber involves applying a coating of the same material used for deposition on the batch of wafers during step (a) or step (c).

In some embodiments, step (a) or step (c) may involve depositing material on the wafer in a batch of wafers.

In some embodiments, the step of seasoning includes applying a coating to the inner surfaces of the reaction chamber by atomic layer deposition (ALD) while no wafers are present in the reaction chamber.

The methods may further involve cleaning the interior surfaces of the reaction chamber following completion of step (c).

The methods may further involve the step (d) of cleaning the interior surfaces of the reaction chamber after processing of the batch of wafers is complete.

In some embodiments, step (b) is performed at specified intervals of the total batch accumulation limit of the batch of wafers. Also, the specified intervals may be determined empirically. In addition, the specified intervals may occur prior to the accumulation of a detrimental level of material on the interior surfaces of the chamber, causing flaking of materials and generation of wafer defects and/or particles.

In some embodiments, the total batch accumulation limit is the thickness of material accumulated on the interior surfaces of the reaction chamber where processing is impaired such that cleaning of the reaction chamber is required before further processing.

In some embodiments, step (b) involves depositing a film that binds to materials accumulated on the interior surfaces of the reaction chamber. In addition, the compressibility of the deposited film may be improved by adjusting any one or more selected from the group consisting of radio frequency (RF) power levels, reaction chamber pressure, or RF processing time.

In some embodiments, step (b) involves exposing the accumulated material on the inner surfaces of the reaction chamber to the plasma after the materials have accumulated to a specified thickness. In addition, plasma exposure may be performed at a pressure in the range of 2 Torr to 10 Torr to facilitate plasma diffusion into the film deposited on the inner surfaces of the reaction chamber. In addition, the plasma may be ignited on the faceplate of the showerhead in the reaction chamber. Further, the plasma may be derived from hydrogen, helium, argon, or any one source selected from the group consisting of nitrogen-containing sources. In addition, exposure to plasma may deposit approximately 200 mm 3 of film on materials accumulated on the interior surfaces of the reaction chamber. In addition, purging may be deactivated so that the plasma is uniformly extinguished throughout the reaction chamber. In some embodiments, the plasma has a frequency of 400 kHz.

In some embodiments, the deposited film stabilizes materials on the inner surfaces of the reaction chamber. In addition, exposure to plasma may densify the deposited film to stabilize materials on the inner surfaces of the reaction chamber. Further, the compressibility of the film is by a method selected from the group consisting of applying RF power in the range of 2 kw to 7 kw, applying a high pressure in the range of 2 torr to 10 torr, or using an RF plasma time of 0.2 s to 10 s. May be increased.

The methods may further include the step (d) of grounding the reaction chamber. In addition, the grounded reaction chamber may facilitate plasma diffusion out of the reaction chamber. In some embodiments, a showerhead is powered that may be configured to deliver deposition gas to a batch of wafers. Also, in some embodiments, a pedestal configured to support the placement of wafers is powered. Also, the plasma used to perform step (d) may be supplied by a remote plasma cleaning unit. The remote plasma cleaning unit may be on-board to the reaction chamber.

Another aspect involves a plasma processing apparatus for processing a substrate. The apparatus includes a reaction chamber including inner chamber surfaces, a substrate support for supporting a substrate within the reaction chamber, and an exhaust port for removing material from the reaction chamber; A remote plasma chamber including a plasma generator for generating plasma in the remote plasma chamber, an inlet for delivering gas to the remote plasma chamber, and an outlet for providing plasma generated in the remote plasma chamber to the reaction chamber; And processing a portion of the batch of wafers within the reaction chamber; Performing center-batch reaction chamber processing to stabilize materials accumulated on the inner surfaces of the reaction chamber as a result of the batch processing; And a controller configured to execute instructions for the operation of processing another portion of the batch of wafers within the chamber.

In some embodiments, the plasma processing device is remote from the reaction chamber.

In some embodiments, the controller is further configured to execute instructions for the operation of cleaning the interior surfaces of the reaction chamber following completion of operation (c).

These and other aspects are further described below with reference to the drawings.

1 illustrates a simplified view of a reaction chamber for processing a substrate using plasma delivered from a remote source.
2 shows the reaction chamber of FIG. 1 with a coating covering the interior surfaces of the chamber.
3 is a process flow diagram illustrating operations for a method according to disclosed embodiments.
4A and 4B are process flow diagrams illustrating operations for a method according to disclosed embodiments.
5A and 5B are example tables showing sample operating conditions for a method according to disclosed embodiments.
6 is an exemplary table showing sample operating conditions for a method according to disclosed embodiments.
7 is a schematic diagram of an exemplary process tool for performing certain disclosed embodiments.
8 is a schematic diagram of another exemplary process tool for performing certain disclosed embodiments.

In the following description, numerous specific details are presented to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other examples, well-known process operations have not been described in detail in order not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments.

In this application, the terms “wafer” and “substrate” are used interchangeably. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise specified, the processing details (eg, flow rates, power levels, etc.) cited herein are configured to process 300 mm diameter substrates, or to process 300 mm diameter substrates. Related to processing chambers, it can be scaled appropriately for substrates or chambers of different sizes. The chambers described herein may be used to process workpieces that may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may be processed in chambers prepared according to certain embodiments include printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro-mechanical devices And various other items.

Introduction

It is desirable to achieve efficient reaction chamber productivity in semiconductor manufacturing. The batches of wafers are typically fed into the reaction chamber for processing on the wafers within the reaction chamber, for example deposition. However, accidental off-target deposition of materials on various interior chamber surfaces, for example side walls of a reaction chamber, may contribute to final particle production, for example by flaking these materials on wafers to be processed in the chamber. have. Flaking of these off-target materials is undesirable because it may contaminate the wafers to be processed, thus degrading the overall quality of the processed batch of wafers.

Conventionally, performing a complete cleaning inside the reaction chamber is the maximum of the number of wafers that can be processed in the reaction chamber before the reaction chamber batch size, a significant likelihood of contamination of the wafer to be processed by particle generation from deposition off the target accumulated in the chamber Required when the number was reached. Performing this cleaning requires emptying the contents held in the reaction chamber for processing, thus potentially reducing throughput and preventing processing of larger batches of wafers within a specified time.

Increasing the reaction chamber batch size will increase productivity (or throughput) by allowing additional wafers to be processed in the reaction chamber between required cleaning cycles. This increase increases the internal reaction chamber components (e.g., chamber interior sidewalls) to prevent one or more of the methods disclosed herein, namely flaking or otherwise creating particles and contaminating wafers to be processed. Achieved by application of processes related to Batch Increase Accumulation Sequence (BIAS), which describe processes where normal wafer processing is temporarily suspended with intermediate, or center-batch, chamber processing to stabilize off-target materials deposited on It may be.

As used herein and throughout this disclosure, flaking is caused by partial or total collapse of off-target deposited materials on the inner surfaces of the reaction chamber onto a batch of wafers to be processed inside the reaction chamber. It may also refer to the form of production. Flaking is an undesirable situation and may introduce defects and/or other particles into the wafer, thereby compromising the quality of the processed batch. In addition to flaking, “peeling” may be observed. Peeling describes a particular type of flaking that uniformly disengages to fall on the wafer during processing from the inner wall to which the top exposed surface of the off-target deposition material was attached.

Reaction chamber

1 provides a simplified illustrative view of a reaction chamber or processing chamber in which the processes and apparatus according to the present disclosure may be implemented. The processing chamber 102 includes chamber walls 103, a chamber floor 104, and a chamber ceiling 105. Located within the processing chamber 102 is a substrate support 106 over which a substrate 107 is placed. The processing chamber 102 also includes an inlet 108 and an exhaust outlet 109. In some embodiments, a remote plasma source 110 is provided over the processing chamber 102. The remote plasma source 110 includes a plasma generator (not shown) for generating plasma within the remote plasma source. The plasma generator includes hardware (eg, coils, electrodes, etc.) for generating plasma, which may be an Inductively Coupled Plasma (ICP), Capacitively Coupled Plasma (CCP), or microwave generated plasma. The remote plasma source 110 is separated from the processing chamber 102 by a showerhead 111 having a plurality of showerhead holes 112. The remote plasma source 110 has an inlet 113 for providing gas used to generate a remote plasma.

Under typical circumstances, a set of wafers, for example one, two to four wafers, is sequentially processed within the processing chamber 102, for example deposition on wafers. For example, four wafers entering processing chamber 102 are processed and then removed. Next, four additional unprocessed wafers may be transferred into processing chamber 102 for processing. Transfer of these sets of wafers until the total target amount or “batch” is reached between the required chamber cleaning cycles may be referred to as “batch processing”. Wafers are processed sequentially at one or more stations (eg, 1, 2, or 4 stations) until the reaction chamber batch size (eg, limit) is reached. The application of BIAS extends the reaction chamber batch size by intermediate processing of off-target deposited materials to prevent these materials from interfering with subsequent wafer processing. Thus, with the application of BIAS, a significant number of wafers may be processed prior to temporarily stopping wafer processing to treat or clean the interior surfaces of the reaction chamber of residue that accumulates from off-target deposition on the reaction chamber.

FIG. 2 illustrates the device shown in FIG. 1 after the inner component surfaces have been coated, for example “seasoned” by applying an undercoat (UCT) such as coating 220, as described further below. Generally, “seasoning” refers to the process of preparing the interior surfaces of a reaction chamber for processing wafers within the reaction chamber. In some embodiments, seasoning may involve coating of silicon oxide (SiO ₂ ) on the inner surfaces or application of UCT. In other embodiments, other suitable materials such as silicon oxides (SiO _X ), nitrides, tungsten, or dielectric materials may be used for seasoning depending on what is deposited in the reaction chamber.

The illustrated coating 220 can also exhibit accumulation of off-target deposition of materials during processing of wafers in the reaction chamber. As used elsewhere in this specification and this disclosure, the term “accumulation” generally describes the build-up of off-target deposited materials on the inner surfaces of the reaction chamber. Likewise, the term “normal accumulation” describes a conventional accumulation process during processing of a batch of wafers in the reaction chamber that is cleaned upon reaching the maximum reaction chamber batch size. The substrate 107, for example a wafer, is not shown in this figure, and the coating 220 is exaggerated for illustrative purposes. In addition, coating 220 may be present in areas not visible in FIG. 2, such as on the inner surfaces of showerhead holes 112. In some embodiments, low recombination material coating 220 covers only surfaces that are on the interior of processing chamber 102.

Processing of the substrate 107, for example a semiconductor wafer, may involve deposition on the substrate by various processes such as ALD. During wafer processing, wafers of specified quantities, for example, one, two or four wafers, may be processed within processing chamber 102 and then cycled to allow entry of new unprocessed wafers. After a certain amount of time has been spent processing a large number of wafers, the material intended for deposition on the wafers may begin to accumulate on unintended locations, such as on chamber walls 103. Eventually, the deposited materials off this target may begin to create, for example flake and drop, or otherwise move particles from chamber walls 103 onto the substrate 107 to contaminate wafer processing.

Thus, implementations of the processes further described in FIGS. 4 and 5A and 5B may fix or stabilize off-target deposition materials on chamber walls. Stabilization of these off-target deposition materials may allow for further in-process processing of substrates 107 until a final cleaning cycle of chamber walls 103 must be performed to extract and dispose of off-target deposition materials. . Generally, the cleaning cycle refers to the removal of unwanted off-target deposition materials from various internal reactor components such as side walls. The reaction chamber is typically cleaned to restart processing of the wafer within the reaction chamber to continue. The chamber cleaning may be wet with liquid phase chemicals, or dry using, for example, plasma. In addition, chamber cleaning may be performed by providing plasma in the reaction chamber, often referred to as “plasma cleaning” for cleaning off-target deposited materials on the interior surfaces. Plasma cleaning may be performed using in situ plasma or remote plasma.

3 shows an exemplary process flow 300 for solving the problems posed by off-target deposition on the inner surfaces of the reaction chamber during batch processing of wafers. Process 300 begins at operation 302, which involves providing one or more wafers to a reaction chamber, such as the process chamber as illustrated in FIG.

In some embodiments, multiple wafers may be entered into the reaction chamber for multi-station sequential processing, and then removed from the reaction chamber upon completion of processing. In other embodiments, the chamber may be configured to process one wafer at a time. The processing of such a plurality of wafers may collectively be referred to as “batch processing”, and the “batch” of wafers is a target accumulated on internal reactor components, particularly sidewalls, due to the processing of the wafers within the reaction chamber. Reaction chamber cleaning cycles before the reactor must be shut down for complete cleaning to continue processing of the wafers without the risk of process drift and/or wafer contamination from particle generation, such as flaking of material deposition out of order. Refers to the total number of wafers that can be processed in the reaction chamber in between. In general, the cleaning cycle is the processing of wafers without the risk of contamination from particle generation, eg flaking of off-target material deposition accumulated on internal reactor components, particularly sidewalls due to previous processing of wafers within the reaction chamber. This entails complete deactivation of the reaction chamber to accommodate complete cleaning before continuing.

Under conventional batch processing procedures, the targeted process throughput may be limited due to the ongoing accumulation of off-target materials on the inner surfaces of the reaction chamber during processing of the batch of wafers. The operation 306 performed after the initial processing of a portion of the batch of wafers, for example, off-target deposition by performing center-batch reaction chamber processing to stabilize off-target materials deposited on the side walls of the reaction chamber. Solve it. Any wafers in the reaction chamber may be removed from the reaction chamber prior to the start of the center-batch processing of operation 306 to prevent unwanted contamination from the center-batch processing. In some embodiments, center-batch processing may involve one or more distinct process variations further described in FIGS. 4A and 4B. After completion of the center-batch processing of the reaction chamber in operation 306, another portion of the batch of wafers may be processed in the reaction chamber in operation 308 before terminating process 300 in operation 310. .

Therefore, the implementation of center-batch reaction chamber processing in operation 306 may increase the total number of wafers that can be processed in the reaction chamber between the required cleaning cycles, thus effectively increasing the batch size of wafers to be processed. Increase. Accordingly, process 300, which includes operation 306, also referred to as BIAS, is required cleaning cycles, for example, where the off-target deposition materials are removed from attaching to the side walls of the reaction chamber. It is desirable to increase the usefulness of the reaction chamber in between, or to increase the total operational throughput of wafers processed in a given reaction chamber by extending the lifetime.

4A shows a comprehensive process flow 400 describing BIAS according to one particular embodiment of the general process described with respect to FIG. 3. 4B will be discussed and described in conjunction with FIG. 4A, for example, some of the central-batch reaction chamber processing performed in operation 306 of process flow 300, and likewise operation 412 of process flow 400. It shows four specific types. After starting in operation 402, those skilled in the art will recognize that the inner surfaces of the reaction chamber may be prepared or seasoned by deposition of a thin film on the inner surface through conventional deposition methods or via ALD. The film deposited in the seasoning operation 404 may be referred to as “pre-coating”, or “undercoating” (UCT), and in some embodiments, a dielectric such as silicon oxide (SiO ₂ ), or other oxide suitable for deposition. It may include. In addition, silicon oxide has a relatively short duration to control the thickness of the deposited film over the course of 500 to 1,200 ALD cycles, for example within a range of at least 100 mm 2 and up to 2,000 mm 2, typically within 700 mm to 1,400 mm 2 It may be deposited as a UCT through ALD.

ALD is a cyclic process of nominal self-limiting steps that results in numerical and minor changes in film thicknesses. The process is characterized by smoothness and conformality. The concept of “cycle” is related to the discussion of various embodiments herein. In general, the ALD cycle is the minimum set of operations used to perform one surface deposition reaction. The result of one cycle is, for example, the creation of at least a portion of the silicon-containing film layer on the substrate surface. Typically, the ALD cycle includes operations to deliver and adsorb at least one reactant to the substrate surface, and then react the adsorbed reactant with one or more reactants to form a partial layer of the film. The cycle may include certain auxiliary operations, such as sweeping one of the reactants or byproducts and/or treating the partial film when deposited. Generally, a cycle includes an example of a unique sequence of operations. As an example, the ALD cycle includes the following operations: (i) delivery/adsorption of a silicon-containing precursor, (ii) purging of a silicon-containing precursor from the chamber, (iii) delivery of a second reactant and plasma, (iv) may include purging of plasma from the chamber. Various ranges of flow rates of precursors, process gases and/or reagents suitable for the production and application of various types of UCTs by ALD are shown in FIG. 5A with a thermal label of “UCT”. Flow rates for ALD processes provided in standard cubic centimeters per minute (sccm), used to apply UCT, as well as additional various center-batch processing coatings, may include the specific ranges shown in FIG. 5A. For example, precursors selected from bis-tert-butyalaminosilane (BTBAS), bisdiethylaminosilane (BDEAS) ((Et ₂ N) ₂ SiH ₂ ), or diisopropylaminosilane (DIPAS), such as silicate glass on the inner surfaces of the reaction chamber, For example, it may flow into the reaction chamber at a volumetric flow rate of 500 to 3,000 sccm to produce and apply UCT of silicon oxide (SiO ₂ ). Other suitable exemplary precursors, or reactants used to produce silicon-containing UCT, may include a variety of other bisalkylaminosilanes, and their alkyl groups may contain 1 to 6 carbon groups. . Further, each of the amine groups may be individually substituted with an alkyl group or a single group or two groups. Also, in some embodiments, an alkenyl modification or alkynyl modification may be employed as precursors or reactants used to produce silicon-containing UCT. In some cases or configurations, different alkyl groups may be employed on the molecule (eg, one or more amines may be substituted with methyl groups, and one or more other amines may be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance of the silane core. Likewise, carrier gases such as argon (Ar) gas may also flow into the reaction chamber as needed to generate UCT.

Next, after seasoning the reaction chamber in operation 404 to apply the UCT as discussed above, a portion of the batch of wafers is provided to the reaction chamber for processing. As previously introduced for process flow 300, batch may refer to the maximum number of wafers that can be processed by the reaction chamber between required chamber cleaning cycles. Portions of the batch may be any number smaller than the entire batch. In some embodiments, the batch may be divided into even quotients of the batch, eg, half, 1/3, 1/4, etc., which are processed by particle generation from deposition beyond the accumulated target in the chamber. It may also be empirically related to the limitations of the previous accumulation, which has a significant potential for contamination of the wafers to be produced. In one particular example, the batch may be divided into quarters following completion of processing where processing of the batch is 25%, 50%, 75% and 100% complete. Operation 408 involves processing of a portion of a batch of wafers, and as described above, multiple groups of wafers, eg one, two, are sequentially cycled into and out of the reaction chamber for processing. Or may involve processing of each of the four wafers. In some embodiments, processing at operation 408 may involve one or more techniques performed on a portion of the batch of wafers, including deposition through ALD processes.

After removing the processed wafers from the reaction chamber, processing of the portion in operation 412 is temporarily stopped to perform center-batch processing of the reaction chamber. Center-batch processing stabilizes off-target materials that are accidentally deposited on the inner surfaces of the reaction chamber during processing of the portion in operation 408.

One of the advantages of BIAS is to increase the net throughput of the reaction chamber by increasing the maximum batch size that can be processed by the reaction chamber between required cleaning cycles. The relatively large batch size means that more reaction chamber time is available for processing wafers inside the reaction chamber than to frequently stop processing to complete comprehensive overhead operations such as chamber cleaning. Thus, the implementation of BIAS will contribute to increased throughput, as well as less defects observed in batches (eg, which may occur due to frequent processing interruptions to clean the reaction chamber).

4B shows some variations of specific types of processing that may be performed in operation 412. For example, off-target deposition materials attached to the sidewalls of the reaction chamber can be prevented, for example, by variant A, which prevents future flaking or decomposition of off-target deposition materials that may interfere with the processing of the batch of wafers. , To be fixed or sealed in place by application (eg, deposition) of a highly compressible film that bonds off-target deposition materials to the surfaces to which they are attached, for example sidewalls and/or other reaction chamber interior components. (sealed).

Such a film may be deposited at a set of predetermined intervals during batch processing, which may be empirically determined, eg, 25%, 50%, or 75% of the total batch limit. Alternatively, center-batch processing may be performed at regular time intervals, for example, every unit time elapsed from the start of processing. Also, considering that the off-target materials tend to accumulate on the inner surfaces of the reaction chamber in proportion to the number of wafers processed in the reaction chamber after the most recent cleaning cycle, the center-batch chamber coating will be applied. A possible interval may be selected when measuring the accumulation of off-target materials. This measurement may be performed in addition to, or instead of, applying a specified percentage of the total batch limit to the intermediate batch chamber coating.

Variant A, a conventional method of increasing the compressibility of the applied film or coating to combine off-target deposition materials by center-batch processing in a subset of operation 412, high RF power from 2 kW to 7 kW , At a high pressure of 2 T to 10 T, at a longer RF time (0.2 seconds to 10 seconds), including but not limited to applying the membrane via ALD or through other methods apparent to those skilled in the art. Further, in a particular embodiment, one or more of the mentioned techniques may be combined in any combinations as needed to increase the compressibility of the film.

A more comprehensive list of exemplary process conditions is provided in Figure 5A under the heading "Central-Batch-1/2". For example, mid-batch processing conditions suitable for applying a compressible film coating, for example at 50% of the total batch accumulation limit, may involve the flow of precursors at a volume flow rate of 500 to 3,000 sccm. For the formation and application of silicon oxide coatings comprising silicon-containing species selected from the group comprising bis-tert-butyalaminosilane (BTBAS), bisdiethylaminosilane (BDEAS) ((Et ₂ N) ₂ SiH ₂ ), or diisopropylaminosilane (DIPAS) Suitable precursors may flow into the reaction chamber at a volume flow rate of 500 to 3,000 sccm to create and apply UCT of, for example, silicon oxide (SiO ₂ ), such as silicate glass, to the interior surfaces of the reaction chamber. Other suitable exemplary precursors, or reactants used to generate silicon-containing UCT, may include a variety of other bisalkylaminosilanes, whose alkyl groups may contain 1 to 6 carbon groups. Further, each of the amine groups may be individually substituted with an alkyl group or substituted with two groups. Also, in certain embodiments, alkenyl modification and alkynyl modification may be employed as precursors or reactants used to generate silicon-containing UCT. In some cases or configurations, different alkyl groups may be employed on the molecules (eg, one or more amines may be substituted with methyl groups, and one or more other amines may be substituted with ethyl groups). In certain embodiments, one or more alkyl groups may provide steric hindrance of the silane core. Carrier gases, such as argon (Ar) gas, may also flow into the reaction chamber as needed to generate UCT. Further, in certain embodiments, the oxygen-containing species may be selected from the group comprising nitrous oxide (N ₂ O) gas and/or oxygen (O ₂ ) gas, and may flow into the reaction chamber.

Subsequent purge operation with nitrogen (N ₂ ) gas may be used to evacuate process reagents from the reaction chamber as required in the illustrated ranges, eg 5,000 to 50,000 sccm. In certain embodiments, the second purge operation may be performed at a flow rate range similar to the first purge. The total reaction chamber pressure may be maintained between 1 T and 10 T during deposition operations (eg, ALD) and purge operations.

Similarly, step timings for deposition and related purge operations are shown below the approximate flow rate ranges. Dosage timing indicates the precursor dosing time in seconds; PDP represents the purge time after dosing of an inert gas flow purge time, for example, to remove the deposition precursor from the wafer reaction zone in the reaction chamber; RF time refers to the period of time during which the RF plasma power is turned on with the reactant during the deposition operation; And the RF purge time refers to the duration of the purge that does not use the reactant or plasma power following the RF plasma-powered deposition. Additional reaction chamber process parameters available for adjustment during ALD operation and purge operation include chamber temperature and power settings. For example, the ampoule temperature refers to the reactant temperature when entering the chamber and may be in the range of 20 °C to 80 °C; The gas line temperature refers to the temperature at which the process gas is delivered through the gas line to the reaction chamber and may be in the range of 20 °C to 85 °C; The pedestal (“ped”) temperature refers to the temperature of the pedestal holding the wafer(s) intended for processing and may be in the range of 20°C to 550°C depending on the process application and deposited film requirements. There is; The chamber temperature refers to the internal temperature of the reaction chamber during ALD and related purge processes and may be set in the range of 20 °C to 85 °C; And the top plate temperature may be set in the range of 20 °C to 85 °C.

Acceptable power settings include those shown in FIG. 5A in specific ranges for various reaction chamber components such as showerhead (“SHD”) and pedestal (“ped”), all of which are frequency as shown. Range. Also, in certain embodiments, the post-processing processes are related to the ALD shown for the center-batch-half processing of FIG. 5A with approximate power levels, gas species flowing into the reaction chamber, and frequency and time intervals shown. It can also be applied in combination with fuzzy processes.

In some embodiments, instead of applying a compressible film to coat and seal off-target deposition materials as described above, off-target deposition materials accumulated on the inner surfaces of the reaction chamber, for example, are deformed It may also be exposed to plasma as shown in B. Plasma exposure may be performed at low pressure, for example, to allow the plasma to more easily diffuse into the off-target deposition materials to stabilize off-target deposition materials in place, and the targeted interval of the total batch accumulation limit, eg For example, at 25%, 50% or 75%, off-target deposition materials are prevented from falling onto the batch of wafers during processing. For example, reaction chamber process conditions suitable for variant B may be shown as “center-batch-3” in FIG. 5B with selectable post-treatment. Plasma may be generated in the same way as shown for deposition, as shown in the “Process” column of FIG. 5A, or may be delivered to a process chamber between a showerhead that may be powered and a pedestal that may be grounded. . Further, in certain embodiments, the plasma generated as described above may be diffused to improve the quality of materials deposited on a carrier ring that may be placed in a reaction chamber to hold wafers during processing. The carrier ring may be made of high-impedance ceramic oriented or configured to concentrate plasma power on a grounded pedestal.

In some embodiments, the plasma treatment presented in variant B is as shown in variant C, on a deposition material off the plasma-treated target on the inner surfaces of the reaction chamber, for example of a thin film of less than 200 mm 3 It may also lead to deposition. In addition, variant C may involve the initial application of an oxidized plasma treatment provided at low pressures, without flow of beads, eg reactive precursors or deposition reagents. In addition, the plasma provided to first stabilize the off-target deposition materials is argon gas (Ar) or argon gas and oxygen gas (O ₂ ) It can also be produced from mixtures. Thus, modification C may be achieved by selecting and applying specific process parameters as previously shown in the center-batch-1/2 column of FIG. 5A to deposit the thin film through ALD after plasma treatment of off-target deposition materials. have. This ALD process may involve short reactant flow times, for example, to deposit a thinner film of less than 200 kPa.

In the conventional processing sequence for variant C, chemicals such as reactive species used to perform deposition on the substrate 107 may be released from the showerhead 111. The inert gases used to generate the plasma used in variant C are typically difficult to ignite. Thus, power may be supplied to ignite inert gases on the faceplate of the showerhead 111. Also in these situations, the secondary purge (eg, for purging gases and/or other species from the reaction chamber) is turned off to cause the plasma to dissipate uniformly outwards throughout the processing chamber.

Next, after exposure of the off-target deposition materials to the plasma as described above, a thin film of, for example, less than 200 mm 2 may be deposited thereon to hold or solidify the off-target deposition materials in place. Such a coating may include silicon oxide or another suitable oxide. Further, in some embodiments, additional processing of post-thin film deposition, such as annealing or plasma processing, may be performed.

Variant D shown in FIG. 5B may be performed with Variant A, V or V, and the plasma ignited within the reaction chamber ultimately diffuses (eg, toward the side walls) to the outer regions of the reaction chamber. It involves grounding the reaction chamber as much as possible. Conventionally, a pedestal or support for holding a substrate, such as the substrate 107 shown in FIGS. 1 and 2, is grounded while the showerhead, which delivers the species towards the substrates for deposition, is powered on. Here, according to variant D and unlike conventional configurations, the pedestal may be powered while the showerhead is grounded. For example, the parameters shown in the column “Central-Batch-4” shown in FIG. 5B may cause the pedestal to generate grounding of the reaction chamber, which may be operated at a power level in the range of 500 W to 7 kW, for example. It may be applied selectively. This configuration provided by variant D may help target the area within the reaction chamber for plasma activation, application orientation, and impact, for example, towards the side walls of the reaction chamber with off-target materials deposited on the reaction chamber. have. This plasma may then be diffused towards an exterior region of the reaction chamber after use to process or process off-target deposited materials on chamber sidewalls and other chamber components.

After successful completion of the combinations for one or more variants A to D and/or variants A to D that collectively constitute the central-batch reaction chamber processing in operation 412, another portion of the batch of wafers is operated ( 416) is inserted into the reaction chamber at operation 414 for processing in the reaction chamber. Decision operation 420 determines whether a reaction chamber batch size limit has been reached during operations 408 and 416 for processing of the initial portion of the batch of wafers and any additional portions. For example, if the result of the determination is “no”, process workflow 400 loops back to operation 412 for additional center-batch processing and deposition to allow additional portions of the batch of wafers to be processed. . Thus, those skilled in the art recognize that employing BIAS and center-batch processing in operation 412 of process workflow 400 results in an expansion of the batch size that allows additional wafers to be processed between required reaction chamber cleaning cycles. something to do.

Eventually, and potentially after multiple runs of the central-batch reaction chamber processing operation 412, the inner surfaces of the reaction chamber have a threshold amount of off-target materials deposited on the inner surfaces of the reaction chamber (or The total batch accumulation limit is reached in operation 420 (possibly exceeding), resulting in a “yes” in operation 420. Accordingly, process workflow 400 will proceed toward end operation 422 where chamber cleaning is performed.

As previously mentioned, FIGS. 5A and 5B show tables providing various exemplary process parameter data values corresponding to various wafer processing and mid-batch reaction chamber processing operations. These values shown are intended to represent the parameters used in the various BIAS-related processes described above, but are not complete and not intended to be limiting. Process values and/or parameters may be adjusted as needed to achieve specific wafer processing throughput goals.

The various individual parameters are listed vertically in the “Parameters” column of both FIGS. 5A and 5B. And, as introduced above, the flow is provided in sccm relative to the volume flow rate of precursors, reactants and/or inert purge species into and out of the reaction chamber. The step timings shown in FIGS. 5A and 5B are, for example, dosing time, etc., as described above. Likewise, the remaining parameters included in the temperature, power level and selectable post-processing settings, for example, as described above, include one or more applications of UCT, or any one or more of variations A to D Corresponding to the central-batch processing through.

5A also shows approximate parameter setting ranges suitable for processing batches of wafers listed under the “Process” column. The processing of the batch may occur by depositing a film of the desired thickness thereon using ALD techniques as described above, and may involve the flow of precursor and reagent species in the amounts and/or combinations shown.

The remaining rows of UCT, center-batch-1/2, center-batch-3, and center-batch-4, respectively, represent the application of the undercoat during pre-treatment seasoning of the reaction chamber, and variations A through D. That is, the column header of “UCT” indicates the operating conditions, or settings, for the production and application of the pre-treatment seasoning undercoat on the interior surfaces of the reaction chamber. Likewise, in certain embodiments, the column header of “middle-placement-1/2” indicates settings for variant A; The column header of “Center-Batch-3” indicates the settings for variant B; And, the column header of “Center-batch-4” indicates the settings for variant D. Variant C may be performed by selectively combining the set ranges provided in the column headers of center-batch-1/2 and center-batch-3.

6 shows another table of example process parameters for a remote cleaning recipe that may be used to perform remote cleaning of the reaction chamber at the end of process workflow 400 at operation 422, for example. The abbreviations HP and LP refer to “High-Pressure” and “Low-Pressure”, respectively (and also reflected in the respective pressure ranges shown in FIG. 6). Various recipes of the species used to generate the plasmas employed for cleaning may be used. After successful removal of off-target deposition materials from the interior surfaces of the reaction chamber by a completed cleaning cycle, as shown by process workflows 300, or 400, BIAS processes add additional wafers as desired. It may be restarted to process the batches.

Device

7 shows a schematic illustration of one embodiment of an ALD process station 700 with a process chamber 702. Process station 700 may be used to perform certain disclosed embodiments. For example, process station 700 may typically be used to deposit films by ALD on a substrate, but process station 700 may be used to etch or clean carbon-containing material, respectively, in a patterning scheme, for example. For example, it may be used in certain configurations to perform ALE (Atomic Layer Etching) or ALC (Atomic Layer Cleaning). In some embodiments, process stations 700 may be used for ALE, ALC, and ALD, or in some embodiments, some process stations of a multi-station tool do not allow substrates to break the vacuum and ALC station It may also include a station for ALE or ALC and a station for ALD so that it may be transferred between and the ALD station.

Process chamber 702 may be used to maintain a low pressure atmosphere. Multiple process stations may be included in a common low pressure process tool environment. For example, FIG. 8 shows an embodiment of a multi-station processing tool 800. In some embodiments, one or more hardware parameters of process station 700, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers 750.

Process station 700 is in fluid communication with reactant delivery system 701a to deliver process gases to distribution showerhead 706. The reactant delivery system 701a includes a mixing vessel 704 for blending and/or conditioning process gases such as oxygen-containing gas or inert gas for delivery to the showerhead 706 do. One or more mixing vessel inlet valves 720 may control the introduction of process gases to mixing vessel 704.

By way of example, the embodiment of FIG. 7 includes a vaporization point 703 for vaporizing the liquid reactant to be supplied to the mixing vessel 704. In some embodiments, the deposition chemistry may be provided as a vaporized liquid reactant. Deposition chemicals may be used following performing ALE or ALC in process chamber 702 to form a patterned carbon-containing material such that a conformal film may be deposited by ALD over the patterned carbon-containing material. It might be. In some embodiments, vaporization point 703 may be a heated vaporizer. The saturated reactant vapor produced from these vaporizers may condense in downstream delivery pipes. Exposure of gases that are incompatible with condensed reactants may produce small particles. These small particles may clog the pipe, interfere with valve operation, contaminate substrates, and the like. Some approaches to solving these problems involve purging and/or venting the delivery pipe to remove residual reactants. However, purging the delivery pipe may increase the process station cycle time, degrading process station throughput. Thus, in some embodiments, the downstream delivery pipe of vaporization point 703 may be heat traced. In some examples, mixing vessel 704 may also be heat traced. In one non-limiting example, the piping downstream of vaporization point 703 has an increasing temperature profile that extends from mixing vessel 704 to approximately 100 °C to approximately 150 °C.

In some embodiments, a liquid precursor or liquid reactant may be vaporized in a liquid injector (not shown in FIG. 7 ). For example, the liquid injector may inject pulses of the liquid reactant into the upstream carrier gas stream of the mixing vessel 704. In one embodiment, the liquid injector may vaporize the reactants by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector may atomize the liquid with dispersed micro-droplets that are subsequently vaporized in a heated delivery pipe. Smaller droplets may vaporize faster than larger droplets, reducing the delay between liquid injection and complete vaporization. Faster vaporization may reduce the length of the downstream pipe from vaporization point 703. In one scenario, the liquid injector may be mounted directly to the mixing vessel 704. In another scenario, the liquid injector may be mounted directly to the showerhead 706.

In some embodiments, an upstream Liquid Flow Controller (LFC) of the vaporization point 703 may be provided to control the mass flow of liquid for vaporization and delivery to the process chamber 702. For example, the LFC may include a thermal Mass Flow Meter (FMM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to feedback control signals provided by a Proportional-Integral-Derivative (PID) controller in electrical communication with the MFM. However, it may take more than 1 second to stabilize the liquid flow using feedback control. This may extend the time to doze the liquid reactant. Thus, in some embodiments, the LFC may be switched dynamically between the feedback control mode and the direct control mode. In some embodiments, this may be done by disabling the sense tubes of the LFC and PID controllers.

The showerhead 706 distributes process gases towards the substrate 712. In the embodiment shown in FIG. 7, the substrate 712 is shown positioned under the showerhead 706 and mounted on the chuck or pedestal 708. The showerhead 706 is provided by the showerhead 706 towards the substrate 712, or from 0.75 mil (0.35 in.) to 700 mil (0.7 in.) to achieve the desired level of directionality of the dispersed ions. It can also be located on the street. In some embodiments, a lower or less gap between showerhead 706 and pedestal 712 may be employed to maintain the directionality of ions dispersed from showerhead 706. However, a higher or larger gap in low pressure conditions (eg, 10 mT, or 0.01 Torr or less) may be necessary to achieve stable dispersion of the ionized plasma from the showerhead 706. In some embodiments, the chamber may include a plurality of chucks or pedestals. Showerhead 706 may have any suitable shape, and may have any suitable number and arrangement of ports to distribute process gases to substrate 712.

In some embodiments, pedestal 708 may be raised or lowered to expose substrate 712 at a volume between substrate 712 and showerhead 706. In some embodiments, the pedestal 708 may be temperature controlled via a heater 710. The pedestal 708 may be set to any suitable temperature, such as from about 25 °C to about 650 °C or from about 35 °C to about 100 °C during operations to perform various disclosed embodiments. It will be appreciated that in some embodiments, the pedestal height may be adjusted programmatically by a suitable computer controller 750.

In another scenario, adjusting the height of the pedestal 708 may cause the plasma density to vary during plasma activation performed in certain disclosed embodiments. For example, the plasma may be ignited when an inert gas flows through the showerhead 706 to the substrate 712 to remove the modified core material after the core material is exposed to the oxygen-containing gas. At the end of the process phase, pedestal 708 may be lowered during another substrate transfer step to allow removal of substrate 712 from pedestal 708.

In some embodiments, the position of the showerhead 706 may be adjusted relative to the pedestal 708 to vary the volume between the substrate 712 and the showerhead 706. It will also be appreciated that the vertical position of pedestal 708 and/or showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 708 may include an axis of rotation to rotate the orientation of substrate 712. It will be appreciated that in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers 750. Computer controller 750 may include any of the features described below with respect to controller 750 of FIG. 7.

In some embodiments where plasma may be used as discussed above, showerhead 706 and pedestal 708 are in electrical communication with RF power supply 714 and matching network 716 to power the plasma. do. In some embodiments, plasma energy may be controlled by controlling one or more of process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, RF power supply 714 and matching network 716 may be operated with any suitable power to form a plasma having a targeted composition of radical species. Likewise, RF power supply 714 may provide RF power at any suitable frequency. In some embodiments, RF power supply 714 may be configured to control a high frequency RF power source and a low frequency RF power source independently of each other. Exemplary low frequency RF frequencies may include, but are not limited to, frequencies between 0 kHz and 500 kHz. Exemplary high frequency RF frequencies may include, but are not limited to, frequencies from 1.8 MHz to 2.45 GHz, greater than about 13.56 MHz, greater than 27 MHz, greater than 40 MHz, or greater than 60 MHz. It will be appreciated that any suitable parameters may be adjusted discretely or continuously to provide plasma energy for surface reactions.

In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (eg, VI probes). In another scenario, plasma density and/or process gas concentration may be measured by one or more Optical Emission Spectroscopy (OES) sensors. In some embodiments, one or more plasma parameters may be adjusted programmatically based on measurements from these in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop to provide programmatic control of plasma power. In some embodiments, the OES sensor may be used to set an endpoint to stop etching after a certain amount of time using certain disclosed embodiments. It will be appreciated that in some embodiments, other monitors may be used to monitor plasma and other process characteristics. Some monitors may include, but are not limited to, IR (infrared) monitors, acoustic monitors, and pressure transducers.

In some embodiments, instructions for the controller 750 may be provided through Input/Output Control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process step may be included in the corresponding recipe phase of the process recipe. In some cases, the process recipe step may be arranged sequentially, such that all instructions for the process step are executed concurrently with the process step. In some embodiments, instructions for setting one or more reactor parameters may be included in the recipe step. For example, the first recipe step may include instructions for setting the flow rate of the inert gas and/or reactant gas (eg, oxygen-containing gas), and the flow rate of the carrier gas (such as argon). For instructions, and time delay instructions for the first recipe step. The second, subsequent recipe phase includes instructions for adjusting or stopping the flow rate of the inert gas and/or reactant gas, instructions for adjusting the flow rate of the carrier gas or purge gas, and time for the second recipe phase It may also include delay instructions. The third recipe phase includes instructions for adjusting the flow rate of the second gas, such as argon, instructions for adjusting the flow rate of the carrier gas or purge gas, about 250 W to about 750 W for a 4-station processing tool. May include instructions for igniting the plasma at low plasma power, and time delay instructions for the third recipe phase. Fourth, subsequent recipe phases include instructions for adjusting or stopping the flow rate of inert gas and/or reactant gas, instructions for adjusting the flow rate of carrier gas or purge gas, and time for the fourth recipe phase It may also include delay instructions. These recipes may be used to etch a carbon-containing material, such as core materials on the substrate, to yield vertical sidewalls that meet the surface of the underlying layer to be etched at about 90°±5°. Additional recipes may also be followed, and used to deposit a conformal film over the core material patterned by ALD. For example, to deposit a silicon oxide conformal film over a patterned core material, one additional recipe phase may include instructions to set the flow rate of the silicon-containing precursor, another additional recipe phase is It may also include instructions for setting the flow rate of the oxygen-containing reactant and time delay instructions for the additional recipe phase. It will be appreciated that these recipe phases may be further subdivided and/or repeated in any suitable manner within the scope of the present disclosure.

Further, in some embodiments, pressure control for the process station 700 may be provided by a butterfly valve 718. As shown in the embodiment of FIG. 7, butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown in FIG. 7). However, in some embodiments, the pressure control of process station 700 may also be adjusted by varying the flow rate of one or more gases introduced to process station 700.

As described above, one or more process stations may be included in a multi-station processing tool. 8 shows an inbound load lock 802 and an outbound load lock 804, one or both of which may include a remote plasma source (not shown in FIG. 8). Together, they show a schematic drawing of one embodiment of a multi-station processing tool 800. At atmospheric pressure, the robot 806 is configured to move wafers from the cassette loaded through the pod 808 through the atmospheric port 810 into the inbound load lock 802. A wafer (not shown in FIG. 8) is placed by the robot 806 on the pedestal 812 in the inbound load lock 802, the standby port 810 is closed, and the inbound load lock 802 is pumped down. (Pump down). If inbound load lock 802 includes a remote plasma source, the wafer may be exposed to remote plasma processing within inbound load lock 802 before being introduced into processing chamber 814. In addition, the wafer may also be heated in the inbound load lock 802, for example to remove moisture and adsorbed gases. Next, the chamber transfer port 816 to the processing chamber 814 is opened, and another robot (not shown) places the wafer into the reactor on the pedestal of the illustrated first station of the reactor for processing. It will be appreciated that although the embodiment shown in FIG. 8 includes load locks, in some embodiments, direct entry of the wafer into the process station may be provided.

The illustrated processing chamber 814 includes four process stations numbered 1-4 in the embodiment shown in FIG. 8. Each station has a heated pedestal (shown as 818 for Station 1), and gas line inlets. It will be appreciated that in some embodiments, each of the process stations may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between ALC, ALD and plasma-enhanced ALD process modes. In some embodiments, exposure to the deposition precursor and exposure to the second reactant and plasma are performed at the same station. Additionally or alternatively, in some embodiments, processing chamber 814 may include one or more matched pairs of ALD and plasma-enhanced ALD process stations. It will be appreciated that although the illustrated processing chamber 814 includes four stations, the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments the processing chamber may have three or fewer stations.

8 shows an embodiment of a wafer handling system 890 for transferring wafers within a processing chamber 814. In some embodiments, wafer handling system 890 may transfer wafers between various process stations and/or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. 8 also shows an embodiment of a system controller 850 employed to control process conditions and hardware conditions of the process tool 800. System controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a CPU or computer, analog input/output connections and/or digital input/output connections, stepper motor controller boards, and the like.

In some embodiments, system controller 850 controls all activities of process tool 800. System controller 850 executes system control software 858 stored in mass storage device 854, loaded into memory device 856, and executed on processor 852. Alternatively, control logic may be hard coded within controller 850. Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) (eg, field-programmable gate arrays, or FPGAs) may be used for these purposes. In the following discussion, whenever “software” or “code” is used, functionally similar hard coded logic may be used instead. System controller software 858 includes timing, mixture of gases, gas flow rates, chamber pressure and/or station pressure, chamber temperature and/or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, It may include instructions for controlling the chuck and/or susceptor location, and other parameters of a particular process performed by process tool 800. System control software 858 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components used to perform various process tool processes. System control software 858 may be coded in any suitable computer readable programming language.

In some embodiments, system control software 858 may include IOC sequencing instructions for controlling various parameters described above. Other computer software and/or programs stored on mass storage device 854 and/or memory device 856 associated with system controller 850 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 818 and control the interval between the substrate and other components of the process tool 800.

The process gas control program is for controlling gas composition (eg, silicon-containing gases, oxygen-containing gases, and purge gases as described herein) and flow rates, and optionally a process station It may also include a code to flow gas into one or more process stations prior to deposition to stabilize the pressure within. The pressure control program may include code for controlling the pressure in the process station, for example, by regulating the throttle valve of the process station's exhaust system, gas flow into the process station, and the like.

The heater control program may include code for controlling the current to the heating units used to heat the substrate. Alternatively, the heater control program may control the transfer of heat transfer gas (such as helium) to the substrate.

The plasma control program may include code for setting RF power levels applied to process electrodes at one or more process stations in accordance with embodiments herein.

The pressure control program may include code for maintaining the pressure in the reaction chamber according to embodiments herein.

In some embodiments, there may be a user interface associated with system controller 850. The user interface may include a display screen, graphical software displays of apparatus and/or process states, and user input devices such as pointing devices, keyboards, touch screens, microphones, and the like.

In some embodiments, parameters adjusted by system controller 850 may be related to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), and the like. These parameters may be provided to users in the form of a recipe that may be input using a user interface.

Signals for monitoring the process may be provided by analog input connections and/or digital input connections of the system controller 850 from various process tool sensors. Signals for controlling the process may be output on the analog output connection and digital output connection of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, and the like. Properly programmed feedback and control algorithms may be used as data from these sensors to maintain process conditions.

System controller 850 may provide program instructions for implementing the deposition processes described above. Program instructions may control various process parameters such as DC power level, RF bias power level, pressure, temperature, and the like. Instructions may control parameters to operate in-situ deposition of film stacks in accordance with various embodiments described herein.

System controller 850 will typically perform methods according to embodiments in which the apparatus is disclosed, including one or more memory devices and one or more processors configured to execute instructions. A machine-readable medium including instructions for controlling process operations in accordance with disclosed embodiments may be coupled to system controller 850.

In some implementations, system controller 850 is part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment, including a processing tool or tools, a chamber or chambers, a platform or platforms for processing, and/or specific processing components (wafer pedestal, gas flow system, etc.). . These systems may be integrated into electronics to control their operation before, during, and after processing a semiconductor wafer or substrate. Electronic devices may be referred to as “controllers” that may control various components or sub-portions of a system or systems. System controller 850, depending on processing conditions and/or type of system, delivers processing gases, temperature settings (eg, heating and/or cooling), pressure settings, vacuum settings, Power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, tools and other transfer tools and/or It may be programmed to control any of the processes disclosed herein, including wafer transfers into and out of loadlocks connected or interfaced with a particular system.

Generally speaking, the system controller 850 receives various instructions, issues instructions, controls the operation, enables cleaning operations, enables endpoint measurements, etc., various integrated circuits, logic, memory , And/or electronic devices with software. Integrated circuits are chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as ASICs, and/or one or more microprocessors that execute program instructions (eg, software), Or it may include microcontrollers. The program instructions are instructions delivered to the system controller 850 or to the system in the form of various individual settings (or program files), which define operating parameters for executing a particular process on the semiconductor wafer or on the semiconductor wafer. It might be. In some embodiments, operating parameters are processed to achieve one or more processing steps during manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. It may be part of the recipe prescribed by the engineers.

System controller 850 may, in some implementations, be coupled to, or be part of, a computer that may be integrated into, coupled to, or otherwise networked to, or a combination of systems. For example, system controller 850 may be in the “cloud” or all or part of a fab host computer system that may enable remote access of wafer processing. The computer monitors the current progress of manufacturing operations, examines the history of past manufacturing operations, examines trends or performance metrics from multiple manufacturing operations, changes parameters of the current processing, and processes steps following the current processing. You can also enable remote access to the system to set up or start a new process. In some examples, a remote computer (eg, a server) can provide process recipes to the system through a local network or a network that may include the Internet. The remote computer may include a user interface that enables input or programming of parameters and/or settings to be subsequently transferred from the remote computer to the system. In some examples, system controller 850 receives instructions in the form of data, specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of tool to be controlled or interfaced by the system controller 850 and the type of process to be performed. Thus, as described above, system controller 850 may be distributed by including one or more separate controllers that are networked and operated together for a common purpose, such as the processes and controls described herein. An example of a distributed controller for these purposes can be one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (eg at the platform level or as part of a remote computer), combined to control processes on the chamber. have.

Non-limitingly, exemplary systems include plasma etch chambers or modules, deposition chambers or modules, spin-rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) Used in the manufacture and/or fabrication of chambers or modules, CVD (Chemical Vapor Deposition) chambers or modules, ALD chambers or modules, ALC chambers or modules, ion implantation chambers or modules, track chambers or modules, and semiconductor wafers Or any other semiconductor processing systems that may or may not be associated.

As described above, depending on the process step or steps to be performed by the tool, the system controller 850 is from and to tool positions and/or load ports in the semiconductor manufacturing plant. Other tool circuits or modules, other tool components, cluster tools, other tool interfaces, neighboring tools, neighboring tools, tools located throughout the factory, main computers, used in material transport to move containers of wafers, It may also communicate with one or more of the other controllers or tools.

A suitable device for performing the methods disclosed herein was filed on April 11, 2011, and entitled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION” US Patent Application No. 13/084,399 (currently US Patent No. 8,728,956) ; And United States Patent Application No. 13/084,305, filed April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS”, each of which is incorporated herein in its entirety.

The apparatus/process described herein may be used in conjunction with lithographic patterning tools or processes, for example for the manufacture or fabrication of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not necessarily, these tools/processes will be used or performed together in a common manufacturing facility. The lithographic patterning of a film typically includes some or all of the following actions, each of which is enabled with a number of possible tools: (1) spin-on tool or spray-on. ) Application of a photoresist onto a workpiece, ie a substrate, using a tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing photoresist to visible or UV light or x-ray light with a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and pattern it using a tool such as a wet bench; (5) transferring the resist pattern into the underlying film or workpiece by using a dry etching tool or a plasma-assisted etching tool; And (6) removing the resist using a tool such as an RF plasma resist stripper or a microwave plasma resist stripper.

conclusion

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and apparatus of the present embodiments. Accordingly, the embodiments are to be regarded as illustrative and not restrictive, and the embodiments are not limited to the details given herein.

Claims (34)

A method for increasing the reaction chamber batch size,
(a) processing a portion of a batch of wafers within a reaction chamber, the processing causing deposition of at least some off-target material on the inner surfaces of the reaction chamber, Processing a portion of the batch;
(b) performing mid-batch reaction chamber processing to stabilize the off-target deposition material accumulated on the inner surfaces of the reaction chamber; And
(c) processing another portion of the batch of wafers within the reaction chamber. According to claim 1,
And repeating steps (b) and (c) until processing of the batch of wafers is complete. According to claim 1,
The reaction chamber batch size is the number of wafers that can be processed in the reaction chamber between reaction chamber cleaning cycles, the method of increasing the reaction chamber batch size. According to claim 1,
A method of increasing a reaction chamber batch size, further comprising seasoning the inner surfaces of the reaction chamber before batch processing inside the reaction chamber. The method of claim 4,
The step of seasoning the inner surfaces of the reaction chamber involves applying a coating of the same material used for deposition on the batch of wafers during step (a) or step (c) to determine the reaction chamber batch size. How to increase. According to claim 1,
The step (a) or step (c) involves depositing material on a wafer of the batch of wafers, the method of increasing the reaction chamber batch size. The method of claim 4,
The step of seasoning comprises applying a coating to the inner surfaces of the reaction chamber by atomic layer deposition (ALD) while no wafers are present in the reaction chamber. According to claim 1,
(d) cleaning the inner surfaces of the reaction chamber following completion of step (c), further increasing the reaction chamber batch size. According to claim 2,
(d) cleaning the inner surfaces of the reaction chamber after processing of the batch of wafers is completed. According to claim 1,
The step (b) is performed at specified intervals of the total batch accumulation limit of the batch of wafers, to increase the reaction chamber batch size. The method of claim 10,
A method for increasing the reaction chamber batch size, wherein the total batch accumulation limit is the thickness of material accumulated on the inner surfaces of the reaction chamber where processing is impaired such that cleaning of the reaction chamber is required before further processing. The method of claim 10,
A method of increasing the reaction chamber batch size, wherein the intervals specified above are empirically determined. The method of claim 10,
The specified intervals occur prior to the accumulation of a detrimental level of material on the interior surfaces of the chamber that causes flaking of the material and generation of wafer defects and/or particles. According to claim 1,
The step (b) involves depositing a film that binds to the materials accumulated on the inner surfaces of the reaction chamber, the method of increasing the reaction chamber batch size. The method of claim 14,
The method of increasing the reaction chamber batch size, wherein the compressibility of the film is improved by adjusting any one or more selected from the group consisting of radio frequency (RF) power levels, reaction chamber pressure, or RF processing time. According to claim 1,
The step (b) involves exposing the materials accumulated on the inner surfaces of the reaction chamber to plasma after the materials have accumulated to a specified thickness, thereby increasing the reaction chamber batch size. The method of claim 16,
Plasma exposure is performed at a pressure in the range of 1 Torr to 10 Torr to facilitate plasma diffusion into the film deposited on the inner surfaces of the reaction chamber, the method of increasing the reaction chamber batch size. The method of claim 16,
The plasma is ignited on the faceplate of the showerhead in the reaction chamber, to increase the reaction chamber batch size. The method of claim 16,
And deactivating the purge to cause the plasma to dissipate uniformly throughout the reaction chamber. The method of claim 16,
Wherein the plasma is derived from hydrogen, helium, argon, or any one source selected from the group consisting of nitrogen-containing sources. The method of claim 16,
The method of increasing the reaction chamber batch size, wherein exposure to the plasma deposits a film of approximately 200 mm 3 on the materials accumulated on the inner surfaces of the reaction chamber. The method of claim 21,
The deposited film stabilizes the materials on the inner surfaces of the reaction chamber, increasing the reaction chamber batch size. The method of claim 21,
The exposure to the plasma densify the deposited film to stabilize the materials on the inner surfaces of the reaction chamber, thereby increasing the reaction chamber batch size. The method of claim 15,
The compressibility of the film is increased by a method selected from the group consisting of applying RF power in the range of 2 kw to 7 kw, applying a high pressure in the range of 2 torr to 10 torr, or using an RF plasma time of 0.2 s to 10 s. To increase the reaction chamber batch size. The method of claim 15,
(d) further comprising grounding the reaction chamber. The method of claim 25,
Wherein the grounded reaction chamber facilitates plasma diffusion to the outside of the reaction chamber. The method of claim 26,
A method of increasing a reaction chamber batch size, wherein a showerhead configured to deliver deposition gas to the batch of wafers is powered. The method of claim 26,
A method of increasing the reaction chamber batch size, wherein a pedestal configured to support the batch of wafers is powered. The method of claim 9,
A method of increasing the reaction chamber batch size, wherein the plasma used to perform step (d) is supplied by a remote plasma cleaning unit. The method of claim 29,
The remote plasma cleaning unit is mounted on the reaction chamber (on-board), a method of increasing the reaction chamber batch size. The method of claim 16,
Wherein the plasma has a frequency of 400 kHz, increasing the reaction chamber batch size. A plasma processing apparatus for processing a substrate,
Reaction chamber; And
A remote plasma chamber,
The reaction chamber,
Interior chamber surfaces,
A substrate support for supporting a substrate in the reaction chamber, and
An exhaust port for removing material from the reaction chamber,
The remote plasma chamber,
A plasma generator for generating plasma in the remote plasma chamber,
An inlet for delivering gas to the remote plasma chamber,
An outlet for providing plasma generated in the remote plasma chamber to the reaction chamber, and
As a controller,
(a) processing a portion of a batch of wafers within the reaction chamber, the processing causing the deposition of at least some off-target material on inner surfaces of the reaction chamber;
(b) performing center-batch reaction chamber processing to stabilize the off-target deposition material accumulated on the inner surfaces of the reaction chamber; And
(c) the controller, configured to execute instructions for the operation of processing another portion of the batch of wafers within the reaction chamber. The method of claim 32,
Wherein the plasma processing device is remote from the reaction chamber. The method of claim 32,
The controller,
(d) further configured to execute instructions for the operation of cleaning the inner surfaces of the reaction chamber following completion of operation (c).

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