KR20200066565A - Fabrication method of metal-free soi wafer - Google Patents

Abstract

Various embodiments of the present application relate to a method for forming a semiconductor-on-insulator (SOI) device having an impurity contention layer to absorb potential contaminant metal particles during an annealing process, and an SOI structure thereof. In some embodiments, an impurity contention layer is formed on a dummy substrate. An insulating layer is formed on a support substrate. A front surface of the dummy wafer is bonded to the insulating layer. An annealing process is performed, and the impurity contention layer absorbs metal from an upper part of the dummy substrate. Next, a main part of the dummy substrate including the impurity contention layer is removed to leave a device layer of the dummy substrate on the insulating layer.

Description

Manufacturing method of non-metallic SOI wafer {FABRICATION METHOD OF METAL-FREE SOI WAFER}

Reference of related applications

This application claims the benefit of U.S. Provisional Application No. 62/773,304, filed on November 30, 2018, the content of which is incorporated herein by reference in its entirety.

Silicon on insulator (SOI) technology uses a layered silicon-insulator-substrate instead of a conventional silicon substrate in semiconductor manufacturing. SOI-based devices are fabricated on electrical insulators, and advantages include lower parasitic devices, reduced short-channel effects, reduced temperature dependence, lower leakage current, and the like in microelectronic devices.

Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that according to standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
1 is a cross-sectional view showing an SOI structure having an impurity competing layer in accordance with some embodiments.
2 is a cross-sectional view showing an SOI structure having an impurity contention layer according to some alternative embodiments.
3 is a cross-sectional view showing an SOI structure having an impurity contention layer according to some alternative embodiments.
4 to 10, 11 and 12, 13 to 18, and 19 to 24 are each a series of cross-sectional views of an SOI structure having an impurity contention layer in various manufacturing steps according to some embodiments.
25 is a flow diagram of a method for manufacturing an SOI structure in accordance with some embodiments.

This disclosure provides a number of different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and devices are described below to simplify the present disclosure. This, of course, is merely an example, and is not intended to be limiting. For example, in the description that follows, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed by direct contact, and additional features may be applied to the first and first features. It may also be formed between two features, which may also include embodiments in which the first and second features may not be in direct contact. Moreover, the present disclosure may repeat figure numbers and/or letters in various examples. This repetition is for simplicity and clarity, and does not itself dictate the relationship between various embodiments and/or described configurations.

In addition, spatial relative terms such as “bottom”, “bottom”, “bottom”, “top”, “top”, etc., may be one element relative to another element(s) or feature(s) as shown in the figure, or It may be used herein for easy description to describe the relationship of features. The spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in a different orientation), and the spatial relative descriptors used herein may likewise be interpreted accordingly.

Moreover, “first”, “second”, “third”, etc. may be used herein for easy description to distinguish between different elements of a drawing or series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding elements. Accordingly, the “first dielectric layer” described in connection with the first drawing may not necessarily correspond to the “first dielectric layer” described in connection with other drawings.

As an example, preparation of the SOI structure may include the following steps. First, a main wafer (also referred to as a carrier wafer in the present disclosure) is provided. The carrier wafer may also include a buried oxide layer disposed over the support substrate. Also, a dummy wafer is prepared. The dummy wafer includes a silicon layer disposed on the dummy substrate. Next, the main wafer and the dummy wafer are joined together. The bonded wafer is then subjected to a splitting process to remove portions of the dummy substrate and silicon layer, leaving the upper silicon layer formed on the buried oxide layer. The splitting process can be performed in a number of ways, such as polishing or smart-cut. High residual metal in the top silicon layer is a common problem with SOI structures. For example, in an SOI structure manufactured by a smart cut process, due to hydrogen injection, the implanted region will increase potential metal contamination. The wafer-bonding process is another cause of increasing metal contamination into the bonding interface between the buried oxide layer and the top silicon layer, and then causing high residual metal in the top silicon layer. Residual metal contaminants may include iron (Fe), molybdenum (Mo), titanium (Ti), copper (Cu), and nickel (Ni), segregating on the wafer surface during the cooling process and causing surface defects. .

In view of the above, some aspects of the present disclosure relate to SOI structures and methods for manufacturing the same to alleviate metal contamination during the SOI structure manufacturing process. The SOI manufacturing process includes bonding the dummy wafer to the carrier wafer followed by a splitting process to form an upper silicon layer on the carrier wafer. An additional impurity contention layer is formed on the dummy wafer as a metal gettering layer to reduce metal contamination of the SOI structure. As a result, metal contamination has been eliminated or at least reduced in the SOI structure and the semiconductor device formed therefrom. The impurity contention layer may be removed after the final thinning process. In some embodiments, the impurity contention layer may also act as an etch stop layer for a subsequent removal process of the dummy wafer. As an example, the impurity contention layer may include an epitaxial p-type silicon layer having a gettering source such as germanium, boron, and carbon.

In some embodiments, the impurity contention layer may be implanted into the dummy wafer prior to the bonding process. The impurity contention layer may be formed on or within the dummy substrate of the dummy wafer. The substrate of the dummy wafer may include a high concentration doped silicon substrate, such as p-type doped silicon having a doping concentration ^greater than 10 ¹⁷ cm ^-3 . The impurity contention layer may include an injection of carbon, boron, phosphorus, helium, or a combination thereof. Next, the dummy wafer is bonded to the carrier wafer followed by a bonding annealing process. During the bonding annealing process, the impurity contention layer absorbs metal from the top silicon layer. Next, the carrier wafer and the dummy wafer are separated. In the wafer separation step, both the impurity contention layer and the dummy substrate of the dummy wafer are removed.

In some alternative embodiments, instead of forming an impurity contention layer in the substrate, it can also be formed on the back side of the dummy wafer opposite the top silicon layer. The impurity contention layer may be formed through a backside sandblasting process, a gettering dry polishing process for a dummy substrate, a polysilicon film, a silicon oxynitride film, a silicon germanium film, or a deposition of a silicon nitride film. Next, the dummy wafer is bonded to the carrier wafer followed by an annealing process. During the bonding annealing process, the impurity contention layer absorbs metal from the top silicon layer. Next, the wafers are separated. In the wafer separation step, both the impurity contention layer and the substrate of the dummy wafer are removed. Also, instead of using the smart cut process, the carrier wafer and the dummy wafer can be separated by a bismart process. The impurity contention layer may be formed in or on the backside of the dummy wafer, and then removed from the carrier wafer together with the dummy substrate, leaving the upper silicon layer with reduced metal contamination on the carrier wafer.

In some alternative embodiments, instead of forming an additional contention layer on the dummy substrate, the substrate of the dummy wafer can function as a highly doped and thick impurity contention body. A low concentration doped epitaxial layer (eg, P-doped epi layer) is deposited on a high concentration doped dummy substrate (eg, P++ 10 ¹⁷ cm ^-3 doping concentration). During the bonding annealing process, impurity contention (P++ substrate) increases potential metal contamination. Next, portions of the P++ dummy substrate and the P-epi layer may be removed.

1 shows a cross-sectional view 100 illustrating an SOI structure having an impurity contention layer 108 in accordance with some embodiments. The SOI structure may include a carrier wafer 142 having an insulating layer 104 disposed over the support substrate 102. In some embodiments, support substrate 102 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, glass, silicon dioxide, aluminum oxide, or any combination thereof. The support substrate 102 may have a circular top layout and/or a diameter of about 200, 300, or 450 millimeters. The support substrate 102 may also have some other shape and/or some other dimension. The support substrate 102 may have a high resistance and/or low oxygen concentration. The high resistance and low oxygen concentration reduce the substrate and/or RF loss respectively. High resistance may be, for example, greater than about 1, 3, 4, or 9 mm 2 /cm, and/or, for example, about 1 to 4 mm 2 /cm, about 4 to 9 mm 2 /cm, or about 1 It may also be 9 ㏀/cm. The low oxygen concentration may be, for example, about 1, 2, or 5 ppma, and/or may be, for example, about 0.1 to 2.5 ppma, about 2.5 to 5.0 ppma, or about 0.1 to 5.0 ppma. In some embodiments, support substrate 102 is doped with a p-type or n-type dopant. In some embodiments, the thickness of the support substrate 102 is about 720-780 micrometers, about 720-750 micrometers, or about 750-780 micrometers. The insulating layer 104 may be, for example, silicon dioxide or sapphire. The insulating layer 104 may cover the outer surface of the support substrate 102. In some embodiments, the thickness of the insulating layer 104 is about 0.2 to 2.0 micrometers, about 0.2 to 1.1 micrometers, or about 1.1 to 2.0 micrometers.

The dummy wafer 144 is bonded to the carrier wafer 142. The dummy wafer 144 includes a dummy substrate 106. In some embodiments, dummy substrate 106 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination thereof. The dummy substrate 106 may have a circular top layout and/or a diameter of about 200, 300, or 450 millimeters. The dummy substrate 106 may also have some other shape and/or some other dimension. In some embodiments, dummy substrate 106 is a bulk semiconductor substrate and/or a semiconductor wafer. In some embodiments, the thickness of the dummy substrate 106 is about 720-780 micrometers, about 720-750 micrometers, or about 750-780 micrometers. In some embodiments, a hydrogen floating region 110 is disposed at a location within the dummy substrate 106 from the front surface 146 of the dummy wafer 144.

In some embodiments, an impurity contention layer 108 is disposed within the dummy substrate 106. The impurity contention layer 108 may be formed by an implantation process at an internal location of the dummy substrate 106 by a carbon implantation process, a boron implantation process, a phosphorus implantation process, a helium implantation process, or a combination thereof. The impurity contention layer 108 is configured to absorb contaminated metal particles 112 when a thermal process is performed. During the thermal process, the impurity contention layer 108 is directed toward the impurity contention layer 108 from the interface region between the carrier wafer 142 and the dummy wafer 144, as shown by the arrows connected to the particles 112. Potentially contaminating particles 112 are absorbed. Thus, potential contaminant particles 112 are removed from the upper portion of the dummy substrate 106 proximate the insulating layer 104. The thermal process is integrated with the bonding annealing process and may enhance bonding of the dummy wafer 144 and the carrier wafer 142. In some embodiments, the annealing process is performed at a temperature of about 300 to 1150°C, about 300 to 725°C, or about 735 to 1150°C. In some embodiments, the annealing process is performed for about 2 to 5 hours, about 2 to 3.5 hours, or about 3.5 to 5 hours. In some embodiments, the annealing process is performed at a pressure of about 1 atm, about 0.5 to 1.0 atm, about 1.0 to 1.5, or about 0.5 to 1.5 atm. In some embodiments, an annealing process is performed while nitrogen gas (eg, N ₂ ) and/or some other gas flows over the structure of FIG. 10. The flow rate of the gas may be, for example, about 1 to 20 standard liters per minute (slm), about 1 to 10 slm, or about 10 to 20 slm.

The SOI structure shown in FIG. 1 is an intermediate structure for preparing an SOI substrate. After the thermal process, the dummy wafer 144 and the carrier wafer 142 are divided along the hydrogen floating region 110 to partially remove portions of the dummy substrate 106 from the dummy wafer 144 and the device layer for the SOI substrate. As 116, the upper portion is left. Chemical mechanical polish (CMP) is performed into the portion of the dummy substrate 106 remaining on the carrier wafer 142 to planarize the remaining portion, and to clean the remnant portion 114 of the hydrogen floating region 110 do. The rest of the dummy substrate 106 forms the device layer 116 of the carrier wafer 142.

2 shows a cross-section 200 illustrating an SOI structure with impurity contention layer 108 in accordance with some alternative embodiments. The dummy substrate 118 of the dummy wafer 144 can be doped with high concentration (eg, P++, doping concentration ^greater than 10 ¹⁷ cm ^-3 ), and thick with the impurity contention layer 108 to absorb contaminant metal particles. It can function as an impurity contention body. In some embodiments, dummy substrate 118 may be, for example, less than about 8, 10, or 12 mm 2 /cm, and/or, for example, about 8 to 12 mm 2 /cm, about 8 to 10 mm 2, /cm, or may have a low resistance, which may be about 10 to 12 mm 2 /cm. The hydrogen floating region 110 shown in FIG. 1 may not exist, and the dummy wafer 144 may be removed by a thinning process. The thinning process removes portions of the dummy wafer 144, which may include portions of the entire dummy substrate 118 and the device layer 120. In some embodiments, the thinning process is performed into a dummy wafer 144 that includes the device layer 120 until it leaves an upper portion having a predetermined thickness. The predetermined thickness may be, for example, about 20 to 45 micrometers, about 20 to 32.5 micrometers, or about 32.5 to 45 micrometers.

3 is a cross-sectional view illustrating an SOI structure having an impurity contention layer according to some alternative embodiments. Compared to FIG. 2, a low concentration doped epitaxial layer 130 (eg, a P-doped epi layer) may be deposited on the high concentration doped dummy substrate 126. The impurity contention layer 108 may be formed at an internal position in the epitaxial layer 130. A thinning process is performed to remove portions of the dummy substrate 126, impurity contention layer 108, and epitaxial layer 130, leaving the top portion 132 having a predetermined thickness. The predetermined thickness may be, for example, about 20 to 45 micrometers, about 20 to 32.5 micrometers, or about 32.5 to 45 micrometers.

4 to 10 are cross-sectional views 400 to 1000 showing a method of manufacturing an SOI structure using an impurity contention layer for obtaining contaminant particles according to some embodiments.

As shown in sectional view 400 of FIG. 4, a carrier wafer 142 is provided. The carrier wafer 142 includes a support substrate 102. The insulating layer 104 is formed on the support substrate 102. In some embodiments, support substrate 102 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, glass, silicon dioxide, aluminum oxide, or any combination thereof. In some embodiments, support substrate 102 has a circular top layout and/or a diameter of about 200, 300, or 450 millimeters. In other embodiments, the support substrate 102 has several different shapes and/or several different dimensions. In some embodiments, support substrate 102 has a high resistance and/or low oxygen concentration. The high resistance and low oxygen concentration reduce the substrate and/or RF loss respectively. High resistance may be, for example, greater than about 1, 3, 4, or 9 mm 2 /cm, and/or, for example, about 1 to 4 mm 2 /cm, about 4 to 9 mm 2 /cm, or about 1 It may also be 9 ㏀/cm. The low oxygen concentration may be, for example, about 1, 2, or 5 ppma, and/or may be, for example, about 0.1 to 2.5 ppma, about 2.5 to 5.0 ppma, or about 0.1 to 5.0 ppma. In some embodiments, the support substrate 102 has a low resistance to reduce the cost of the substrate, as the high resistance substrate may be more expensive than, for example, a low resistance substrate. The low resistance may be, for example, less than about 8, 10, or 12 mm 2 /cm, and/or, for example, about 8 to 12 mm 2 /cm, about 8 to 10 mm 2 /cm, or about 10 to 12 mm It may be Ω/cm. In some embodiments, support substrate 102 is doped with a p-type or n-type dopant. The resistance of the support substrate 102 may be controlled, for example, by the doping concentration of the support substrate 102. In some embodiments, the thickness of the support substrate 102 is about 720-780 micrometers, about 720-750 micrometers, or about 750-780 micrometers. The insulating layer 104 may be, for example, silicon dioxide or sapphire. In some embodiments, the insulating layer 104 may be formed by performing a thermal process on the support substrate 102 to form a thermal oxide layer. In other embodiments, the insulating layer 104 may be formed by a deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). An insulating layer 104 may be formed to cover the outer surface of the support substrate 102. In some embodiments, the thickness of the insulating layer 104 is about 0.2 to 2.0 micrometers, about 0.2 to 1.1 micrometers, or about 1.1 to 2.0 micrometers.

5, a dummy wafer 144 is provided. The dummy wafer 144 includes a dummy substrate 106. In some embodiments, dummy substrate 106 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination thereof. In some embodiments, dummy substrate 106 is doped with a p-type or n-type dopant and/or has a low resistivity. The low resistance may be, for example, less than about 0.01 or 0.02 mm 2 /cm, and/or may be, for example, about 0.01 to 0.2 mm 2 /cm. In some embodiments, dummy substrate 106 has a lower resistance than support substrate 102. In some embodiments, dummy substrate 106 has a circular top layout and/or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the dummy substrate 106 has several different shapes and/or several different dimensions. In some embodiments, dummy substrate 106 is a bulk semiconductor substrate and/or a semiconductor wafer. In some embodiments, the thickness of the dummy substrate 106 is about 720-780 micrometers, about 720-750 micrometers, or about 750-780 micrometers. In some embodiments, the thickness of the dummy substrate 106 is the same or approximately the same as the thickness of the support substrate 102.

As also shown in sectional view 500 of FIG. 5, an impurity contention layer 108 is formed on the dummy substrate 106. In some embodiments, the impurity contention layer 108 may be formed by an implantation process at an internal location of the dummy substrate 106 by a carbon implantation process, boron implantation process, phosphorus implantation process, helium implantation process, or a combination thereof. .

6, in some embodiments, hydrogen ions are implanted into the dummy substrate 106 to form a hydrogen floating region 110 embedded within the dummy substrate 106. The hydrogen injection process may be performed from the front surface 146 of the dummy wafer 144 to form the hydrogen floating region 110 at a position in the dummy substrate 106. The hydrogen injection process may increase some potential metal contamination (shown by particles 112 for illustrative purposes) on the dummy wafer 144.

As shown in sectional view 700 of FIG. 7, dummy wafer 144 is bonded to carrier wafer 142 from front side 146. The bonding presses the dummy wafer 144 and the carrier wafer 142 together, and forms a bonding interface in which the insulating layer 104 and the upper portion of the carrier wafer 142 directly contact. Bonding may be performed by, for example, melt bonding, vacuum bonding, or some other bonding process. Melt bonding may be performed, for example, at a pressure of about 1 standard atmospheric pressure (atm), about 0.5 to 1.0 atm, about 1.0 to 1.5, or about 0.5 to 1.5 atm. Vacuum bonding may be performed, for example, at a pressure of about 0.5 to 100 millibars (mBar), about 0.5 to 50 mBar, or about 50 to 100 mBar. The bonding process may also increase some potential metal contamination (shown by particles 112 for illustrative purposes) at the interface between carrier wafer 142 and dummy wafer 144.

8, an annealing process is performed. During the annealing process, the impurity contention layer 108 is directed toward the impurity contention layer 108 from the interface region between the carrier wafer 142 and the dummy wafer 144, as illustrated by the arrow connected to the particles 112. Potentially contaminating particles 112 are absorbed. Thus, potential contaminant particles 112 are removed from the upper portion of the dummy substrate 106 proximate the insulating layer 104. The annealing process is integrated with the bonding annealing process and may enhance bonding of the dummy wafer 144 and the carrier wafer 142. The annealing process may also form linkage voids along the hydrogen floating region 110 by promoting the formation and chaining of brittle silicon hydride. In some embodiments, the annealing process is performed at a temperature of about 300 to 1150°C, about 300 to 725°C, or about 735 to 1150°C. In some embodiments, the annealing process is performed for about 2 to 5 hours, about 2 to 3.5 hours, or about 3.5 to 5 hours. In some embodiments, the annealing process is performed at a pressure of about 1 atm, about 0.5 to 1.0 atm, about 1.0 to 1.5, or about 0.5 to 1.5 atm. In some embodiments, an annealing process is performed while nitrogen gas (eg, N ₂ ) and/or some other gas flows over the structure of FIG. 10. The flow rate of the gas may be, for example, about 1 to 20 standard liters per minute (slm), about 1 to 10 slm, or about 10 to 20 slm.

9, the dummy wafer 144 and the carrier wafer 142 are fractured and separated along the pores of the hydrogen floating region 110 to separate the dummy substrate 106 from the dummy wafer 144. ) Is partially removed.

10, chemical mechanical polishing (CMP) is performed into the portion of the dummy substrate 106 remaining on the carrier wafer 142 to planarize the remaining portion, and to the hydrogen floating region ( The residue portion 114 of 110) is cleaned. The rest of the dummy substrate 106 forms the device layer 116 of the carrier wafer 142.

11 and 12 are cross-sectional views 1100 to 1200 showing some alternative embodiments of a method of manufacturing an SOI structure using an impurity contention layer to obtain contaminant particles. 11 and 12, instead of forming the impurity contention layer 104 in the dummy substrate 106 as shown in FIG. 5, as shown by FIG. 11, The impurity contention layer 104 may have processing steps similar to those illustrated by FIGS. 4-10, except that the impurity contention layer 104 may be formed on the back surface 148 of the dummy substrate 106. The impurity contention layer 108 may be formed by a deposition process such as a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD). The impurity contention layer 108 may be formed on the dummy substrate 106 by a backside sandblasting process or a gettering dry polishing process. The impurity contention layer 108 may be or include a monocrystalline silicon, polycrystalline silicon or silicon acid layer. Next, during the annealing process, as shown by FIG. 12, the impurity contention layer 108, as shown by the arrow connected to the particles 112, the carrier wafer 142 and the dummy wafer 144 Potential contaminant particles 112 are absorbed toward the impurity contention layer 108 from the interface region therebetween. Thus, potential contaminant particles 112 are removed from the upper portion of the dummy substrate 106 proximate the insulating layer 104. The annealing process is integrated with the bonding annealing process and may enhance bonding of the dummy wafer 144 and the carrier wafer 142. Next, a portion of the dummy substrate 106 is removed from the dummy wafer 144, similar to that described above and described in conjunction with FIGS. 9 and 10, forming the device layer 116 of the carrier wafer 142 The remaining portion of the dummy substrate 106 is left. The hydrogen floating region 110 is shown in some views of the embodiment shown in FIGS. 4 to 12, but an alternative manufacturing method for separating the dummy wafer 144 and the carrier wafer 142 is the hydrogen floating region 110. It is understood that it may be embodied in these embodiments in the absence of. For example, the separation method shown below in connection with FIGS. 18 and 24 may be embodied by the embodiments shown in FIGS. 4 to 12.

13-18 are cross-sectional views 1300-1800 illustrating a method of manufacturing an SOI structure using an impurity contention layer to obtain contaminant particles in accordance with some alternative embodiments.

As shown in sectional view 1300 in FIG. 13, a carrier wafer 142 is provided. The carrier wafer 142 includes a support substrate 102. The insulating layer 104 is formed on the support substrate 102. In some embodiments, support substrate 102 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, glass, silicon dioxide, aluminum oxide, or any combination thereof. In some embodiments, support substrate 102 has a circular top layout and/or a diameter of about 200, 300, or 450 millimeters. In other embodiments, the support substrate 102 has several different shapes and/or several different dimensions. In some embodiments, support substrate 102 is doped with a p-type or n-type dopant. The p-type doping concentration of the support substrate 102 may range from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 . In some embodiments, the insulating layer 104 may be formed by performing a thermal process on the support substrate 102 to form a thermal oxide layer. In other embodiments, the insulating layer 104 may be formed by a deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). An insulating layer 104 may be formed to cover the outer surface of the support substrate 102.

As shown in sectional view 1400 in FIG. 14, a dummy wafer 144 is provided. The dummy wafer 144 includes a dummy substrate 106. In some embodiments, dummy substrate 106 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination thereof. In some embodiments, dummy substrate 106 is doped with a p-type or n-type dopant and/or has a low resistivity. As an example, the dummy substrate 106 may be p-type doped silicon having a doping concentration ^greater than 10 ¹⁷ cm ^-3 . The resistance of the dummy substrate 106 may be controlled, for example, by the doping concentration of the dummy substrate 106. The resistance of the dummy substrate 106 may be, for example, less than about 0.01 or 0.02 mm 2 /cm, and/or may be, for example, about 0.01 to 0.2 mm 2 /cm. In some embodiments, dummy substrate 106 has a lower doping concentration and resistance than support substrate 102. In some embodiments, dummy substrate 106 has a circular top layout and/or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the dummy substrate 106 has several different shapes and/or several different dimensions. In some embodiments, dummy substrate 106 is a bulk semiconductor substrate and/or a semiconductor wafer. In some embodiments, the thickness of the dummy substrate 106 is about 720-780 micrometers, about 720-750 micrometers, or about 750-780 micrometers. In some embodiments, the thickness of the dummy substrate 106 is the same or approximately the same as the thickness of the support substrate 102.

15, a device layer 120 is formed on the dummy substrate 106, as shown in sectional view 1500 of FIG. The device layer 120 may be made of or include a semiconductor material such as silicon. The device layer 120 may be formed by an epitaxial deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). For example, the device layer 120 may be a p-type doped epitaxial silicon layer on the dummy substrate 106 having a doping concentration ranging from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 .

16, dummy wafer 144 is bonded to carrier wafer 142. The bonding presses the dummy wafer 144 and the carrier wafer 142 together, and forms a bonding interface in which the insulating layer 104 and the device layer 120 directly contact. Bonding may be performed by, for example, melt bonding, vacuum bonding, or some other bonding process. The bonding process may also increase some potential metal contamination (shown by particles 112 for illustrative purposes) at the interface between carrier wafer 142 and dummy wafer 144.

As shown in sectional view 1700 of FIG. 17, an annealing process is performed. During the annealing process, the heavily doped dummy substrate 106 functions as a thick impurity contention, as shown by the arrows connected to the particles 112, and the device layer 120 and carrier wafer 142 and dummy wafer ( 144) absorbs potential contaminant particles 112 from the interface between them toward the impurity contention layer 108. Thus, potential contaminant particles 112 are removed from the interface between the device layer 120 and the carrier wafer 142 and the dummy wafer 144. The annealing process is integrated with the bonding annealing process and may enhance bonding of the dummy wafer 144 and the carrier wafer 142.

As shown in sectional view 1800 of FIG. 18, a thinning process is performed into the dummy wafer 144. The thinning process removes major portions of the dummy wafer 144 that may include the entire dummy substrate 118 and portions of the device layer 120. In some embodiments, the thinning process is performed into a dummy wafer 144 that includes the device layer 120 until leaving the top portion 120a of the device layer 120 having a predetermined thickness. The predetermined thickness may be, for example, about 20 to 45 micrometers, about 20 to 32.5 micrometers, or about 32.5 to 45 micrometers. The thinning process may include a grinding process, a chemical mechanical polishing process, and a wet etching process such as HNA (hydrofluoric acid, nitric acid, acetic acid) and TMAH (tetramethylammonium hydroxide).

19-24 are cross-sectional views 1900- 2400 showing a method of manufacturing an SOI structure using an impurity contention layer for obtaining contaminant particles in accordance with some alternative embodiments.

As shown in sectional view 1900 in FIG. 19, a carrier wafer 142 is provided. The carrier wafer 142 includes a support substrate 102. The insulating layer 104 is formed on the support substrate 102. In some embodiments, support substrate 102 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, glass, silicon dioxide, aluminum oxide, or any combination thereof. In some embodiments, support substrate 102 has a circular top layout and/or a diameter of about 200, 300, or 450 millimeters. In other embodiments, the support substrate 102 has several different shapes and/or several different dimensions. In some embodiments, support substrate 102 is doped with a p-type or n-type dopant. The p-type doping concentration of the support substrate 102 may range from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 . In some embodiments, the insulating layer 104 may be formed by a deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). The insulating layer 104 may be formed on the upper surface of the support substrate 102. Side and bottom surfaces of the support substrate 102 may be without the insulating layer 104.

As shown in sectional view 2000 in FIG. 20, a dummy wafer 144 is provided. The dummy wafer 144 includes a dummy substrate 106. In some embodiments, dummy substrate 106 is or includes monocrystalline silicon, some other silicon material, some other semiconductor material, or any combination thereof. In some embodiments, dummy substrate 106 is doped with a p-type or n-type dopant and/or has a low resistivity. As an example, the dummy substrate 106 may be p-type doped silicon having a doping concentration ^greater than 10 ¹⁷ cm ^-3 .

20, a lower device layer 130 is formed on the dummy substrate 106. The lower device layer 130 may be made of or include a semiconductor material such as silicon. The lower device layer 130 may be formed by an epitaxial deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). For example, the lower device layer 130 may be a p-type doped epitaxial silicon layer on the dummy substrate 106 having a doping concentration ranging from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 .

As also shown in sectional view 2100 of FIG. 21, an impurity contention layer 108 is formed on the dummy substrate 106. In some embodiments, the impurity contention layer 108 may be formed by depositing an epitaxial layer on the lower device layer 130. The impurity contention layer 108 may be or contain silicon, germanium or other semiconductor material having doping of boron, carbon or other dopants as a gettering source. For example, the impurity contention layer 108 may be or include an epitaxial silicon germanium layer having doping of boron and carbon. The upper device layer 132 may then be formed on the impurity contention layer 108. The upper device layer 132 may be or include a semiconductor material such as silicon. The upper device layer 132 may be formed by an epitaxial deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), or atomic layer deposition process (ALD). For example, the upper device layer 132 may be a p-type doped epitaxial silicon layer on the dummy substrate 106 having a doping concentration ranging from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 .

As shown in sectional view 2200 of FIG. 22, dummy wafer 144 is bonded to carrier wafer 142. The bonding presses the dummy wafer 144 and the carrier wafer 142 together, and forms a bonding interface in which the insulating layer 104 and the device layer 120 directly contact. Bonding may be performed by, for example, melt bonding, vacuum bonding, or some other bonding process. The bonding process may also increase some potential metal contamination (shown by particles 112 for illustrative purposes) at the interface between carrier wafer 142 and dummy wafer 144.

23, an annealing process is performed. During the annealing process, the impurity contention layer 108 and the highly doped dummy substrate 106 function as a thick impurity contention, as shown by the arrows connected to the particles 112, and the carrier wafer 142 and the dummy wafer Potential contaminant particles 112 are absorbed from the interface between 144 toward the impurity contention layer 108. Thus, potential contaminant particles 112 are removed from the interface between the carrier wafer 142 and the dummy wafer 144. The annealing process is integrated with the bonding annealing process and may enhance bonding of the dummy wafer 144 and the carrier wafer 142.

As shown in cross-section 2400 of FIG. 24, a thinning process is performed into dummy wafer 144. The thinning process removes major portions of the dummy wafer 144, which may include portions of the dummy substrate 118, the lower device layer 130, the impurity contention layer 108, and the upper device layer 132, prior to The upper portion 132a of the upper device layer 132 having the determined thickness is left. The predetermined thickness may be, for example, about 20 to 45 micrometers, about 20 to 32.5 micrometers, or about 32.5 to 45 micrometers. In some embodiments, the thinning process includes a first etch step that stops on impurity contention layer 108, a second etch step that removes impurity contention layer 108 and stops on top device layer 132, and a more precise etch. It is performed by a plurality of etch steps, which may include a third etch step performed on the upper device layer 132 with control. As an example, the first etchant for the first etch step may include TMAH, and may have an etch rate ratio of the lower device layer 130 to an impurity contention layer 108 greater than 100. The second etchant for the second etch step may include hydrofluoric acid or nitric acid, or may have an etch rate ratio of the impurity contention layer 108 to the upper device layer 132 greater than at least 7.

25 is a flowchart of a method for manufacturing an SOI structure according to some embodiments. The SOI structure includes an impurity contention layer formed on a dummy wafer to provide contaminated metal gettering. Exemplary methods of forming the SOI structure are shown in FIGS. 4-10, 11 and 12, 13-13, and 19-24. 4 to 10, 11 and 12, 13 to 18, and 19 to 24 are described in connection with the method shown in FIG. 25, but FIGS. 4 to 10, 11 and 12, It should be noted that the structures disclosed in FIGS. 13 to 18 and 19 to 24 are not limited to the method illustrated in FIG. 25, but may instead stand alone as a structure independent of the method illustrated in FIG. 25. Will be understandable. Similarly, the method illustrated in FIG. 25 is described with respect to FIGS. 4 to 10, 11 and 12, 13 to 18, and 19 to 24, but the method illustrated in FIG. 25 is illustrated in FIG. It is not limited to the structures disclosed in FIGS. 4 to 10, 11 and 12, 13 to 18, and 19 to 24, instead, instead of FIGS. 4 to 10, 11 and 12, and 13 to It will be understood that it may stand alone as a structure independent of the structures disclosed in FIGS. 18 and 19-24. Also, although the disclosed method (eg, the method illustrated in FIG. 25) is illustrated and described below as a series of actions or events, it is understood that the illustrated order of such actions or events should not be interpreted as a limiting concept. It could be. For example, some actions may occur in different orders and/or concurrently with other actions or events other than those illustrated and/or described herein. Moreover, it is also possible that not all illustrated acts are required to implement one or more aspects or embodiments of the description herein. Further, one or more of the operations described herein may be performed in one or more individual operations and/or steps.

In operation 2502, a dummy substrate is prepared for the dummy wafer. See, for example, those shown by the cross-sections shown in FIGS. 5 and 6, 11, 14 and 15, or 20 and 21.

In operation 2504, an impurity contention layer is formed for the dummy wafer. See, for example, what is shown by the cross-section shown in FIGS. 5, 11, or 21.

In operation 2506, a carrier wafer having an insulating layer is provided over the support substrate. See, for example, what is shown by the cross-sectional views shown in FIGS. 4, 13, or 19.

In operation 2508, the dummy wafer and the carrier wafer are joined. See, for example, what is shown by the cross-sectional views shown in FIGS. 7, 16, or 22.

In operation 2510, an annealing process is performed. During the annealing process, the impurity contention layer absorbs metal from the dummy substrate. See, for example, what is shown by the cross-sectional views shown in FIGS. 8, 12, 17, or 23.

In operation 2512, at least a portion of the impurity contention layer and the dummy substrate is removed, leaving the device layer on the carrier wafer. See, for example, what is shown by the cross-sectional views shown in FIGS. 9, 10, 18, or 24.

Thus, as can be understood from above, the present disclosure relates to SOI structures and associated methods. An impurity contention layer or impurity contention body is formed and used during the annealing process to absorb metal particles and reduce contamination of the SOI structure to the semiconductor layer. The impurity contention layer is positioned at or within the back surface of the dummy wafer, and may include a doped semiconductor material having a gettering source.

In some embodiments, the present disclosure relates to a method of forming an SOI structure. The method includes preparing a dummy substrate for a dummy wafer and forming an impurity contention layer on the dummy substrate. The method further includes providing a carrier wafer comprising an insulating layer over the support substrate and bonding the front side of the dummy wafer to the carrier wafer. The method further includes performing an annealing process in which the impurity contention layer absorbs metal from the upper portion of the dummy substrate. The method further includes removing the main portion of the dummy substrate including the impurity contention layer, leaving the device layer of the dummy substrate on the insulating layer of the carrier wafer.

In another embodiment, the present disclosure is directed to a method of forming an SOI structure. The method includes preparing a dummy substrate for the dummy wafer and forming an impurity contention layer on the back surface of the dummy wafer. The method further includes providing a carrier wafer comprising an insulating layer over the support substrate and bonding the front side of the dummy wafer to the carrier wafer. The method further includes performing an annealing process. The impurity contention layer absorbs the metal from the upper portion of the dummy substrate. The method further includes removing the impurity contention layer and the main portion of the dummy substrate, leaving the device layer of the dummy substrate on the insulating layer of the carrier wafer.

In another embodiment, the present disclosure relates to a method of forming an SOI structure. The method includes preparing a dummy substrate for a dummy wafer and forming an impurity contention layer on the dummy substrate. The method further includes forming a device layer on the impurity contention layer and providing a carrier wafer comprising an insulating layer over the support substrate. The method further includes bonding the front side of the dummy wafer to the carrier wafer. The method further includes performing an annealing process in which the dummy substrate absorbs metal from the device layer. The method further includes performing a thinning process to remove the dummy substrate and leave at least a portion of the device layer on the insulating layer of the carrier wafer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should understand that they may immediately use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same objectives of the embodiments presented herein and/or to achieve the same advantages. do. Those skilled in the art also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and modifications of the specification without departing from the spirit and scope of the invention. Should be.

Examples

Example 1. A method of forming an SOI structure,

Preparing a dummy substrate for the dummy wafer;

Forming an impurity competing layer on the dummy substrate”;

Forming an insulating layer on the support substrate;

Bonding the entire surface of the dummy wafer to the insulating layer;

Performing an annealing process in which the impurity contention layer absorbs metal from an upper portion of the dummy substrate; And

Removing a major portion of the dummy substrate including the impurity contention layer and leaving the rest of the dummy substrate as a device layer on the insulating layer

A method of forming a SOI structure comprising: a.

Example 2. In Example 1,

A method of forming an SOI structure, wherein the impurity contention layer is injected into the dummy substrate by a carbon implantation process.

Example 3 In Example 1, before the step of bonding the dummy wafer to the insulating layer,

And forming a hydrogen-rich region at a position in the dummy substrate under the device layer by performing a hydrogen injection process on the front surface of the dummy wafer.

Example 4. In Example 3,

The hydrogen injection process is performed after forming the impurity contention layer, a method of forming an SOI structure.

Example 5. In Example 1,

The impurity contention layer is a method of forming an SOI structure, which is injected into the dummy substrate by a boron implantation process.

Example 6. In Example 1,

The impurity contention layer is a method of forming an SOI structure, which is injected into the dummy substrate by a phosphorus implantation process.

Example 7. In Example 1,

The impurity contention layer is implanted into the dummy substrate by a helium implantation process.

Example 8. In Example 1,

A method of forming an SOI structure, prior to the bonding step, performing a thermal process on the support substrate to form a thermal oxide layer as an insulating layer.

Example 9. In Example 1,

A method of forming an SOI structure, wherein the dummy substrate of the dummy wafer is p-type doped silicon having a doping concentration greater than 10 ¹⁷ cm ^-3 .

Example 10. In Example 9,

And forming a p-type doped epitaxial silicon layer having a doping concentration in a range from about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 on the dummy substrate.

Example 11. In Example 10,

The dummy substrate and a portion of the p-type doped epitaxial silicon layer are left while the upper portion of the p-type doped epitaxial silicon layer is left on the insulating layer by performing a polishing process on the back surface of the dummy substrate. A method of forming an SOI structure, further comprising removing.

Example 12. A method of forming an SOI structure,

Preparing a dummy substrate for the dummy wafer;

Forming an impurity contention layer on the back surface of the dummy wafer;

Forming an insulating layer on the support substrate;

Bonding the entire surface of the dummy wafer to the insulating layer;

Performing an annealing process in which the impurity contention layer absorbs metal from an upper portion of the dummy substrate; And

Removing the impurity contention layer and main parts of the dummy substrate while leaving the device layer of the dummy substrate on the insulating layer

A method of forming a SOI structure comprising: a.

Example 13. In Example 1,

The impurity contention layer is a method of forming an SOI structure, which is formed by a backside sandblasting process or a gettering dry polishing process for the dummy substrate.

Example 14. The method of Example 1, wherein the impurity contention layer is formed by a deposition process of a polysilicon layer or a silicon oxynitride layer.

Example 15. A method of forming an SOI structure,

Preparing a dummy substrate for the dummy wafer;

Forming an impurity contention layer on the dummy substrate;

Forming a device layer on the impurity contention layer;

Forming an insulating layer on the support substrate;

Bonding the entire surface of the dummy wafer to the insulating layer;

Performing an annealing process in which the dummy substrate absorbs metal from the device layer; And

Performing a thinning process to remove the dummy substrate and leaving a device layer on the insulating layer

A method of forming an SOI structure comprising: a.

Example 16. The method of Example 15,

The dummy substrate is a p-type doped silicon having a doping concentration of greater than 10 ¹⁷ cm ^-3 , the method of forming an SOI structure.

Example 17. The method of Example 15,

The impurity contention layer is formed by depositing an epitaxial silicon germanium layer having doping of boron and carbon, forming a SOI structure.

Example 18. The method of Example 15,

Wherein the thinning process has an etch rate for the impurity contention layer that is at least 7 times larger than the device layer.

Example 19. The method of Example 15,

The impurity contention layer is formed to have a thickness in the range of about 5 nm to about 15 nm, a method of forming an SOI structure.

Example 20. In Example 15,

And forming a p-type silicon layer having a doping concentration in a range of about 10 ¹⁴ cm ^-3 to about 10 ¹⁶ cm ^-3 between the impurity contention layer and the dummy substrate. .

Claims (10)

As a method of forming an SOI structure,
Preparing a dummy substrate for the dummy wafer;
Forming an impurity competing layer on the dummy substrate;
Forming an insulating layer on the support substrate;
Bonding the entire surface of the dummy wafer to the insulating layer;
Performing an annealing process in which the impurity contention layer absorbs metal from an upper portion of the dummy substrate; And
Removing a major portion of the dummy substrate including the impurity contention layer and leaving the rest of the dummy substrate as a device layer on the insulating layer
A method of forming a SOI structure comprising: a. According to claim 1,
The impurity contention layer is a method of forming an SOI structure, which is injected into the dummy substrate by at least one of a carbon injection process, a boron implantation process, a phosphorus implantation process, and a helium implantation process. According to claim 1, Before the step of bonding the dummy wafer to the insulating layer,
And forming a hydrogen-rich region at a position in the dummy substrate under the device layer by performing a hydrogen injection process on the front surface of the dummy wafer. According to claim 3,
The hydrogen injection process is performed after forming the impurity contention layer, a method of forming an SOI structure. According to claim 1,
A method of forming an SOI structure, prior to the bonding step, performing a thermal process on the support substrate to form a thermal oxide layer as an insulating layer. According to claim 1,
A method of forming an SOI structure, wherein the dummy substrate of the dummy wafer is p-type doped silicon having a doping concentration greater than 10 ¹⁷ cm ^-3 . The method of claim 6,
And forming a p-type doped epitaxial silicon layer having a doping concentration in the range of 10 ¹⁴ cm ^-3 to 10 ¹⁶ cm ^-3 on the dummy substrate. The method of claim 7,
The dummy substrate and a portion of the p-type doped epitaxial silicon layer are left while the upper portion of the p-type doped epitaxial silicon layer is left on the insulating layer by performing a polishing process on the back surface of the dummy substrate. A method of forming an SOI structure, further comprising removing. As a method of forming an SOI structure,
Preparing a dummy substrate for the dummy wafer;
Forming an impurity contention layer on the back surface of the dummy wafer;
Forming an insulating layer on the support substrate;
Bonding the entire surface of the dummy wafer to the insulating layer;
Performing an annealing process in which the impurity contention layer absorbs metal from an upper portion of the dummy substrate; And
Removing the impurity contention layer and main portions of the dummy substrate while leaving the device layer of the dummy substrate on the insulating layer
A method of forming a SOI structure comprising: a. As a method of forming an SOI structure,
Preparing a dummy substrate for the dummy wafer;
Forming an impurity contention layer on the dummy substrate;
Forming a device layer on the impurity contention layer;
Forming an insulating layer on the support substrate;
Bonding the entire surface of the dummy wafer to the insulating layer;
Performing an annealing process in which the dummy substrate absorbs metal from the device layer; And
Performing a thinning process to remove the dummy substrate and leaving a device layer on the insulating layer
A method of forming a SOI structure comprising: a.

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