KR20200032586A - Gate driver, organic light emitting display apparatus and driving method thereof - Google Patents

Abstract

According to the present exemplary embodiment, an input unit receiving the first clock and the second clock, a plurality of signal output units respectively outputting a plurality of scan clocks corresponding to the first clock and the second clock, and the first clock and the second clock A gate driver including a counter for counting at least one of clocks, an organic light emitting display device using the same, and a driving method thereof can be provided.

Description

Gate driver, organic light emitting display device and its driving method {GATE DRIVER, ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND DRIVING METHOD THEREOF}

The present embodiments relate to a gate driver, an organic light emitting display device, and a driving method thereof.

As the information society develops, demands for display devices for displaying images are increasing in various forms, and liquid crystal display devices (LCDs), plasma display devices (PDPs), and organic light emitting displays ( Various types of flat panel display devices such as OLED: Organic Light Emitting Display Device) have appeared.

Recently, among the flat panel display devices, an organic light emitting display device that is easy to thin and has excellent viewing angle and contrast ratio has been widely used. The organic light emitting display device expresses an image by emitting light by supplying a driving current to an organic light emitting diode, which is a self-light emitting device. However, if the organic light emitting diode emits light for a long time, deterioration occurs. In particular, when displaying a still image with high luminance, deterioration may be more easily generated. The organic light emitting diode may have a residual image due to deterioration, which may cause a problem of shortening the life.

In addition, the driving transistors that supply the driving current to the organic light emitting diode may have a threshold voltage difference due to a process deviation, which may cause a difference in driving current for each subpixel. When a difference in driving current occurs, the luminance is not uniform, and thus the organic light emitting display device has a problem of deteriorating image quality. In addition, when the organic light-emitting diode is deteriorated, there is a problem in that it emits light with a lower luminance than the gradation voltage.

For this reason, the organic light emitting display device operates in a sensing mode for sensing the characteristics of the display panel to prevent deterioration of image quality, and a display mode for correcting a data signal in response to the sensed result and displaying an image using the corrected data signal can do.

The organic light emitting display device can sense the characteristics of the display panel in real time. In the display panel, a blanking section is set between display sections displaying an image, and when sensing in real time, the blanking section is performed. Therefore, since the sensing time is very short, it is difficult to sense in real time for all sub-pixels included in the display panel, so only sub-pixels connected to a specific gate line should be sensed.

Therefore, the organic light emitting display device must be able to select a specific gate line among a plurality of gate lines of the display panel in order to sense in real time.

An object of the present embodiments can provide a gate driver, an organic light emitting display device, and a driving method thereof that can prevent the image quality from deteriorating.

In addition, another object of the present embodiments is to provide a gate driver, an organic light emitting display device and a driving method capable of reducing manufacturing cost.

In one aspect, the present exemplary embodiments include a signal output unit including an input unit receiving a first clock and a second clock, and a plurality of output circuits outputting a scan clock corresponding to the first clock and the second clock, respectively. It is to provide a gate driver including a counter for counting at least one of the first clock and the second clock.

In another aspect, the present embodiments provide a display panel, a level shifter that supplies a gate signal to the display panel, and outputs a plurality of clock signals, and a gate signal that receives the plurality of clock signals and supplies the gate signal to a display panel. It includes a gate driver including an output circuit, a data driver supplying a data signal to the display panel, and a timing controller controlling the gate driver and data driver. The level shifter receives the first clock and the second clock from the timing controller. An input unit, an output unit including a plurality of output circuits outputting a plurality of scan clocks corresponding to the first clock and a second clock to the gate signal output circuit, and a counter counting at least one of the first clock and the second clock It is to provide an organic light emitting display device.

In another aspect, in the present exemplary embodiments, at least one of a first mode and a second clock in response to a line selection signal, a display mode sequentially supplying gate signals corresponding to the first clock and the second clock to a plurality of gate lines. Supply the sensing clocks corresponding to the first clock and the second clock to the selected line in the line selection mode and the line selection mode to select the gate line to receive the sensing clock among the plurality of gate lines in response to the counted number. It provides a method of driving an organic light emitting display device that includes a sensing mode.

According to embodiments of the present invention, an organic light emitting display device capable of improving image quality and a driving method thereof can be provided.

According to embodiments of the present invention, to provide a gate driver, an organic light emitting display device and a driving method thereof, which can reduce manufacturing cost.

1 is a structural diagram showing an embodiment of an organic light emitting display device according to embodiments of the present invention.
2 is a circuit diagram illustrating an embodiment of the subpixel shown in FIG. 1.
3A is a timing diagram illustrating generating a driving current in a subpixel.
3B is a timing diagram illustrating sensing a threshold voltage in a subpixel.
3C is a timing diagram illustrating a process of sensing electron mobility in a subpixel.
4 is a waveform diagram illustrating the operation of the organic light emitting display device shown in FIG. 1.
FIG. 5 is a structural diagram showing the structure of the data driver shown in FIG. 1.
6 is a structural diagram illustrating an embodiment of a connection relationship between a timing controller and a gate driver shown in FIG. 1.
7 is a structural diagram showing an embodiment of the level shifter shown in FIG.
8 is a timing diagram showing waveforms of signals input / output to the level shifter.
9 is a structural diagram showing an embodiment of a gate signal output circuit.
10 is a flowchart illustrating an embodiment of a method of driving an organic light emitting display device according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, the same components may have the same reference numerals as possible even though they are displayed on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of related known configurations or functions may obscure the subject matter of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for distinguishing the component from other components, and the essence, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected to or connected to the other component, but different components between each component It will be understood that the "intervenes" may be, or each component may be "connected", "coupled" or "connected" through other components.

1 is a structural diagram showing an embodiment of an organic light emitting display device according to embodiments of the present invention.

Referring to FIG. 1, the organic light emitting display device 100 may include a display panel 110, a data driver 120, a gate driver 130, and a timing controller 140.

The display panel 110 may be arranged such that a plurality of gate lines GL1,…, GLn and a plurality of data lines DL1,…, DLm intersect. In addition, the plurality of subpixels 101 may be formed to correspond to regions where the plurality of gate lines GL1,…, GLn and the plurality of data lines DL1,…, DLm intersect. The plurality of sub-pixels 101 may include an organic light emitting diode (not shown) and a pixel circuit (not shown) that supplies a driving current to the organic light emitting diode. The pixel circuit is connected to the gate lines GL1, ..., GLn and the data lines DL1, ..., DLm to supply a driving current to the organic light emitting diode. Here, the wiring arranged on the display panel 110 is not limited to the plurality of gate lines GL1, ..., GLn and the plurality of data lines DL1, ..., DLm.

The data driver 120 may apply a data signal to a plurality of data lines DL1, ..., DLm. The data signal may correspond to gradation, and the voltage level of the data signal may be determined according to the gradation. The voltage of the data signal may be referred to as a data voltage. Also, the data driver 120 may transmit a sensing signal to the data lines DL1, ..., DLm. The sensing signal may be a signal sensing a characteristic value of a subpixel. The voltage of the sensing signal may be referred to as a sensing voltage. If the voltage applied to the organic light-emitting diode is a voltage lower than the threshold voltage of the organic light-emitting diode, no current flows through the organic light-emitting diode, so that light is not emitted. In order to prevent the current from flowing through the organic light-emitting diode by the sensing voltage, the sensing voltage may be a voltage lower than the threshold voltage of the organic light-emitting diode. The data driver 120 can sense the voltage applied to the organic light emitting diode.

Here, although the number of data drivers 120 is shown as one, it is not limited thereto, and may be two or more corresponding to the size and resolution of the display panel 110. Also, the data driver 120 may be implemented as an integrated circuit.

The gate driver 130 may apply a gate signal to a plurality of gate lines GL1,…, GLn. The subpixel 101 corresponding to the plurality of gate lines GL1, ..., GLn to which the gate signal is applied may receive a data signal. Also, the gate driver 130 may transmit a sensing control signal to the sub-pixel 101. The sub-pixel 101 receiving the sensing control signal output from the gate driver 130 may receive the sensing voltage output from the data driver 120. Here, the number of gate drivers 130 is shown as one, but is not limited thereto, and may be at least two. Further, the gate drivers 130 are disposed on both sides of the display panel 110, and one gate driver 130 is connected to an odd numbered gate line among the plurality of gate lines GL1, ..., GLn and the other gate driver. The 130 may be connected to an even-numbered gate line among the plurality of gate lines GL1,…, GLn. However, it is not limited thereto. The gate driver 130 may be implemented as an integrated circuit.

The timing controller 140 can control the data driver 120 and the gate driver 130. In addition, the timing controller 140 may transmit sensing data corresponding to the sensing result and image data corresponding to the data signal to the data driver 120. The timing controller 140 may sequentially output sensing data and image data corresponding to one frame section. The sensing data and image data may be digital signals. The timing controller 140 may correct the data signal and transmit it to the data driver 120. The operation of the timing controller 140 is not limited to this.

In addition, the timing controller 140 may transfer the first clock and the second clock to the gate driver 130 and the gate driver 130 may output a gate signal using the first clock and the second clock. The signal output from the gate driver 130 is not limited thereto. The timing controller 140 may correct the data signal in response to the sensing control signal and then transmit the data signal to the data driver 120. The timing controller 140 may be implemented as an integrated circuit.

FIG. 2 is a circuit diagram illustrating an embodiment of the subpixel shown in FIG. 1, and FIG. 3A is a timing diagram illustrating a process of generating a driving current in the subpixel. 3B is a timing diagram illustrating a process of sensing a threshold voltage in a subpixel. In addition, FIG. 3C is a timing diagram illustrating a process of sensing voltage mobility in a subpixel.

Referring to FIG. 2, the sub-pixel 101 may include an organic light emitting diode (OLED) and a pixel circuit driving the organic light emitting diode (OLED). The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cs.

The first transistor M1 has a first electrode connected to a first node N1 connected to a first power line VL1 to which a pixel high potential voltage EVDD is transmitted, and a gate electrode connected to a second node N2. The second electrode may be connected to the third node N3. The first transistor M1 may allow current to flow from the first node N1 to the third node N3 in response to the voltage transmitted to the second node N2. The first electrode of the first transistor M1 may be a drain electrode, and the second electrode may be a source electrode. However, it is not limited thereto.

The current flowing from the first node N1 to the third node N3 may correspond to Equation 1 below.

Here, Id is the amount of current flowing from the first node (N1) to the third node (N3), k is the electron mobility of the transistor, V _GS is the gate electrode of the first transistor (M1) The voltage difference between the source electrode and Vth means the threshold voltage of the first transistor M1.

Therefore, since the amount of current varies according to the deviation of the electron mobility and the threshold voltage, the image quality can be prevented from deteriorating by correcting the data signal in response to the deviation of the electron mobility and the threshold voltage.

The second transistor M2 may have a first electrode connected to the data line DL, a gate electrode connected to the gate line GL, and a second electrode connected to the second node N2. Accordingly, the second transistor M2 may transmit the data voltage Vdata corresponding to the data signal to the second node N2 in response to the gate signal transmitted through the gate line GL. The first electrode of the second transistor M2 may be a drain electrode, and the second electrode may be a source electrode. However, it is not limited thereto.

In the third transistor M3, a first electrode is connected to the third node N3, a gate electrode is connected to a sensing line Sense transmitting a sensing control signal, and a second electrode is connected to the second power line VL2. You can. The third transistor M3 initializes the voltage of the third node N3 by transmitting the first initialization voltage VpreR or the second initialization voltage VpreS in response to the sensing control signal transmitted to the sensing line Sense. You can. The first initialization voltage VpreR initializes the third node N3 when the data voltage Vdata is applied to the data line DL, and the second initialization voltage VpreS senses the sensing voltage Vsense to the data line DL. ) Is applied, the third node N3 may be initialized. However, it is not limited thereto.

Also, the voltage applied to the third node N3 may include information corresponding to the characteristic value of the subpixel 101. Therefore, the characteristic value of the sub-pixel 101 can be grasped using the voltage of the third node N3 and the data signal can be compensated. The characteristic value of the sub-pixel 101 may be threshold voltage of the first transistor M1, electron mobility, and deterioration information of the organic light emitting diode OLED. However, it is not limited thereto. The first electrode of the third transistor M3 may be a drain electrode, and the second electrode may be a source electrode. However, it is not limited thereto.

The capacitor Cs may be connected between the first node N1 and the third node N3. The capacitor Cs may maintain the voltage of the gate electrode and the voltage of the source electrode of the first transistor M1 constant.

In the organic light emitting diode OLED, the anode electrode may be connected to the third node N3 and the cathode electrode may be connected to the pixel low potential voltage EVSS. Here, the pixel low potential voltage (EVSS) may be ground. However, it is not limited thereto. The organic light emitting diode (OLED) may emit light in response to the amount of current when current flows from the anode electrode to the cathode electrode. The organic light emitting diode (OLED) may emit any one of red, green, blue, and white colors. However, it is not limited thereto.

The circuit of the subpixel employed in the organic light emitting display device 100 is not limited thereto.

Also, an analog digital converter 120b may be connected to the pixel circuit. The analog digital converter 120b may be connected to the second power line VL2. The analog digital converter 120b may receive the voltage of the third node N3 through the second power line VL2 and convert it into a digital signal. The digital signal converted by the analog digital converter 120b may be supplied to the timing controller 140. However, it is not limited thereto.

The operation of supplying the driving current to the organic light emitting diode (OLED) in the pixel circuit will be described with reference to FIG. 3A.

The third node N3 may be initialized by turning on the first switch RPRE and turning on the third transistor M3 by the sensing control signal Ssen. Then, the first switch RPRE and the third transistor M3 may be turned off. When the second transistor M2 is turned on by the gate signal GATE, the data voltage Vdata may be transmitted to the second node N2. The first transistor M1 may allow a driving current to flow from the first node N1 to the third node N3 in response to the voltage between the second node N2 and the third node N3. Therefore, the driving current may flow corresponding to the data voltage Vdata.

Then, the operation of sensing the threshold voltage in the pixel circuit may be described using FIG. 3B.

First, the gate signal GATE is transmitted while a predetermined voltage is applied to the data line DL, so that the second transistor M2 may be turned on. When the second transistor M2 is turned on, a voltage applied to the data line DL may be supplied to the second node N2. Then, in response to the voltage applied to the second node N2, a current flows from the first node N1 to the third node N3 by the first transistor M1, so that the voltage level of the third node N3 This becomes higher.

Then, the second switch SPRE may be turned on. When the second switch SPRE is turned on, the second initialization voltage VpreS may be transmitted to the second power line VL2. After the second switch SPRE is turned on, when the sensing control signal is supplied through the sensing control signal line Sense, the third transistor M3 may be turned on. After the third transistor M3 is turned on, the second switch SPRE may be turned off. When the third transistor M3 is turned on while the second switch SPRE is turned off, the voltage of the third node N3 rises and a certain period of time after the voltage of the third node N3 starts to rise. When it has elapsed, the third switch SAM may be turned on. When the third switch SAM is turned on, the voltage of the third node N3 may be transmitted to the analog digital converter 120b. The third switch SAM may be turned on when the voltage of the third node N3 no longer rises. At this time, the threshold voltage of the first transistor M1 may be sensed by comparing the voltage sensed by the analog digital converter 120b with a preset voltage.

As described above, in the process of generating the driving current, the first initialization voltage VpreR is transmitted through the second power line VL2 in the process of generating the driving current.

In addition, the process of sensing the voltage mobility in the pixel circuit may be described using FIG. 3C.

First, the gate signal GATE is transmitted while a predetermined voltage is applied to the data line DL, so that the second transistor M2 may be turned on. The preset voltage may be a sensing voltage (Vsense). When the second transistor M2 is turned on, the sensing voltage Vsense applied to the data line DL may be supplied to the second node N2. In addition, the third transistor M3 may be turned on by the sensing control signal Ssen. At this time, the second switch SPRE may be turned on. When the third transistor M3 and the second switch SPRE are turned on, the second initialization voltage VpreS may be transmitted to the third node N3.

The second transistor M2 may be turned off and the second switch SPRE may be turned off by the gate signal GATE. When the second transistor M2 and the second switch SPRE are turned off, the second node N2 and the third node N3 may be floating. At this time, the first transistor M1 corresponds to the voltage of the second node N2 so that the sensing current flows through the third transistor M3 to the second power line VL2. The voltage of the second power line VL2 is increased due to the sensing current, so that the voltage level of the third node N3 is increased. At this time, since the second node N2 is connected through the third node N3 and the capacitor Cs, the voltage level of the second node N2 also increases. The voltage of the third node N3 rises with a constant slope, and the slope becomes electron mobility. Then, after the time of the predetermined time t1 has elapsed, the third switch SAM is turned on, and information about the electron mobility may be transferred to the analog digital converter 120b.

4 is a waveform diagram illustrating the operation of the organic light emitting display device shown in FIG. 1.

Referring to FIG. 4, the organic light emitting display device may display an image including a plurality of frames, and an image corresponding to one frame in each frame section may be displayed. The plurality of frames may include a first frame section (1st frame) and a second frame (2nd frame). The first frame section (1st frame) and the second frame (2nd frame) may each include a blank section (blank) section and a display section (Display). A gate signal is output to the display section to receive a data signal to display an image.

The organic light emitting display device 100 driven as described above receives black data in a blank section and does not display an image, but receives a data signal in a display section and displays an image. Since an image is not displayed in the blank section, the sensing mode may be performed in response to the blank section. When the sensing mode is performed in the blank section, the sensing voltage Vsense may be supplied to the data line. The sensing voltage Vsense may be a voltage lower than the threshold voltage of the organic light emitting diode OLED.

FIG. 5 is a structural diagram showing the structure of the data driver shown in FIG. 1.

Referring to FIG. 5, the data driver 120 may include a digital-to-analog converter 120a and an analog-to-digital converter 120b. The digital-to-analog converter 120a may be connected to the data line DL, and the analog-to-digital converter 120b may be connected to the second power line VL2. The digital-to-analog converter 120a and the analog-to-digital converter 120b are illustrated as being connected to one data line DL and a second power line VL2, respectively, but are not limited thereto.

The digital-to-analog converter 120a may receive image data RGB from the timing controller 140. Also, the digital-to-analog converter 120a may receive sensing data Dsense from the timing controller 140. The digital-to-analog converter 120a may generate a data signal and a data voltage using image data RGB and sensing data and supply the data signal to the data line DL.

The analog digital converter 120b may convert a voltage transmitted from the second power line VL2 into a digital signal. The analog digital converter 120b may generate sensing data Dsense in response to the voltage transmitted from the second power line VL2.

6 is a structural diagram illustrating an embodiment of a connection relationship between a timing controller and a gate driver shown in FIG. 1.

Referring to FIG. 6, the timing controller 140 may output a first clock (G-CLK), a second clock (M-CLK), a line selection signal (Mute), and a sensing mode signal (CSP). The timing controller 140 may supply the first clock (G-CLK) and the second clock (M-CLK) differently according to the display mode, the line selection mode, and the sensing mode. The first clock (G-CLK) and the second clock (M-CLK) supplied differently may have different clock waveforms. When the clock waveform is supplied differently, periods and / or phases of the first clock (G-CLK) and the second clock (M-CLK) clock may be different. The timing controller 140 may supply the first clock (G-CLK) and the second clock (M-CLK) through a separate output stage in response to a display mode, a line selection mode, and a sensing mode, and a display mode at one output stage. , Line selection mode, can be supplied in response to the sensing mode. In addition, the timing controller 140 may output a line selection signal (Mute) and a sensing mode signal (CSP) in response to a display mode, a line selection mode, and a sensing mode.

The timing controller 140 outputs the first clock (G-CLK) and the second clock (M-CLK) in the display mode, and the first clock (G-CLK) and second clock (M-CLK) in the line selection mode. ), The line selection signal (Mute) is output, and in the sensing mode, the first clock (G-CLK), the second clock (M-CLK), and the sensing mode signal (CSP) can be output. However, the signal output from the timing controller 140 does not correspond to this.

The gate driver 130 may receive the first clock (G-CLK), the second clock (M-CLK), the line selection signal (Mute), and the sensing mode signal (CSP) from the timing controller 140. The gate driver 130 may output a plurality of gate signals (GATE1, GATE2, ..., GATEn-1, GATEn). Also, the gate driver 130 may output a sensing clock (SSCLK). The gate driver 130 may receive the first clock (G-CLK) and the second clock (M-CLK) in the display mode to generate a plurality of scan clocks (SCCLK1 to SCCLK6). In addition, the gate driver 130 may output a plurality of gate signals GATE1, GATE2, ..., GATEn-1, GATEn in response to the plurality of scan clocks SCCLK1 to SCCLK6. When the gate driver 130 receives the line selection signal Mute, it does not output the scan clocks SSCLK1 to SSCLK6. In addition, the gate driver 130 acquires counting information counting the rising edge of the first clock (G-CLK) and the falling edge of the second clock (M-CLK), and responds to the counting information, one of a plurality of gate lines You can select the gate line. When the gate driver 130 receives the sensing mode signal CSP, the gate driver 130 may determine that it has entered the sensing mode and supply the sensing clock SSCLK to the selected gate line.

Further, the gate driver 130 may include a second clock (M-CLK) and a gate signal output circuit 130b.

The second clock (M-CLK) may receive the first clock (G-CLK) and the second clock (M-CLK) from the timing controller 140 to generate a plurality of scan clocks (SCCLK1 to SCCLK6). The number of scan clocks (SCCLK1 to SCCLK6) generated by the second clock (M-CLK) is illustrated as six, but is not limited thereto. The plurality of scan clocks SCCLK1 to SCCLK6 generated in the second clock M-CLK may be supplied to the gate signal output circuit 130b. When the display panel 110 illustrated in FIG. 1 has a resolution of UHD (Ultra high definition), 2160 gate lines may be included, so the gate signal output circuit 130b may output 2160 gate signals. However, the number of gate signals output from the gate signal output circuit 130b is not limited thereto. The gate signal output circuit 130b may receive six scan clocks SCCLK1 to SCCLK6 from the second clock M-CLK and sequentially output gate signals to 2160 gate lines.

7 is a structural diagram showing an embodiment of the level shifter shown in FIG.

Referring to FIG. 7, the level shifter 130a includes an input unit 131a receiving a first clock (G-CLK) and a second clock (M-CLK), a first clock (G-CLK), and a second clock ( M-CLK) may include output units 132a including a plurality of output circuits 1301 to 1306 outputting scan clocks SCCLK1 to SCCLK6, respectively. In addition, the level shifter 130a may include a counter 133a counting at least one of the first clock (G-CLK) and the second clock (M-CLK). When the plurality of output circuits 1301 to 1306 receive the line selection signal Mute, the scan clocks SCCLK1 to SCCLK6 are not output.

The counter 133a may count the rising edge of the first clock G-CLK and / or the falling edge of the second clock M-CLK. Further, the counter 133a stores a preset number, and if the number counted in the counter 133a is equal to the preset number, an output circuit corresponding to the preset number among the output circuits 1301 to 1306 may be selected.

When the counter 133a is not used, the level shifter 130a needs a memory to store information about the output circuit to be selected. However, since the level shifter 130a uses the counter 133a, the memory may not be used, and manufacturing cost may be reduced.

In addition, when the level shifter 130a receives the sensing mode signal CSP, the sensing clock may be output from the selected output circuit among the plurality of output circuits 1301 to 1306.

8 is a timing diagram showing waveforms of signals input / output to the level shifter.

Referring to FIG. 8, the level shifter 130a may receive the first clock G-CLK and the second clock M-CLK in the display mode TD. The first clock (G-CLK) and the second clock (M-CLK) may be pulse signals having a constant period and a phase difference of 180 degrees. However, the present invention is not limited thereto, and the first clock (G-CLK) and the second clock (M-CLK) may be supplied in different types of waveforms corresponding to the display mode, the line selection mode, and the sensing mode. The level shifter 130a may receive the first clock (G-CLK) and the second clock (M-CLK) and sequentially output a plurality of scan clocks (SCCLK1 to SCCLK6). In the level shifter 130a, the first clock (G-CLK) causes the rising edge of the first scan clock (SCCLK1) to correspond to the first rising edge, and the second clock (M-CLK) corresponds to the first falling edge of the first scan clock. The falling edge of (SCCLK1) can be made to correspond. And, the second scan clock (SCCLK2) is the first clock (G-CLK) is the second rising edge of the second scan clock (SCCLK2) corresponding to the second rising edge and the second clock (M-CLK) is the second falling edge The falling edge of the second scan clock SCCLK2 can be made to correspond. In this way, the third to sixth scan clocks SSCLK3 to SSCLK6 may also be generated so that a plurality of scan clocks SSCLK1 to SSCLK6 are sequentially generated.

In the line selection mode TLS, the level shifter 130a may receive the first clock G-CLK, the second clock M-CLK, and the line selection signal Mute. When the level shifter 130a receives the line selection signal Mute, an operation of generating a plurality of scan clocks SCCLK1 to SCCLK6 using the first clock G-CLK and the second clock M-CLK is performed. You can stop. Also, the level shifter 130a may count the first clock (G-CLK) and / or the second clock (M-CLK). The level shifter 130a can be counted using the counter 133a. In addition, the level shifter 130a may select one of the plurality of output circuits 1301 to 1306 corresponding to the number counted by the counter 133a. The timing controller 140 may determine and supply the number of the first clock (G-CLK) and / or the second clock (M-CLK) in the line selection mode (TLS). The counter 133a counts the number of first clocks (G-CLK) and / or second clocks (M-CLK) in the line selection mode (TLS) and corresponds to a counted number of output circuits 1301 to 1306).

That is, when the first controller G-CLK and / or the second clock M-CLK occurs in the line selection mode TLS, the timing controller 140 counts the number of counters 133a. It becomes 1, and the second output circuit 1322 of the plurality of output circuits 1301 to 1306 is selected. In addition, when the first controller G-CLK and / or the second clock M-CLK are generated in the line selection mode TLS, the timing controller 140 counts in the counter 133a. It becomes 3, and the fourth output circuit 1324 among the plurality of output circuits 1301 to 1306 may be selected. Also, when the number counted by the counter 133a becomes 6, the first output circuit 1321 may be selected from among the plurality of output circuits 1301 to 1306. However, the method of selecting the output circuit in response to the counted number is not limited thereto. Here, a description will be given using a case in which the number of counts of the first clock (G-CLK) and / or the second clock (M-CLK) by the counter 133a is three.

In addition, in the sensing mode TS, the level shifter 130a may receive the first clock G-CLK, the second clock M-CLK, and the sensing mode signal CSP. Waveforms of the first clock (G-CLK) and the second clock (M-CLK) received from the level shifter 130a are the first clock (G-CLK) and the second clock (M) received in the display mode (TD). -CLK). However, it is not limited thereto. When the number counted by the counter 133a is 3, the level shifter 130a may activate the fourth output circuit 1324 in the sensing mode and output the sensing clock SSCLK through the fourth output circuit 1324. When the fourth output circuit 1324 is activated and the first first clock (G-CLK) rises after the sensing mode signal (CSP) is input, the signal output from the fourth output circuit (1324) rises and the first second clock When (M-CLK) descends, the signal output to the fourth output circuit 1324 falls, so that the sensing clock SSCLK may be output from the fourth output circuit 1324. In addition, the fourth output circuit 1324 is activated even when the second first clock (G-CLK) and the second clock (M-CLK) are input, so the fourth output circuit when the second first clock (G-CLK) rises. The sensing clock SSCLK may be output by descending when the signal output from 1324 rises again and the second second clock descends. Here, the sensing clock SSCLK may be a signal corresponding to the gate signal and may be supplied to the gate electrode of the second transistor M2 of the subpixel shown in FIG. 2 in the sensing mode TS. In the sensing mode TS, a characteristic value of a subpixel may be sensed.

9 is a structural diagram showing an embodiment of a gate signal output circuit.

Referring to FIG. 9, the gate signal output circuit 130b includes a plurality of signal output circuits. Here, for convenience of description, only two signal output circuits of the fourth signal output circuit 131b and the fifth signal output circuit 132b are shown among the plurality of signal output circuits.

The fourth signal output circuit 131b includes a fourth carrier signal output unit 1311 outputting a fourth carrier signal carry4, a fourth gate signal output unit 1312 outputting a fourth gate signal GATE4, A fourth sensing control signal output unit 1313 may be output to output the four sensing control signals Ssen4. In addition, the fourth signal output circuit 131b may further include a fourth signal processing unit 1314.

The fifth signal output circuit 132b includes a fifth carrier signal output unit 1321 for outputting a fifth carry signal, and a fifth gate signal output unit 1322 for outputting a fifth gate signal GATE5. A fifth sensing control signal output unit 1323 may output a fifth sensing control signal Ssen5. Also, the fifth signal output circuit 132b may further include a fifth signal processing unit 1324.

  Here, the fourth signal processing unit 1314 receives the third carrier signal (carry3) from the third carrier signal output unit (not shown) and the fifth carrier signal output unit 1321 is a fifth signal processing unit not shown Signal (carry5) can be transmitted. The gate signal output circuit 130b may operate in response to the display mode TD and the sensing mode TS. In response to the display mode TD and the sensing mode TS, the fourth gate signal output unit 1312 and the fifth gate signal output unit 1322 output the gate signal (GATE) signal shown in FIGS. 3A to 3C. The fourth sensing control signal output unit 1313 and the fifth sensing control signal output unit 1323 may output the sensing control signal Ssen shown in FIGS. 3A to 3C.

First, the operation in the display mode TD will be described. In the display mode TD, the fourth carrier signal output unit 1311, the fourth gate signal output unit 1312, and the fourth sensing control signal output unit 1313 receive a fourth scan clock (SCCLK4) and receive a fifth carrier. The signal output unit 1321, the fifth gate signal output unit 1322, and the fifth sensing control signal output units 1313 and 1323 may receive the fifth scan clock SCCLK5. In addition, the fourth signal processing unit 1314 and the fifth signal processing unit 1324 may receive a charging signal (LSP). The charging signal LSP may be received from the timing controller 140. However, it is not limited thereto.

When the fourth signal processing unit 1314 receives the charging signal LSP and the third carry signal carry3, the fourth carrier signal output unit 1311 may be activated. In addition, the fourth gate signal output unit 1312 and the fourth sensing control signal output unit 1313 may be activated by the charging signal LSP. In addition, when the fifth signal processing unit 1324 receives the charging signal LSP and the fourth carry signal 4ry, the fifth carrier signal output unit 1321 may be activated. In addition, the fifth gate signal output unit 1322 and the fifth sensing control signal output units 1313 and 1323 may be activated by the charging signal LSP.

In addition, when the third carry signal (carry3) is transmitted to the fourth signal processing unit 1314 while the charging signal LSP is transmitted to the fourth signal processing unit 1314 and the fifth signal processing unit 1324, the fourth carry signal The output unit 1311, the fourth gate signal output unit 1312, and the fourth sensing control signal output unit 1313 are activated to activate a fourth carry signal, a fourth gate signal GATE4, and a fourth sensing control signal. When (Ssen4) can be output and the fourth carry signal (carry4) is transmitted to the fifth signal processing unit 1324, the fifth carry signal output unit 1321, the fifth gate signal output unit 1322, and the fifth sensing control The signal output units 1313 and 1323 are activated to output a fifth carry signal, a fifth gate signal GATE5, and a fifth sensing control signal Ssen5.

The second transistor M2 shown in FIG. 2 may be turned on by the gate signals GATE4 and GATE5, and the third transistor M3 may be turned on by the sensing control signals Ssen4 and Ssen5. Here, the fourth signal processing unit 1314 is illustrated as receiving the carry signal carry3 from a previous signal output circuit (not shown), but is not limited thereto. In addition, the fifth carry signal output unit 1321 is described as outputting a carry signal (carry 5) to the next signal output circuit (not shown), but is not limited thereto.

Then, the operation in the sensing mode (TS) will be described. In the sensing mode TS, the fourth carrier signal output unit 1311, the fourth gate signal output unit 1312, and the fourth sensing control signal output unit 1313 receive the sensing clock SSCLK and output the fifth carrier signal. The unit 1321, the fifth gate signal output unit 1322, and the fifth sensing control signal output units 1313 and 1323 do not receive the sensing clock SSCLK and the fifth scan clock SCCLK5. In addition, since the fourth carrier signal output unit 1311 and the fifth carrier signal output unit 1321 are not activated, the fourth carrier signal carry4 and the fifth carrier signal carry5 are not generated.

In addition, the fourth signal processing unit 1314 and the fifth signal processing unit 1324 may receive the charging signal LSP. When the fourth gate signal output unit 1312 receives the sensing clock SSCLK while the fourth signal processing unit 1314 receives the charging signal LSP, the fourth gate signal output unit 1312 receives the sensing clock SSCLK. ) May output a gate signal.

Here, the gate signals (GATE4, GATE5) and the sensing control signals (Ssen4, Ssen5) output from the gate signal output units (1312, 1322) and the sensing control signal output units (1313, 1323) are associated with scan clocks (SCCLK4, SCCLK5). GATE1, GATE2,… with the same period and phase , GATEn-1, GATEn. However, the present invention is not limited thereto, and the frequencies of the gate signals GATE4, GATE5 and the sensing control signals Ssen4, Ssen5, respectively, in the gate signal output units 1312, 1322 and the sensing control signal output units 1313, 1323, respectively. And the phase may be output differently.

10 is a flowchart illustrating an embodiment of a method of driving an organic light emitting display device according to the present invention.

Referring to FIG. 10, in the driving method of the organic light emitting display device, gate signals corresponding to the first clock (G-CLK) and the second clock (M-CLK) are sequentially applied to the plurality of gate lines GL1, ..., GLn. The display mode supplied by may be performed (S100). In the display mode, the timing controller 140 shown in FIG. 1 may output a first clock (G-CLK), a second clock (M-CLK), and an image signal (RGB). In the display mode, the data driver 120 may receive an image signal from the timing controller 140 and supply a data signal corresponding to the image signal RGB to the data lines DL1, ..., DLm. In addition, the gate driver 130 may receive the first clock (G-CLK) and the second clock (M-CLK) to generate a gate signal. When the gate signal is supplied in the display mode, the data signal supplied to the data lines DL1, ..., DLm may be supplied to the subpixel 101. The gate driver 130 may include a level shifter 130a and may boost gate voltages of signals received from the timing controller 140 to a predetermined voltage by the level shifter 130a to generate gate signals. .

The gate driver 130 may include a gate signal output circuit 130b and receive scan clocks SCCLK1 to SCCLK6 output from the level shifter 130a to generate gate signals and supply them to the gate line. . The display mode may be performed in a display section among one frame section divided into a display section and a blank section.

Then, a line selection mode may be performed (S110). In the line selection mode, gate lines GL1, ..., and GLn to which gate signals GATEs corresponding to the sensing clock SSCLK are transmitted may be selected from among the plurality of gate lines. Therefore, the sensing time can be shortened. In the line selection mode, the level shifter 130a counts the first clock (G-CLK) and / or the second clock (M-CLK) in response to the line selection signal and senses among the plurality of gate lines in response to the counted number. Since the time for performing the sensing mode for selecting the gate line to receive the clock SSCLK can be set short, it can be performed in a blank section of one frame period. For this reason, the sub-pixel performing the sensing mode may be a sub-pixel of a part of the display panel. The timing controller may determine the number of clocks of the first clock (G-CLK) and / or the second clock (M-CLK) to be transmitted in the line selection mode corresponding to the gate line to receive the sensing clock. In addition, the timing controller determines the first clock (G-CLK) and / or the second clock (M-CLK) according to the determined number of the first clock (G-CLK) and / or the second clock (M-CLK). Can occur. That is, the timing controller may cause one or six first clocks (G-CLK) and / or second clocks (M-CLK) to be generated in the line selection mode. Here, the number of the first clock (G-CLK) and / or the second clock (M-CLK) is exemplary and is not limited thereto.

Therefore, before performing the sensing mode, it is necessary to select a subpixel to be supplied with the sensing control signal in the sensing mode, and in the line selection mode, the gate line to which the sensing control signal is supplied can be selected. In order to select the gate line, at least one of the first clock and the second clock may be counted at the counter and the gate line may be selected according to the counted number. Selecting the gate line selects the output stage of the level shifter and then activates some of the gate output circuits among the plurality of gate output circuits.

Then, a sensing mode may be performed (S120). In the sensing mode, a characteristic value of a subpixel can be sensed. In the sensing mode, the sensing clock SSCLK corresponding to the first clock G-CLK and the second clock M-CLK may be supplied to the gate line selected in the line selection mode. In the sensing mode, a gate signal corresponding to the sensing clock SSCLK may be transmitted to the second transistor M2 of the subpixel through the gate line. In the sensing mode, a sensing voltage corresponding to the sensing data may be transmitted to the data line.

The above description and the accompanying drawings are merely illustrative of the technical spirit of the present invention, and those of ordinary skill in the art to which the present invention pertains combine combinations in a range that does not depart from the essential characteristics of the present invention. , Various modifications and variations such as separation, substitution and change will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

100: organic light emitting display device
101: subpixel
110: display panel
120: gate driver
130: data driver
140: timing controller

Claims (12)

An input unit that receives the first clock and the second clock;
An output unit including a plurality of output circuits respectively outputting scan clocks corresponding to the first clock and the second clock; And
A gate driver including a counter for counting at least one of the first clock and the second clock.
According to claim 1,
It operates in response to the display mode, line selection mode and sensing mode.
In the line selection mode, the counter counts a preset number and selects one of the plurality of output circuits in correspondence to the counted number. In the sensing mode, the first clock is selected as the output circuit selected in the line selection mode. A gate driver that outputs a sensing clock corresponding to the second clock.
According to claim 1,
The plurality of output terminals are gate drivers that output the plurality of scan clocks in response to the first clock and the second clock in the display mode.
According to claim 1,
Each of the plurality of output terminals is a gate driver connected to a gate signal output circuit that outputs a gate signal.
Display panel;
A gate driver including a level shifter that supplies a gate signal to the display panel and outputs a plurality of clock signals, and a gate signal output circuit that receives the plurality of clock signals and supplies the gate signal to the display panel;
A data driver supplying a data signal to the display panel; And
It includes a timing controller for controlling the gate driver and the data driver,
The level shifter,
An input unit receiving the first clock and the second clock from the timing controller;
An output unit including a plurality of output circuits outputting a plurality of scan clocks corresponding to the first clock and the second clock to the gate signal output circuit; And
And a counter for counting at least one of the first clock and the second clock.
The method of claim 5,
The level shifter operates in response to a display mode, a line selection mode and a sensing mode,
In the line selection mode, after the counter counts a preset number, one of the plurality of signal output units is selected according to the counted number, and the first clock is selected from the sensing mode to the signal output terminal selected in the line selection mode. And an organic light emitting display device outputting a sensing clock corresponding to the second clock.
The method of claim 5,
The plurality of output stages in the display mode, the organic light emitting display device for outputting the plurality of scan clock corresponding to the first clock and the second clock.
The method of claim 5,
The gate signal output circuit further outputs a carry signal and a sensing control signal, but receives the plurality of scan clocks and outputs the gate signal, the carry signal, and the sensing control signal.
The method of claim 8,
The gate signal output circuit includes a plurality of stages respectively outputting the gate signal, the carry signal, and the sensing control signal, wherein the plurality of stages sequentially operate by the carry signal.
The method of claim 5,
The display panel includes a plurality of sub-pixels,
The subpixel includes a data line supplying the data signal, a gate line supplying the gate signal, a first power line supplying a high potential voltage to the subpixel, and an initialization supplying an initialization voltage to the subpixel. Connected to the voltage line,
The sub-pixel is an organic light emitting display device for sensing the characteristic value of the sub-pixel through the initialization voltage line in the sensing mode.
A display mode for sequentially supplying gate signals corresponding to the first clock and the second clock to the plurality of gate lines;
A line selection mode for selecting at least one of the first clock and the second clock in response to the line selection signal and selecting a gate line to receive a sensing clock among the plurality of gate lines in correspondence to the counted number; And
And a sensing mode for supplying the sensing clock corresponding to the first clock and the second clock to the gate line selected in the line selection mode.
The method of claim 12,
A method of driving an organic light emitting display device in which the number of the first clock and the second clock in the line selection mode is determined corresponding to a gate line to receive the sensing clock.

Images