KR20190134011A - Solar cell including a tunnel oxide layer and method of manufacturing the same - Google Patents

Abstract

A manufacturing method of a photovoltaic cell including a tunnel oxide film of the present invention comprises the steps of: preparing a silicon substrate of a first conductivity type; forming an emitter layer of a second conductivity type on an upper surface of the silicon substrate; forming a tunneling oxide layer on a lower surface of the silicon substrate; annealing the tunneling oxide layer and performing an ozone post-treatment process to form a tunnel oxide film; forming a doped polycrystalline silicon layer on a lower surface of the tunnel oxide film; forming a first electrode on a lower surface of the doped polycrystalline silicon layer; and forming a second electrode in electrical connection with the emitter layer. The generating efficiency of a photovoltaic cell is increased.

Description

SOLAR CELL INCLUDING A TUNNEL OXIDE LAYER AND METHOD OF MANUFACTURING THE SAME

The present invention relates to a solar cell, and more particularly, to a solar cell comprising a tunnel oxide film and a method of manufacturing the same.

Silicon solar cells have a p-n junction. When light is irradiated onto the p-n junction surface, electrons and holes are generated, and the electrons and holes move to p and n regions. At this time, a potential difference (electromotive force) is generated between the p region and the n region, and a current flows when the load is connected to the solar cell.

Silicon solar cells are classified into crystalline, amorphous, and compound types according to the type of material used, and crystalline silicon solar cells are classified into monocrystalline and polycrystalline forms. Single crystal silicon solar cells are easy to achieve high efficiency because of the high quality of the substrate, but has a disadvantage in that the manufacturing cost of the substrate is large. On the other hand, polycrystalline silicon solar cells have a disadvantage in that high efficiency is difficult because the quality of the substrate is relatively poor compared to monocrystalline silicon solar cells. Recently, high efficiency has been promoted through the development of process technology.

The present invention is to provide a solar cell and a method of manufacturing the same that the power generation efficiency is increased.

The present invention has been made in an effort to provide a solar cell and a method of manufacturing the same, which reduce defects of silicon oxide (sub-oxide state).

The method for manufacturing a solar cell including the tunnel oxide film of the present invention includes preparing a silicon substrate of a first conductive phase type, forming an emitter layer of a second conductivity type on an upper surface of the silicon substrate, and Forming a tunneling oxide layer on a bottom surface of the substrate, annealing the tunneling oxide layer, and performing an ozone post-treatment process to form a tunnel oxide film, and forming a doped polycrystalline silicon layer on the bottom surface of the tunnel oxide film; Forming a first electrode on a lower surface of the doped polycrystalline silicon layer, and forming a second electrode electrically connected to the emitter layer.

A method of manufacturing a solar cell including the tunnel oxide film of the present invention includes forming a passivation film on the emitter layer, and forming an anti-reflection film on the emitter layer.

In the method of manufacturing a solar cell including the tunnel oxide film of the present invention, in the forming of the tunneling oxide layer, the tunneling oxide layer is formed to have a thickness of 1 nm to 2 nm using nitric acid.

In the method of manufacturing a solar cell including the tunnel oxide film of the present invention, the tunneling oxide layer may be subjected to an ozone post-treatment process at a temperature of 300 ° C. to 600 ° C., and an ozone concentration may be performed at 1 to 25 wt%.

In the method of manufacturing a solar cell including the tunnel oxide film of the present invention, the composition of SiOx at the interface between the silicon substrate and the tunnel oxide film is formed closer to the silicon oxide layer (SiO ₂ ) than to silicon (Si).

In the method for manufacturing a solar cell including the tunnel oxide film of the present invention, the first conductivity type may be an n-type conductivity type, and the second conductivity type may be a p-type conductivity type.

In the method of manufacturing a solar cell including the tunnel oxide layer of the present invention, the aluminum metal layer may be deposited to a thickness of 200 nm to 15 μm, and the doped amorphous silicon layer may be deposited to a thickness of 10 nm to 500 nm.

The solar cell including the tunnel oxide film of the present invention comprises a silicon substrate of a first conductive phase type, an emitter layer of a second conductivity type disposed on an upper surface of the silicon substrate, and a lower surface of the silicon substrate. A tunnel oxide film having a thickness of 2 nm, a doped polycrystalline silicon layer disposed on a lower surface of the tunnel oxide film, a first electrode disposed on a lower surface of the doped polycrystalline silicon layer, and a second electrode electrically connected to the emitter layer. do. The composition of SiOx at the interface between the silicon substrate and the tunnel oxide film is formed closer to the silicon oxide layer (SiO ₂ ) than to silicon (Si).

The solar cell including the tunnel oxide film of the present invention further includes a passivation film and an antireflection film disposed on the emitter layer.

In the solar cell including the tunnel oxide film of the present invention, the first conductivity type may be an n-type conductivity type, and the second conductivity type may be a p-type conductivity type.

In the solar cell including the tunnel oxide film of the present invention, the doped polycrystalline silicon layer is formed to a thickness of 10nm to 500nm. The first electrode is formed to a thickness of 200nm to 15㎛.

The present invention can provide a solar cell and a method of manufacturing the same that the power generation efficiency is increased.

The present invention can provide a solar cell and a method for manufacturing the same, wherein defects of silicon oxide films (reduced sub-oxide state) are reduced.

The present invention can increase the open-circuit voltage (Voc) by about 10mV, it is possible to improve the power generation efficiency of the solar cell.

1 is a view showing a solar cell including a tunnel oxide film according to an embodiment of the present invention.
2 is a view showing a method of manufacturing a solar cell including a tunnel oxide film according to an embodiment of the present invention.
3A and 3B show a method of forming a tunnel oxide film.
4A and 4B illustrate a method of forming a doped polycrystalline silicon layer.
5A and 5B illustrate a method of forming a first electrode.

Hereinafter, with reference to the accompanying drawings, a solar cell including a tunnel oxide film and a method for manufacturing the same according to embodiments of the present invention will be described in detail.

1 is a view showing a solar cell including a tunnel oxide film according to an embodiment of the present invention.

Referring to FIG. 1, a solar cell 100 including a tunnel oxide layer according to an exemplary embodiment of the present invention may include a silicon substrate 110, an emitter layer 120, a tunnel oxide layer 130, a doped polycrystalline silicon layer 140, The first electrode 150, the passivation layer 160, the anti-reflection coating 170, and anti-reflection coating (ARC) and the second electrode 180 may be included.

The silicon substrate 110 is a base substrate of a solar cell, and is a semiconductor substrate doped with impurities of a first conductivity type, for example, an n-type conductivity. When the silicon substrate 110 has an n-type conductivity type, the silicon substrate 110 may include impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb). A fine texturing structure or uneven structure (not shown) may be formed on the front surface of the silicon substrate 110 through wet etching such as acid etching to reduce reflectance.

The emitter layer 120 may be disposed on a front surface of the silicon substrate 110 to which light is incident. The emitter layer 120 may be doped with impurities of a second conductivity type, for example, a p-type conductivity.

When the emitter layer 120 has a p-type conductivity type, the emitter layer 120 may include impurities of trivalent elements such as boron (B), gallium (Ga), and indium (In). The emitter layer 120 may be formed to have a predetermined thickness by diffusing impurities of trivalent elements such as boron (B), gallium (Ga), and indium (In) on the silicon substrate 110.

The p-n junction may be formed by the silicon substrate 110 and the emitter layer 120. P-n junctions can cause built-in potential differences. Electron-hole pairs, which are charges generated by light incident on the silicon substrate 110, may be separated into electrons and holes, electrons may move toward n-type, and holes may move toward p-type. Therefore, when the silicon substrate 110 is n-type and the emitter layer 120 is p-type, the separated electrons may move toward the silicon substrate 110 and the separated holes may move toward the emitter layer 120.

The tunnel oxide layer 130 may be disposed on a rear surface of the silicon substrate 110. The tunnel oxide layer 130 may be formed by oxidizing a lower surface of the silicon substrate 110 to form a tunneling oxide layer having a predetermined thickness (for example, 1 nm to 3 nm), and then performing an annealing process and an ozone post-treatment process. The ozone aftertreatment process may be performed at a temperature of 300 ° C. to 600 ° C., and process time and ozone concentration may be adjusted so that the thickness is not increased much. When the tunnel oxide layer 130 is formed, when the process temperature is less than 300 ° C., the tunneling oxide layer may not be uniformly formed. On the contrary, when the tunnel oxide layer 130 is formed, when the process temperature exceeds 600 ° C., the thickness of the tunneling oxide layer may be thick, resulting in a thick tunnel oxide layer 130.

The oxidizing agent may include oxygen gas or nitric acid containing oxygen, and ozone used as a post-treatment oxidizing agent may lower active process temperature because of active oxygen, and may form a uniform tunnel oxide film 130. When forming the tunnel oxide film 130, the ozone concentration may be applied in the range of 1 to 25wt%. The tunnel oxide layer 130 may be disposed on the bottom surface of the silicon substrate 110 to pass electrons and block holes to increase separation efficiency of electrons and holes. In addition, the tunnel oxide layer 130 may stabilize the surface of the silicon substrate 110 by reducing dangling bonds existing on the surface of the silicon substrate 110. A portion of the silicon substrate 110 except for the lower surface may be masked to form the tunnel oxide layer 130.

Specifically, the tunneling oxide layer may be formed to have a thickness of about 1 nm to 2 nm using nitric acid, and an ozone aftertreatment process may be performed in a chamber. Through this, the composition of SiOx at the interface between the silicon substrate 110 and the silicon oxide layer (SiO2) is formed closer to the silicon oxide layer (SiO ₂ ), thereby reducing defects (reducing the sub-oxide state) of the silicon oxide layer. That is, through the ozone post-treatment, the composition of SiOx at the interface between the silicon substrate 110 and the tunnel oxide film 130 is formed closer to the silicon oxide layer (SiO ₂ ) than the silicon (Si), so that the defect of the tunnel oxide film 130 is reduced. This reduction can increase the open-circuit voltage (Voc) by about 10mV, resulting in improved solar cell power generation efficiency.

If the thickness of the tunnel oxide layer 130 is less than 1 nm, the surface passivation effect may be lowered, thereby reducing the effect of separating electrons and holes. On the contrary, when the thickness of the tunnel oxide film 130 exceeds 2 nm, tunneling of electrons is reduced, and the tunnel oxide film 130 may function as an insulating film.

The doped polycrystalline silicon layer 140 may be disposed on the bottom surface of the tunnel oxide layer 130. The doped polycrystalline silicon layer 140 may be formed by depositing a doped amorphous silicon layer doped with a second conductivity type on the lower portion of the tunnel oxide layer 130 and performing an annealing process. Here, the doped amorphous silicon layer may be annealed together with the aluminum metal layer deposited to form the first electrode 150 to form the doped polycrystalline silicon layer 140. The doped polycrystalline silicon layer 140 may include an n-type conductivity type impurity. For example, pentavalent elements such as phosphorus (P), As, and Sb may be used as impurities.

The doped amorphous silicon layer may be formed to a thickness of 10nm to 500nm. If the thickness of the doped amorphous silicon layer is less than 10 nm, the thickness of the doped polycrystalline silicon layer 140 may become thin and may not sufficiently serve as an electrode. In addition, when the thickness of the doped amorphous silicon layer exceeds 500nm, a lot of process time may be consumed. As such, the silicon substrate 110 and the doped polycrystalline silicon layer 140 are formed with the tunnel oxide layer 130 interposed therebetween. Accordingly, the tunnel oxide film 130 and the doped polycrystalline silicon layer 140 formed on the bottom surface of the n-type conductive silicon substrate 110 can increase the generation efficiency of the solar cell by separating electrons and holes and preventing recombination. have.

The first electrode 150 may be disposed on the bottom surface of the doped polycrystalline silicon layer 140. After depositing an aluminum metal layer under the tunnel oxide layer 130, the first electrode 150 may be formed by performing an annealing process. The first electrode 150 may further include a conductive metal such as silver (Ag) in addition to aluminum. After the aluminum metal layer is deposited to a thickness of 200 nm to 15 μm, the first electrode 150 may be formed by performing an annealing process. If the thickness of the aluminum metal layer is less than 200 nm, the thickness of the first electrode 150 becomes thin, thereby increasing the electrical resistance. On the contrary, when the thickness of the aluminum metal layer exceeds 15 µm, there is a problem that the consumption of aluminum material is unnecessarily increased and the manufacturing cost is increased.

As such, the doped polycrystalline silicon layer 140 and the first electrode 150 may be formed so that the tunnel oxide film 130, the doped polycrystalline silicon layer 140, and the first electrode 150 may improve adhesion. The doped polycrystalline silicon layer 140 and the first electrode 150 may be directly electrically connected to reduce electrical resistance of the solar cell and to improve power generation efficiency.

The passivation layer 160 may have a thickness of about 1 nm to about 50 nm, and may be disposed on an upper surface of the emitter layer 120. The passivation layer 160 may be formed by depositing aluminum oxide (Al ₂ O ₃ ) by atomic layer deposition or plasma enhanced CVD.

The anti-reflection film 170 may be disposed on the passivation film 160. The anti-reflection film 170 may have a structure in which insulating films such as a SiNx: H film and a SiON film are stacked in a single layer or a plurality of layers. The SiNx: H antireflection film may be formed by a plasma enhanced chemical vapor deposition (PECVD) method while supplying a source gas for forming a SiNx film. The SiON anti-reflection film may be formed by an ICP PECVD method while supplying a source gas and an N 2 O gas for forming a SiNx film. The SiNx film may be formed in a range of 100 nm to 180 nm, and the SiON film may be formed in a range of 80 nm to 130 nm.

In FIG. 1, the anti-reflection film 170 is disposed on the upper surface of the passivation film 160, but the present invention is not limited thereto. The anti-reflection film 170 is disposed on the upper surface of the emitter layer 120, and the anti-reflection film 170 is disposed on the upper surface of the passivation film 160. The passivation film 160 may be disposed on the upper surface.

The second electrode 180 may be disposed to be electrically connected to the emitter layer 120 by using a portion where the passivation film 160 and the anti-reflection film 170 are not formed. Alternatively, the second electrode 180 may be disposed to be electrically connected to the emitter layer 120 by etching part of the passivation film 160 and the anti-reflection film 170. The second electrode 180 is made of aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au). And at least one conductive material selected from the group consisting of a combination thereof. The second electrode 180 may be formed by a chemical vapor deposition process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD), a paste coating process such as sputtering, plating, or screen printing. The second electrode 180 may be formed of a plurality of electrodes extending side by side in a predetermined direction. The second electrode 180 may collect charge, for example, holes moved toward the emitter layer 120.

The second electrode 180 may be made of a conductive paste. The second electrode 180 may be formed by applying a conductive paste to the emitter layer 120 exposed by the passivation film 160 and the anti-reflection film 170. The conductive paste may be made of a material containing silver (Ag) or aluminum (Al). In addition, the second electrode 180 may be formed using a conductive paste capable of low temperature baking. When the second electrode 180 is formed of a conductive paste capable of low temperature firing, since the second electrode 180 exhibits excellent electrical conductivity as compared with the case of being formed of a conductive paste that is baked at a high temperature, the charge collection efficiency can be improved.

Although not illustrated, a plurality of current collectors may be positioned on the second electrode 180 in a direction crossing the second electrode 180, and the current collector and the second electrode 180 may be electrically and physically connected to each other. have.

2 is a view showing a method of manufacturing a solar cell including a tunnel oxide film according to an embodiment of the present invention.

1 and 2, in a method of manufacturing a solar cell including a tunnel oxide film, forming an emitter layer 120 on an upper surface of a silicon substrate 110 (S10) and a lower surface of a silicon substrate 110. Forming a tunneling oxide layer (S20), performing ozone post-treatment on the tunneling oxide layer to finally form the tunnel oxide layer 120 (S30), and depositing a doped amorphous silicon layer on the bottom surface of the tunnel oxide layer 120 ( S40), performing a heat treatment on the doped amorphous silicon layer to form a doped polycrystalline (poly) silicon layer (S50), forming an aluminum metal layer on the bottom surface of the doped polycrystalline silicon layer (S60), and performing an annealing process Forming an electrode (S70), forming a passivation film 160 on the emitter layer 120 (S80), forming an anti-reflection film 170 on the passivation film 160 (S90), and Forming a second electrode 180 (S100). There.

Specifically, the emitter layer 120 may be formed on the upper surface of the silicon substrate 110 (S10).

The silicon substrate 110 is a base substrate of a solar cell, and may be doped with impurities of a first conductivity type, for example, an n-type conductivity. The silicon substrate 110 may include impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb). The front surface of the silicon substrate 110 may further include a process of forming a fine texturing structure or concave-convex structure through wet etching, such as acid etching, to reduce reflectance.

The emitter layer 120 may be disposed on a front surface of the silicon substrate 110 to which light is incident. The emitter layer 120 may be doped with impurities of a second conductivity type, for example, a p-type conductivity. When the emitter layer 120 has a p-type conductivity type, the emitter layer 120 may include impurities of trivalent elements such as boron (B), gallium (Ga), and indium (In). The emitter layer 120 may be formed to have a predetermined thickness by diffusing impurities of trivalent elements such as boron (B), gallium (Ga), and indium (In) on the silicon substrate 110.

The p-n junction may be formed by the silicon substrate 110 and the emitter layer 120. P-n junctions can cause built-in potential differences. Electron-hole pairs, which are charges generated by light incident on the silicon substrate 110, may be separated into electrons and holes, electrons may move toward n-type, and holes may move toward p-type. Therefore, when the silicon substrate 110 is n-type and the emitter layer 120 is p-type, the separated electrons may move toward the silicon substrate 110 and the separated holes may move toward the emitter layer 120.

3A and 3B show a method of forming a tunnel oxide film.

1, 2, 3A and 3B, a tunneling oxide layer 130a may be formed on the bottom surface of the silicon substrate 110 (S20).

A process temperature of 300 ° C. to 600 ° C. may be applied to the chamber, and the tunneling oxide layer 130a may be formed by supplying an oxidant into the chamber. In this case, when the process temperature is too low, the tunneling oxide layer 130a may be uneven or insufficiently formed. In addition, when the process temperature is too high, the thickness of the tunneling oxide layer 130a may be too thick.

Subsequently, ozone post-treatment may be performed on the tunneling oxide layer 130a in the chamber to form the final tunnel oxide layer 130 (S30).

The tunnel oxide layer 130 may be disposed on a rear surface of the silicon substrate 110. The tunnel oxide layer 130 may have a thickness of 1 nm to 2 nm, and may be formed by performing ozone post-treatment on the tunneling oxide layer 130a after the annealing process. The ozone aftertreatment process may be performed at a temperature of 300 ° C. to 600 ° C., and the process time and the ozone concentration may be adjusted so that the thickness of the tunnel oxide layer 130 is not increased. When the tunnel oxide film 130 is formed, the tunnel oxide film 130 may not be uniformly formed if the process temperature is less than 300 ° C. On the contrary, when the tunnel oxide film 130 is formed, the tunnel oxide film 130 may be thickened when the process temperature exceeds 600 ° C.

The oxidizing agent may include oxygen gas or nitric acid containing oxygen, and ozone used as a post-treatment oxidizing agent is active oxygen, thereby lowering the process temperature and forming a uniform tunnel oxide film 130. When forming the tunnel oxide film 130, the ozone concentration may be applied in the range of 1 to 25wt%. The tunnel oxide layer 130 may be disposed on the bottom surface of the silicon substrate 110 to pass electrons and block holes to increase separation efficiency of electrons and holes. In addition, the tunnel oxide layer 130 may stabilize the surface of the silicon substrate 110 by reducing dangling bonds existing on the surface of the silicon substrate 110. A portion of the silicon substrate 110 except for the lower surface may be masked to form the tunnel oxide layer 130.

As an example, a tunneling oxide layer may be formed to have a thickness of about 1 nm to 2 nm using nitric acid, and an ozone aftertreatment process may be performed in a chamber. This can be the composition of the interface SiOx silicon substrate 110 and the silicon oxide layer (SiO ₂₎ is reduced to a silicon oxide layer is formed to more of a (SiO ₂₎ (reducing the sub-oxide state) defects in the silicon oxide film . That is, through the ozone post-treatment, defects in the tunnel oxide film 130 may be reduced, thereby increasing the open-circuit voltage (Voc) by about 10 mV, and consequently, the power generation efficiency of the solar cell may be improved.

If the thickness of the tunnel oxide layer 130 is less than 1 nm, the surface passivation effect may be lowered, thereby reducing the effect of separating electrons and holes. On the contrary, when the thickness of the tunnel oxide film 130 exceeds 2 nm, tunneling of electrons is reduced, and the tunnel oxide film 130 may function as an insulating film.

4A and 4B illustrate a method of forming a doped polycrystalline silicon layer.

1, 2, 4A, and 4B, a doped amorphous silicon layer may be deposited on the bottom surface of the tunnel oxide layer 130 (S40).

The doped amorphous silicon layer 140a may be doped with a second conductivity type. The doped amorphous silicon layer 140a may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process. The doped amorphous silicon layer 140a may be formed by injecting pentavalent elements such as phosphorus (P), As, and Sb during deposition. The doped amorphous silicon layer 140a may be formed to a thickness of 10 nm to 500 nm.

Subsequently, the doped polycrystalline silicon layer 140 may be formed by performing heat treatment on the doped amorphous silicon layer 140a (S50).

The doped polycrystalline silicon layer 140 is formed of an n-type silicon layer by a pentavalent element injected during the deposition process. The annealing process may be carried out in the temperature range of 250 ℃ to 550 ℃.

5A and 5B illustrate a method of forming a first electrode.

2, 5A and 5B, an aluminum metal layer 150a may be formed on the bottom surface of the doped polycrystalline silicon layer S140 (S60).

The aluminum metal layer 150a may be formed of pure aluminum, and may further include a conductive metal such as silver (Ag). The aluminum metal layer 150a may be formed through a chemical vapor deposition process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD), or a sputtering process. The aluminum metal layer 150a may be formed by a vacuum deposition method in which aluminum is vacuum evaporated and coated. At this time, the aluminum metal layer 150a may be deposited to a thickness of 200 nm to 15 μm.

Subsequently, an annealing process may be performed to form the first electrode 150 on the bottom surface of the doped polycrystalline silicon layer 140 (S70).

By S40 to S70, the doped polycrystalline silicon layer 140 may be disposed on the bottom surface of the tunnel oxide layer 130. The first electrode 150 may be disposed on the bottom surface of the doped polycrystalline silicon layer 140.

The doped amorphous silicon layer may be formed to a thickness of 10nm to 500nm. If the thickness of the doped amorphous silicon layer is less than 10 nm, the thickness of the doped polycrystalline silicon layer 140 may become thin and may not sufficiently serve as an electrode. In addition, when the thickness of the doped amorphous silicon layer exceeds 500nm, a lot of process time may be consumed. As such, the silicon substrate 110 and the doped polycrystalline silicon layer 140 are formed with the tunnel oxide layer 130 interposed therebetween. Accordingly, the tunnel oxide film 130 and the doped polycrystalline silicon layer 140 formed on the bottom surface of the n-type conductive silicon substrate 110 can increase the generation efficiency of the solar cell by separating electrons and holes and preventing recombination. have.

The first electrode 150 may further include a conductive metal such as silver (Ag) in addition to aluminum. After the aluminum metal layer is deposited to a thickness of 200 nm to 15 μm, the first electrode 150 may be formed by performing an annealing process. If the thickness of the aluminum metal layer is less than 200 nm, the thickness of the first electrode 150 becomes thin, thereby increasing the electrical resistance. On the contrary, when the thickness of the aluminum metal layer exceeds 15 µm, there is a problem that the consumption of aluminum material is unnecessarily increased and the manufacturing cost is increased.

As such, the doped polycrystalline silicon layer 140 and the first electrode 150 may be formed so that the tunnel oxide film 130, the doped polycrystalline silicon layer 140, and the first electrode 150 may improve adhesion. The doped polycrystalline silicon layer 140 and the first electrode 150 may be directly electrically connected to reduce electrical resistance of the solar cell and to improve power generation efficiency.

Subsequently, the passivation film 160 may be formed on the upper surface of the emitter layer 120 (S80).

The passivation layer 160 may have a thickness of about 1 nm to about 50 nm, and may be disposed on an upper surface of the emitter layer 120. The passivation layer 160 may be formed by depositing aluminum oxide (Al 2 O 3) by atomic layer deposition or plasma enhanced CVD. The passivation layer 160 uses Al (OC 2 H 5) ₃ (Tri Methyl Aluminum; TMA) as a source, and uses water vapor (H ₂ O) or ozone (O ₃ ) as an oxygen source, and a process temperature of 100 ° C. to 450 ° C. Can be proceeded from.

Subsequently, an anti-reflection film 170 may be formed on the upper surface of the passivation film 160 (S90).

The anti-reflection film 170 may have a structure in which insulating films such as a SiNx: H film and a SiON film are stacked in a single layer or a plurality of layers. The SiNx: H antireflection film may be formed by a plasma enhanced chemical vapor deposition (PECVD) method while supplying a source gas for forming a SiNx film. The SiON anti-reflection film may be formed by an ICP PECVD method while supplying a source gas and an N 2 O gas for forming a SiNx film. The SiNx film may be formed in a range of 100 nm to 180 nm, and the SiON film may be formed in a range of 80 nm to 130 nm.

In FIGS. 1 and 2, the anti-reflection film 170 is formed on the upper surface of the passivation film 160. However, the anti-reflection film 170 is formed on the upper surface of the emitter layer 120 and the anti-reflection film is not limited thereto. The passivation layer 160 may be formed on the upper surface of the 170.

Subsequently, a second electrode 180 electrically connected to the emitter layer 120 may be formed (S100).

The second electrode 180 may be formed to be electrically connected to the emitter layer 120 by using a portion where the passivation film 160 and the anti-reflection film 170 are not formed. Alternatively, the second electrode 180 may be formed to be electrically connected to the emitter layer 120 by etching part of the passivation film 160 and the anti-reflection film 170. The second electrode 180 is made of aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au). And at least one conductive material selected from the group consisting of a combination thereof. The second electrode 180 may be formed by a chemical vapor deposition process such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD), a paste coating process such as sputtering, plating, or screen printing. The second electrode 180 may be formed of a plurality of electrodes extending side by side in a predetermined direction. The second electrode 180 may collect charge, for example, holes moved toward the emitter layer 120.

The second electrode 180 may be made of a conductive paste. The second electrode 180 may be formed by applying a conductive paste to the emitter layer 120 exposed by the passivation film 160 and the anti-reflection film 170. The conductive paste may be made of a material containing silver (Ag) or aluminum (Al). In addition, the second electrode 180 may be formed using a conductive paste capable of low temperature baking. When the second electrode 180 is formed of a conductive paste capable of low temperature firing, since the second electrode 180 exhibits excellent electrical conductivity as compared with the case of being formed of a conductive paste that is baked at a high temperature, the charge collection efficiency can be improved.

Although not illustrated, a plurality of current collectors may be positioned on the second electrode 180 in a direction crossing the second electrode 180, and the current collector and the second electrode 180 may be electrically and physically connected to each other. have.

The present invention can provide a solar cell and a method of manufacturing the same that the power generation efficiency is increased. The present invention can provide a solar cell and a method for manufacturing the same, wherein defects of silicon oxide films (reduced sub-oxide state) are reduced. The present invention can increase the open-circuit voltage (Voc) by about 10mV, it is possible to improve the power generation efficiency of the solar cell.

What has been described above is only one embodiment for carrying out the solar cell manufacturing method according to the present invention, the present invention is not limited to the above-described embodiment, the subject matter of the present invention as claimed in the following claims Without departing from the technical spirit of the present invention to the extent that any person of ordinary skill in the art to which the present invention pertains various modifications can be made.

100: solar cell including tunnel oxide film
110: silicon substrate 120: emitter layer
130: tunnel oxide film 140: doped polycrystalline silicon layer
140a: doped amorphous silicon layer 150: first electrode
150a: aluminum metal layer 160: passivation film
170: antireflection film 180: second electrode

Claims (11)

Preparing a silicon substrate of a first conductive phase type;
Forming an emitter layer of a second conductivity type on an upper surface of the silicon substrate;
Forming a tunneling oxide layer on a bottom surface of the silicon substrate;
Annealing the tunneling oxide layer and performing an ozone post-treatment process to form a tunnel oxide film;
Forming a doped polycrystalline silicon layer on a lower surface of the tunnel oxide film;
Forming a first electrode on a lower surface of the doped polycrystalline silicon layer; And
Forming a second electrode in electrical connection with the emitter layer;
A solar cell manufacturing method comprising a tunnel oxide film. The method of claim 1,
Forming a passivation film on the emitter layer; And
Forming an antireflection film on the emitter layer;
A solar cell manufacturing method comprising a tunnel oxide film. According to claim 1,
In the forming of the tunneling oxide layer,
Forming the tunneling oxide layer to a thickness of 1nm to 2nm using nitric acid,
A solar cell manufacturing method comprising a tunnel oxide film. The method of claim 3, wherein
Performing an ozone post-treatment process on the tunneling oxide layer at a temperature of 300 ℃ to 600 ℃, the ozone concentration is 1 ~ 25wt%,
A solar cell manufacturing method comprising a tunnel oxide film. The method of claim 4, wherein
Wherein the composition of SiOx at the interface between the silicon substrate and the tunnel oxide film is formed closer to the silicon oxide layer (SiO ₂ ) than to silicon (Si),
A solar cell manufacturing method comprising a tunnel oxide film. The method of claim 1,
The first conductivity type is an n-type conductivity type, and the second conductivity type is a p-type conductivity type,
A solar cell manufacturing method comprising a tunnel oxide film. According to claim 1,
The aluminum metal layer is deposited to a thickness of 200nm to 15㎛,
The doped amorphous silicon layer is deposited to a thickness of 10nm to 500nm,
A solar cell manufacturing method comprising a tunnel oxide film. A silicon substrate of a first conductive phase type;
An emitter layer of a second conductivity type disposed on an upper surface of the silicon substrate;
A tunnel oxide film disposed on a bottom surface of the silicon substrate and having a thickness of 1 nm to 2 nm;
A doped polycrystalline silicon layer disposed on a bottom surface of the tunnel oxide film;
A first electrode disposed on a bottom surface of the doped polycrystalline silicon layer;
A second electrode electrically connected to the emitter layer;
It is formed so that the composition of SiOx at the interface between the silicon substrate and the tunnel oxide film is closer to the silicon oxide layer (SiO ₂ ) than silicon (Si).
A solar cell comprising a tunnel oxide film. The method of claim 8,
Further comprising a passivation film and an anti-reflection film disposed on the emitter layer,
A solar cell comprising a tunnel oxide film. The method of claim 8,
The first conductivity type is an n-type conductivity type, and the second conductivity type is a p-type conductivity type,
A solar cell comprising a tunnel oxide film. The method of claim 8,
The doped polycrystalline silicon layer is formed to a thickness of 10nm to 500nm,
The first electrode is formed to a thickness of 200nm to 15㎛,
A solar cell comprising a tunnel oxide film.

Images