KR20190058281A - Memory device for supporting command bus training mode and operating method thereof - Google Patents

Abstract

A memory device and a method of operation supporting a command bus training (CBT) mode are disclosed. In response to the logic level of the first data signal, which is either one of the data signals in the CBT mode and one of the signals other than the second data signals outputting the CBT pattern in one-to-one correspondence with the command / address signals, (CBT) mode or exit the CBT mode. In the CBT mode, the memory device changes the reference voltage value according to a second reference voltage setting code received at the terminals of the second data signals, and changes the resistance value corresponding to the on-die termination (ODT) code setting stored in the mode register Terminates the command / address signals or the data clock signal pair, and turns off the ODT of the data signals.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory device supporting a command bus training mode,

The present invention relates to a semiconductor memory device, and more particularly, to a memory device supporting a command bus training mode and an operation method thereof.

BACKGROUND OF THE INVENTION Mobile-oriented memory devices such as low power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM), smart phone, tablet ) It is mainly used in mobile electronic devices such as PCs and ultrabooks. As the capacity of a mobile operating system (OS) increases to support multitasking operations performed in mobile electronic devices, mobile electronic devices with lower power consumption characteristics and high operating performance are desired.

For high-speed operation performance of the memory device, a high-speed clock signal may be provided at the interface between the memory device and the memory controller (or CPU (Central Processing Unit).) The memory device responds to the clock signal received from the memory controller, It is possible to process signals received from the controller and synchronize the signals transmitted to the memory controller with the clock signal. As the frequency of the clock signal provided by the memory controller increases according to the demand for a higher data transfer rate, It is becoming increasingly important to accurately capture the transmitted signals. Thus, the memory device employs a bus training technique.

It is an object of the present invention to provide a memory device and a method of operation that support a command bus training mode.

The memory device supporting the command bus training mode according to the embodiments of the present invention includes a data clock signal, command / address signals to which a command bus training (CBT) pattern is transmitted, a first In response to a first logic level of a first data signal synchronized with a data clock signal, and data signals comprising second data signals in which a command bus training pattern is output in a one-to-one correspondence with a data signal and command / And control logic to control the CBT mode to enter and exit the CBT mode in response to a second logic level opposite to the first logic level of the first data signal.

A method of operating a memory device supporting a command bus training (CBT) mode in accordance with embodiments of the present invention includes: receiving a data clock signal; responding to a first logic level of a first data signal synchronized to a data clock signal A command bus training (CBT) pattern composed of a bit configuration of command / address signals in the CBT mode, and an operation of entering the CBT mode in the CBT mode. And the first data signal is set to one of signals other than the second data signals among the data signals of the memory device in the CBT mode.

A memory system according to embodiments of the present invention includes a memory device that enters a command bus training (CBT) mode or escapes a CBT mode in response to a logic level of a first data signal; And a memory controller for transmitting a command bus training (CBT) pattern through terminals of command / address signals to the memory device, wherein the first data signal is one-to-one correspondence with command / address signals among the data signals of the memory device in the CBT mode Are set to any one of signals other than the second data signals corresponding to the CBT pattern. In the CBT mode, the memory device changes the reference voltage value according to a second reference voltage setting code received at the terminals of the second data signals, and changes the resistance value corresponding to the on-die termination (ODT) code setting stored in the mode register Terminates the command / address signals or the data clock signal pair, and turns off the ODT of the data signals.

The memory device performing the command bus training mode of the present invention can accurately capture the signal received through the command / address bus by improving the accuracy of the command bus training.

1 is a block diagram illustrating a memory system in accordance with an exemplary embodiment of the present invention.
2 is a block diagram illustrating the memory device of FIG.
3 is a timing diagram illustrating the command bus training operation of the memory device of FIG.
Figure 4 is a circuit diagram illustrating a portion of the control logic of Figure 2;
5A to 5C are diagrams for explaining the reference voltage setting circuit of FIG.
6 is a circuit diagram illustrating the data (DQ) output drive circuit of FIG.
7A to 7D are diagrams illustrating a command / address (CA) on-die termination (ODT) control circuit.
8A-8C are diagrams illustrating the data (DQ) on-die termination (ODT) control circuit of FIG.
FIGS. 9A to 9C are diagrams illustrating the data clock (WCK) on-die termination (ODT) control circuit of FIG.
10 is a block diagram illustrating an example of application of a memory system according to embodiments of the present invention to a mobile device.

1 is a block diagram illustrating a memory system in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 1, a memory system 1000 includes a memory device 100 and a memory controller 200. The memory system 1000 may be embodied in a personal computer (PC) or a mobile electronic device. The mobile electronic device can be used in a wide range of applications including laptop computers, mobile phones, smart phones, tablet PCs, PDAs (Personal Digital Assistants), EDA (Enterprise Digital Assistant), digital still cameras, digital video cameras, Portable Multimedia Player), PND (Personal Navigation Device or Portable Navigation Device), Handheld game console, Mobile Internet Device (MID), Wearable Computer, Internet of Things (IoT) Device, an Internet of Everything (IoE) device, or a drone.

The memory device 100 may include a memory cell array including a plurality of memory cells. In one embodiment, the memory cell may be a volatile memory cell and the memory device 100 may include, but is not limited to, a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, a double data rate (DDR SDRAM) Synchronous Dynamic Random Access Memory (LPDDR), SDRAM (Low Power DDR) SDRAM, Graphic DDR SDRAM, Rambus Dynamic Random Access Memory (RDRAM), and the like. In another embodiment, the memory cell may be a non-volatile memory cell, and the memory device 100 may include, but is not limited to, a non-volatile memory such as an Electrically Erasable Programmable Read-Only Memory (EEPROM) , A PRAM (Phase Change Random Access Memory), an RRAM (Resistance Random Access Memory), a Nano Floating Gate Memory (NFGM), a Polymer Random Access Memory (PoRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory . In the following, the memory device 100 will be described as being a DRAM, but it will be appreciated that the technical idea of the present disclosure is not limited thereto.

The memory controller 200 may be implemented as an application processor (AP), a mobile AP, a chipset, or a collection of chips. The memory controller 200 may include one or more processors including a single and / or multicore processor. According to an embodiment, the memory controller 200 may be implemented as a physical device separate from the package including the processor (s) and cache components. According to an embodiment, memory controller 200 may be part of a processor, e.g., a circuit of a processor. According to an embodiment, the memory controller 200 may be implemented in logic on a System On Chip (SOC) shared by a plurality of processor devices.

The signal lines between the memory controller 200 and the memory device 100 may be connected through connectors. The connectors may be implemented as pins, balls, signal lines, or other hardware components. Command and address (CA) signals may be transferred from the memory controller 200 to the memory device 100 via the command / address bus 11. A chip select (CS) signal may be transmitted from the memory controller 200 to the memory device 100 via the chip select line 13. The chip select (CS) signal that is logically hyro-activated may indicate that the command / address (CA) signal transmitted via the command / address bus 11 is a command. The data DQ may be transferred from the memory controller 200 to the memory device 100 or from the memory device 100 to the memory controller 200 via the data bus 17, have.

The data storage capacity of the memory device 100 increases and devices accessing the memory device 100 such as a central processing unit (CPU), a graphics processing unit (GPU), an IP core (intellectual) property core, etc., the memory device 100 can support a high-speed interface. The memory device 100 may receive a clock (CK) signal from the memory controller 200 through the clock line 15 and may receive signals from the memory controller 200 based on the received clock (CK) For example, a command / address (CA) signal, data DQ, and the like. The memory device 100 may also send the data DQ synchronized to the received clock (CK) signal to the memory controller 200 so that the memory controller 200 can capture the data DQ.

Although FIG. 1 shows an example in which a clock (CK) signal is transmitted through one clock line 15, a clock (CK) signal may be transmitted through two different signal lines differently. In the following, although the memory device 100 is described as operating in synchronization with the rising edge of a clock (CK) signal, according to exemplary embodiments of the present disclosure, the memory device 100 includes a clock (CK) And may be operated synchronously with the falling edge of the signal.

The memory device 100 and the memory controller 200 may support the bus training mode in order to capture the command / address (CA) signal, data DQ, based on the clock signal (CK) having a high frequency. That is, the memory controller 200 can perform bus training on the command bus 11 and / or the data bus 17 when power is supplied to the memory system 1000 or if certain conditions are satisfied. For example, the memory controller 200 may send a command to the memory device 100 via the command bus 11 to enter the bus training mode with a low frequency clock (CK) signal, Can enter the bus training mode. In the bus training mode, the memory controller 200 can send a specific signal to the memory device 100 via the training object signal line with a high frequency clock (CK) signal and receive a response from the memory device 100 . The memory controller 200 may determine the timing, e.g., delay, of a signal that is transmitted over the training object signal line based on the response received from the memory device 100. [

The data bus training is transmitted through the data bus 17 at the rising or falling edge of the data clock (WCK) signal after the memory controller 200 has transmitted a specific command through the command bus 11 and a certain time has elapsed May be performed by determining whether the data DQ has been accurately captured by the memory device 100. [

On the other hand, the command bus training can be performed before the data bus training is performed. The command bus training can be performed by determining whether a command / address (CA) signal transmitted through the command bus 11 at the rising or falling edge of the clock (CK) signal has been accurately captured by the memory device 100 . In addition, the chip selection (CS) signal (the timings of Ta1 and Ta2 in FIG. 3) indicating that the command / address (CA) signal is a command can have an active pulse width shorter than the period of the clock (CK) The command bus training may include using the activated chip select (CS) signal (Te1 point in FIG. 3).

As described above, the data bus training checks whether the data DQ is accurately captured at a particular rising or falling edge of the clock (CK) signal, while the command bus training can be performed before the data bus training and the clock (CA) signal is correctly captured at the unspecified rising edge of the CK signal. Accordingly, the command bus training may not be easier than the data bus training. In order to accurately capture the command / address (CA) signal during command bus training, the memory device 100 may include control logic 120 that controls the command bus training mode.

The control logic 120 enters the command bus training (CBT) mode using the logic level of the data (e.g., DQ [7], Figure 3) signal from which no command bus training pattern is output among the data (DQ) And escape. The control logic 120 controls to receive the CBT pattern through the terminals of the command / address (CA) signals and selects data (e.g., DQ [6: 0]) from which the command bus training pattern is output, , Fig. 3), and outputting the CBT pattern through the terminals of the signals.

2 is a block diagram illustrating the memory device of FIG.

2, memory device 100 includes a memory cell array 110, control logic 120, a reference voltage setting circuit 330, a command / address (CA) calibration circuit 340, a data DQ output (ODT) control circuit 360, a data (DQ) on-die termination (ODT) control circuit 370, and a data clock (WCK) on- And a die termination (ODT) control circuit 380.

The memory cell array 110 includes a plurality of memory cells arranged in rows and columns. The memory cell array 110 includes a plurality of word lines WL and a plurality of bit lines BL connected to memory cells. A plurality of word lines (WL) may be connected to rows of memory cells, and a plurality of bit lines (BL) may be connected to columns of memory cells.

The control logic 120 may include a clock signal (CK), a chip select (CS) signal, a command / address signal CA, a data clock (WCK) signal, a data DQ and / The CBT enable signal CBT_EN may be generated. The CBT enable signal CBT_EN is used as a driving signal of the CBT mode and includes a reference voltage setting circuit 330, a CA calibration circuit 340, a DQ output drive circuit 350, a CA ODT control circuit 360, a DQ ODT The control circuit 370, and the WCK ODT control circuit 380, respectively.

The mode register 320 may program the functions, features and / or modes of the memory device 100. The mode register 320 may be programmed by an MRS command in accordance with a command / address (CA) signal transmitted via the command / address bus 11 and may be programmed with user defined variables. The mode register 320 may be divided into various fields according to functions, characteristics, and / or modes. Since all the registers of the mode register 320 have defined default values, the contents of the mode register 310 can be initialized. That is, after power-up and / or reset for correct operation, the contents of mode register 320 can be programmed. Further, the contents of the mode register 320 may be changed due to re-execution of the MRS command during the normal operation. Accordingly, the functions, characteristics and / or modes of the memory device 100 may be updated.

The mode register 320 stores the first reference voltage setting code MR [6: 0] provided to the reference voltage setting circuit 330 and controls the FSP operation mode FSP- OP) and the CBT operation mode CBT_OP and stores the CA ODT code CA_ODT [6: 4] and stores the DQ ODT code DQ_ODT [2: 0] provided to the DQ ODT control circuit 370 , And store the WCK ODT code (WCK_ODT [2: 0]) provided to the WCK ODT control circuit 380.

The reference voltage setting circuit 330 generates a reference voltage corresponding to the second reference voltage setting code CBT_DQ [6: 0] received in the DQ [6: 0] data terminal in response to the CBT enable signal CBT_EN in the CBT mode The reference voltage VREFCA can be changed in accordance with the reference voltage code VREFOP [6: 0].

The CA calibration circuit 340 can output the CA_CBT [6: 0] bits of the pattern A received at the CA [6: 0] command / address signal terminal in response to the CBT enable signal CBT_EN in the CBT mode have.

The DQ output drive circuit 350 outputs the pattern A of the CA_CBT [6: 0] bit configuration provided by the CA calibration circuit 340 in response to the CBT enable signal CBT_EN to the DQ [6: 0] Lt; RTI ID = 0.0 > 390 < / RTI >

The memory device 100 may provide on-die termination (ODT) for turning on / off the termination resistors for a command / address (CA) signal, a data clock (WCK) signal, and data DQ. The ODT can be allowed to turn on or turn off the termination resistance through the mode register setting of the memory device 100 in order to improve signal fidelity.

The CA ODT control circuit 360 may control to provide an optimal termination based on the expected impedance match for the command / address (CA) signal. The CA ODT control circuit 360 responds to the CBT enable signal CBT_EN in the CBT mode and outputs a command / address (address) as a resistance value corresponding to the CA ODT code (CA_ODT [6: 4]) setting stored in the mode register 320 (CA) signal.

The DQ ODT control circuit 370 can control to provide optimal termination based on the expected impedance match for the data DQ. The DQ ODT control circuit 370 terminates the data DQ with the resistance value corresponding to the DQ ODT code (DQ_ODT [2: 0]) set in the mode register 320 in the normal mode and sets the DQ ODT Off.

The WCK ODT control circuit 380 can control to provide optimal termination based on the expected impedance match for the data clock signal pair (WCK, WCKB). The WCK ODT control circuit 380 responds to the CBT enable signal CBT_EN in the CBT mode and outputs a data clock signal having a resistance value corresponding to the WCK ODT code (WCK_ODT [2: 0]) set in the mode register 320, The pair (WCK, WCKB) can be terminated.

3 is a timing diagram illustrating the command bus training operation of the memory device of FIG. 3 shows an exemplary timing diagram of signals traveling between the memory device 100 and the memory controller 200 during command bus training.

Referring to FIG. 3, a clock (CK) signal is received from the time Ta0. At the time Ta0, it can indicate that the activated chip select (CS) signal and the command / address signal CA [6: 0] transmitted through the command / address bus 11 are the mode register setting command MRW-1 . At time Ta1, it is possible to indicate that the activated chip select (CS) signal and the command / address signal CA [6: 0] transmitted via the command / address bus 11) are the mode register setting command MRW-2 have. The mode register setting commands MRW-1 and MRW-2 synchronized with the rising edge of the clock (CK) signal are received by the memory device 100 at the time of Ta0 and Ta1 and the memory device 100 receives the command bus training CBT) mode to the mode register 320. [

At time Td1, in response to a transition of logic high of the DQ [7] data synchronized to the rising edge of the data clock (WCK) signal, the memory device 100 may enter the CBT mode. The data clock (WCK) signal may have a clock frequency that is similar to the clock signal generated by dividing the clock (CK) signal, for example, by four. DQ [7] data refers to a data signal excluded from the one-to-one matching relationship with the command / address signal CA [6: 0] among the data (DQ [7: 0]) in the CBT mode. In the CBT mode, each of the CA [6: 0] command / address signals is output as a CBT signal corresponding to each of the DQ [6: 0] data, but DQ [7] data is not used for output as a CBT signal. DQ [7] data that is not used for the CBT output signal can be used as a signal to indicate CBT mode entry.

At the time Td1, when the CBT enable signal CBT_EN is activated by the control logic 120, the reference voltage setting circuit 330 sets the reference voltage VREFCA (6: 0) according to the second reference voltage setting code CBT_DQ [6: 0] ), And the CA ODT control circuit 360 terminates the command / address (CA) signal with the resistance value corresponding to the CA ODT code (CA_ODT [6: 4] The WCK ODT control circuit 380 can terminate the data clock signal pair (WCK, WCKB) with a resistance value corresponding to the WCK ODT code (WCK_ODT [2: 0]) setting .

At time Td2, the frequency setpoint (FSP) can be switched in response to a logic high of the DQ [7] data. From the time Ta0 to the time Td2, the reference voltage setting circuit 330 can change the reference voltage VREFCA according to the first reference voltage setting code MR [6: 0] stored in the mode register 320. [ The FSP can enable an operation setting, such as a reference voltage (VREFCA) setting, a reference voltage (VREFCA) range, and the like. The memory device 100 may set the mode register 320 to the FSP operation mode (FSP-OP). When the memory device 100 is powered up, the FSP-OP is set to the default " 0 ", and the FSP-OP [0] default setting value can be provided for unterminated low frequency operation. Switching to FSP-OP [1] can change the FSP operating mode (FSP-OP) in CBT mode.

At time Td3, the memory device 100 may set the reference voltage VREFCA level in response to a transition of the logic high of the DQ [7] data and the logic high of the data mask inversion (DMI) signal. The reference voltage VREFCA level may be determined by the bit combination of the data signals DQ [6: 0] received by the memory device 100. [ The reference voltage setting circuit 330 outputs a second reference voltage setting code CBT_DQ [6: 0] received at the DQ [6: 0] data terminal as a reference voltage code VREFOP [6: 0] The value of the reference voltage VREFCA can be changed according to the voltage code VREFOP [6: 0].

At the time point Te1, command / address signals CA [6: 0] having " pattern A " at the middle position of the logic high pulse of the chip select (CS) signal can be received. DQ [6: 0]) corresponding to each of the command / address signals CA [6: 0] of "pattern A" in response to the data buffer enable signal DQ_EN output from the data DQ output drive circuit 350 : 0] data output buffers 390 connected to the data terminals can be turned on.

Pattern A " as a CBT output signal through the DQ [6: 0] data terminals of the memory device 100 at time Tf0.

At time Tg0, in response to a transition to a logic low of DQ [7] data synchronized to the rising edge of the clock (CK) signal, memory device 100 may exit the CBT mode.

Figure 4 is a circuit diagram illustrating a portion of the control logic of Figure 2;

4, the control logic 120 may include a comparator 410 and an AND logic 420. The comparator 410 may compare the reference voltage VREFDQ and the DQ [7] data in response to a data clock (WCK) signal. The comparator 410 outputs a logic high if the voltage level of the DQ [7] data is higher than the reference voltage VREFDQ level and outputs a logic low when the voltage level of the DQ [7] data is lower than the reference voltage VREFDQ can do. The AND logic 420 receives the output of the comparator 410 and the first CBT mode signal CBT_MRS provided from the mode register 320 and outputs the CBT enable signal CBT_EN. If the output of the comparator 410 is logic high and the first CBT mode signal CBT_MRS is a logic high, the end logic 420 may output a logic high CBT enable signal CBT_EN.

The control logic 120, illustratively, at the time Td1, the CBT enable signal CBT_EN may be generated logic high. It can act as a drive signal of the CBT mode based on the CBT enable signal CBT_EN of the logic high.

5A to 5C are diagrams for explaining the reference voltage setting circuit of FIG.

5A, the reference voltage setting circuit 330 may include an AND logic 502, a selection unit 510, a reference voltage decoder 520, and a reference voltage generation circuit 530. Referring to FIG.

The end logic 502 may receive a CBT enable signal CBT_EN and a second CBT mode signal CBT_MODE2. The second CBT mode signal CBT_MODE2 is a signal for controlling the reference voltage setting operation to be performed using the version signal DMI [0], which is a data mask. The second CBT mode signal CBT_MODE2 may be provided as a logic high when the data mask inversion signal DMI [0] is logic high. Illustratively, the second CBT mode signal CBT_MODE2 may be provided at a logic high during a period in which the data mask inversion signal DMI [0] is at logic high at the time Td3 in FIG. When the CBT enable signal CBT_EN and the second CBT mode signal CBT_MODE2 are logic high, that is, at the time point Td3, the AND logic 502 outputs an output signal of logic high to the selection signal S0 ). ≪ / RTI >

The selector 510 may output one of the signals input to the first input terminal IN0 and the second input terminal IN1 to the output terminal OUT in response to the selection signal SO. The first reference voltage setting code MR [6: 0] stored in the mode register 320 is input to the first input terminal IN0 and the DQ [6: 0] data is input to the second input terminal IN1 A second reference voltage setting code CBT_DQ [6: 0] can be input.

The selector 510 selects the first reference voltage setting code MR [6: 0] input to the first input terminal IN0 as the reference voltage code VREFOP [6: 0] when the selection signal S0 is logic low, 0]). Illustratively, the first reference voltage setting code MR [6: 0] stored in the mode register 320 may be output as the reference voltage code VREFOP [6: 0] from the Ta0 point to the Td2 point in FIG. have.

The selector 510 selects the second reference voltage setting code CBT_DQ [6: 0] input to the second input terminal IN1 as the reference voltage code VREFOP [6: 0] when the selection signal SO is logic high, 0]). Illustratively, the second reference voltage setting code CBT_DQ [6: 0] received as DQ [6: 0] data at the time Td3 in FIG. 3 may be output as the reference voltage code VREFOP [6: 0] have.

The reference voltage code VREFOP [6: 0] output from the selection unit 510 may be provided to the reference voltage decoder 520. [ The reference voltage decoder 520 outputs the resistance switching signal code RON [3: 0] corresponding to the reference voltage code VREFOP [6: 0], and the resistance switching signal code RON [3: 0] And may be provided to the reference voltage generating circuit 530.

5B, the reference voltage generating circuit 530 includes a plurality of resistors RS0 to RS4 connected in series between a power supply voltage VDDQ and a ground voltage VSS, and a plurality of resistors RS0 to RS4 And transistors MS0 to MS4 connected between the transistors M0 to M4. A voltage corresponding to the resistance switching signal code RON [3: 0] provided as bit information in the reference voltage decoder 520 may be applied to the gates of the transistors MS0 to MS4. The reference voltage generation circuit 530 can output the divided reference voltage VREFCA at the power supply voltage VDDQ by the resistors RS0 to RS4 shorted in accordance with the resistance switching signal code RON [3: 0] have.

5C is a reference voltage setting table that illustratively shows the correlation between the reference voltage code VREFOP [6: 0] and the reference voltage VREFCA as a result of operation of the reference voltage setting circuit 330. [ In the reference voltage setting table, when the reference voltage code VREFOP [6: 0] is 0000000, the reference voltage VREFCA has a voltage value of about 15% of the power source voltage VDDQ and the reference voltage code VREFOP [ The reference voltage VREFCA increases as the reference voltage VREFOP [6: 0] increases and the reference voltage VREFCA increases to 75% of the power source voltage VDDQ when the reference voltage code VREFOP [6: 0] Voltage value. That is, the value of the reference voltage VREFCA can be variably set according to the reference voltage code VREFOP [6: 0].

The reference voltage setting circuit 330 described above exemplarily has a reference voltage code VREFOP [6: 0] corresponding to the second reference voltage setting code CBT_DQ [6: 0] after CBT mode entry at the time Td1 of FIG. 0]) of the reference voltage VREFCA.

FIG. 6 is a circuit diagram illustrating the data (DQ) output drive circuit 350 of FIG.

6, the data (DQ) output drive circuit 350 includes NAND logic 610, a latch circuit 612, and a selector 614.

NAND logic 610 may receive a version signal DMI [0] and a chip select (CS) signal that are data masks and may provide the output of NAND logic 610 to latch circuit 612. The latch circuit 612 can output the CBT output enable signal CBT_DQ_EN by applying the output of the NAND logic 610 and the version signal DMI [0], which is a data mask. Illustratively, the data output buffers at the time point Te1 in FIG. 3 can be turned on.

The selector 614 may input the normal output enable signal NORMAL_DQ_EN to the first input terminal I0 and the CBT output enable signal CBT_DQ_EN to the second input terminal I1. The selector 614 selects either the normal output enable signal NORMAL_DQ_EN of the first input terminal I0 or the CBT output enable signal CBT_DQ_EN of the second input terminal I1 in response to the CBT enable signal CBT_EN And output the selected signal as the data buffer enable signal DQ_EN.

In the normal mode, the selector 614 may output the normal output enable signal NORMAL_DQ_EN to the data buffer enable signal DQ_EN in response to the logic low of the CBT enable signal CBT_EN. The normal mode refers to a mode in which a write operation or a read operation of the memory device 100 is performed.

The selector 614 may output the CBT output enable signal CBT_DQ_EN to the data buffer enable signal DQ_EN in response to the logic high of the CBT enable signal CBT_EN in the CBT mode. Illustratively, the data output buffers 390 (FIG. 3) at the time point Te1 in FIG. 3 can be turned on.

The data buffer enable signal DQ_EN output in accordance with the CBT output enable signal CBT_DQ_EN may be provided to the data output buffer 390. [ The data output buffer 390 can output the pattern A of the CA_CBT [6: 0] bit configuration provided by the CA calibration circuit 340 to the DQ [6: 0] data terminals. Illustratively, the pattern A of the CA_CBT [6: 0] bit configuration can be output as the CBT output signal through the DQ [6: 0] data of the memory device 100 at the time Tf0 in FIG.

7A to 7D are diagrams illustrating a command / address (CA) on-die termination (ODT) control circuit 360. FIG.

Referring to FIG. 7A, the command / address (CA) ODT control circuit 360 may control to provide an optimal termination based on the expected impedance match for the command / address (CA) signal. Command / Address (CA) ODT control circuit 360 may include first to third frequency setpoint drive signal generators 710, 720, 730, CA ODT decoder 740, and CA ODT circuit 750 have.

The first frequency setpoint drive signal generator 710 generates a first frequency setpoint drive signal in response to a CBT enable signal CBT_EN, a first frequency setpoint operation mode signal FSP_OP0, and a first CBT operation mode signal CBT_OP0. Point drive signal FSP_OPD0. The first frequency setpoint operation mode signal FSP_OP0 is a signal corresponding to [00] of the OP [3: 2] setting of the mode table of the mode register 320 shown in FIG. 7B, [0]). The first CBT operation mode signal CBT_OP0 is a signal corresponding to [01] in the OP [5: 4] setting of the mode table of the mode register 320 and may indicate the low frequency setting FSP0 in the CBT mode. The first frequency setpoint drive signal generator 710 outputs the first frequency setpoint operation mode signal FSP_OP0 as a first frequency setpoint drive signal FSP_OPD0 in the normal mode, And output the signal CBT_OP0 as the first frequency set point drive signal FSP_OPD0. The first frequency setpoint drive signal FSP_OPD0 may act as a frequency setpoint enable signal in response to low frequency operation.

The second frequency setpoint drive signal generator 720 generates a second frequency setpoint drive signal in response to the CBT enable signal CBT_EN, the second frequency setpoint operation mode signal FSP_OP1, and the second CBT operation mode signal CBT_OP1. Point drive signal FSP_OPD1. The second frequency setpoint operation mode signal FSP_OP1 is a signal corresponding to [01] of the OP [3: 2] setting of the mode table of the mode register 320 shown in FIG. 7B, FSP [1]). The second CBT operation mode signal CBT_OP1 is a signal corresponding to [10] of the OP [5: 4] setting of the mode table of the mode register 320 and may indicate an intermediate frequency set point FSP1 in the CBT mode . The second frequency setpoint drive signal generator 720 outputs the second frequency setpoint operation mode signal FSP_OP1 as a second frequency setpoint drive signal FSP_OPD1 in the normal mode, And can output the signal CBT_OP1 as the second frequency set point drive signal FSP_OPD1. The second frequency setpoint drive signal FSP_OPD1 may act as a frequency setpoint enable signal according to the intermediate frequency operation.

The third frequency setpoint drive signal generator 730 generates a third frequency setpoint drive signal in response to the CBT enable signal CBT_EN, the third frequency setpoint operation mode signal FSP_OP2, and the third CBT operation mode signal CBT_OP2. Point driving signal FSP_OPD2. The third frequency setpoint operation mode signal FSP_OP2 is a signal corresponding to [10] of the OP [3: 2] setting of the mode table of the mode register 320 shown in FIG. 7B, [2]). The third CBT operation mode signal CBT_OP2 is a signal corresponding to [11] of the OP [5: 4] setting in the mode table of the mode register 320 and may indicate a high frequency set point FSP2 in the CBT mode. The third frequency setpoint drive signal generator 730 outputs the third frequency setpoint operation mode signal FSP_OP2 as the third frequency setpoint drive signal FSP_OPD2 in the normal mode and the third frequency setpoint drive signal generator 730 outputs the third frequency setpoint drive signal FSP_OPD2 as the third frequency setpoint drive signal FSP_OPD2, And output the signal CBT_OP2 as the third frequency setpoint driving signal FSP_OPD2. The third frequency setpoint drive signal FSP_OPD2 may act as a frequency setpoint enable signal according to high frequency operation.

The first to third frequency setpoint drive signals FSP_OPD0, FSP_OPD1 and FSP_OPD2 may be provided to the command / address (CA) ODT decoder 740. [ The CA ODT decoder 740 receives the first to third frequency set point control signals FSP_OPD0, FSP_OPD1 and FSP_OPD2 based on the activated signal and the CA ODT code CA_ODT [6: 4] ODT signals CA_ODT60, CA_ODT 120, CA_ODT 240 may be selectively enabled.

The CA ODT code CA_ODT [6: 4] is a signal corresponding to the OP [6: 4] setting of the mode table of the mode register 320 shown in FIG. 7C and is used for termination of the command / The resistance value can be set. The CA ODT code CA_ODT [6: 4] may be set such that the inherent resistance value RZQ is divided by a predetermined multiple.

Illustratively, the inherent resistance value RZQ is about 240?, And [001] to [110] of the CA ODT code CA_ODT [6: 4] 3, 4, 5, and 6, respectively. The first CA ODT signal CA_ODT 60 is enabled based on the CA ODT code CA_ODT [6: 4] 100 and the second CA ODT signal CA_ODT 120 is enabled based on the CA ODT code CA_ODT [6: 4] [010], and the third CA ODT signal (CA_ODT 240) may be enabled based on the CA ODT code (CA_ODT [6: 4]) [001].

7D, the CA ODT circuit 750 may determine the termination resistance value of the command / address (CA) signal in response to a signal that is enabled among the first through third CA ODT signals (CA_ODT60, CA_ODT 120, CA_ODT 240) . The CA ODT circuit 750 may include first to third termination circuits 751, 752, and 753.

Each of the first to third termination circuits 751, 752 and 753 may be connected to a resistor and a transistor gating to each of the first to third CA ODT signals CA_ODT 60, CA_ODT 120 and CA_ODT 240. The resistance of each of the first to third termination circuits 751, 752, and 753 may have a resistance value of 60?, 120?, And 240 ?.

A command / address (CA) signal terminated with a predetermined resistance value by the CA ODT circuit 750 may be provided to the input buffer 760. The input buffer 760 can receive a command / address (CA) signal based on the reference voltage VREFCA. The reference voltage VREFCA will be output in the reference voltage setting circuit 330 described in Fig. 5A.

The CA ODT control circuit 360 exemplarily outputs a command / address (CA) signal as a resistance value corresponding to the CA ODT code (CA_ODT [6: 4]) setting after entering the CBT mode at the time point Td1 in FIG. Termination.

8A-8C are diagrams illustrating the data (DQ) on-die termination (ODT) control circuit 370 of FIG.

Referring to FIG. 8A, the data (DQ) ODT control circuit 370 can control to provide an optimal termination based on the expected impedance match for the data DQ. The DQ ODT control circuit 370 may include a DQ ODT decoder 810 and a DQ ODT circuit 820.

The DQ ODT decoder 810 selectively enables the first through third DQ ODT signals DQ_ODT60, DQ_ODT 120, and DQ_ODT 240 based on the CBT enable signal CBT_EN and the DQ ODT code DQ_ODT [2: 0] . Illustratively, the DQ ODT decoder 810 receives the first through third (DQ) data corresponding to the DQ ODT code (DQ_ODT [2: 0]) when in normal mode, DQ ODT signals (DQ_ODT60, DQ_ODT 120, DQ_ODT 240).

The DQ ODT code DQ_ODT [2: 0] is a signal corresponding to the OP [2: 0] setting of the mode table of the mode register 320 shown in FIG. 8B and represents a resistance value for termination of the data DQ Can be set. The DQ ODT code (DQ_ODT [2: 0]) can be set such that the unique resistance value RZQ is divided by a predetermined multiple. Illustratively, the inherent resistance value RZQ is about 240?, And [001] to [110] of the DQ ODT code DQ_ODT [2: 0] 3, 4, 5, and 6, respectively. The first DQ ODT signal DQ_ODT 60 is enabled based on the DQ ODT code DQ_ODT [2: 0] 100 and the second DQ ODT signal DQ_ODT 120 is enabled based on the DQ ODT code DQ_ODT [2: 0] [010], and the third DQ ODT signal (DQ_ODT 240) may be enabled based on the DQ ODT code (DQ_ODT [2: 0]) [001].

8C, the DQ ODT circuit 820 may determine the termination resistance value of the data DQ in response to a signal that is enabled among the first through third DQ ODT signals DQ_ODT60, DQ_ODT 120, and DQ_ODT 240. The DQ ODT circuit 820 may include first through third termination circuits 821, 822, and 823. Each of the first to third termination circuits 821, 822 and 823 may be connected to a resistor and a transistor gating to each of the first to third DQ ODT signals DQ_ODT60, DQ_ODT 120, and DQ_ODT 240. The resistance of each of the first to third termination circuits 821, 822, and 823 may have a resistance value of 60Ω, 120Ω, and 240Ω.

Data DQ terminated with a predetermined resistance value by the DQ ODT circuit 820 may be provided to the input buffer 830. [ The input buffer 830 can receive the data DQ based on the reference voltage VREFDQ.

The DQ ODT control circuit 370 is illustratively enabled from the time Ta0 to the time Tb0 in FIG. 3 to terminate the data DQ with a resistance value corresponding to the DQ ODT code (DQ_ODT [2: 0]) setting have. In the CBT mode, the DQ ODT control circuit 370 can disable the DQ ODT from the time Td1 to the time Tg0 in FIG. 3, thereby turning off the DQ ODT.

9A-9C are diagrams illustrating the data clock (WCK) on-die termination (ODT) control circuit 380 of FIG.

9A, the data clock (WCK) ODT control circuit 380 can control to provide optimal termination based on the expected impedance match for the data clock signal pair (WCK, WCKB). The WCK ODT control circuit 380 may include a WCK ODT decoder 910 and a WCK ODT circuit 920.

The WCK ODT decoder 910 selectively enables the first through third WCK ODT signals WCK_ODT60, WCK_ODT 120, and WCK_ODT 240 based on the CBT enable signal CBT_EN and the WCK ODT code WCK_ODT [2: 0] .

The WCK ODT code WCK_ODT [2: 0] is a signal corresponding to the OP [2: 0] setting of the mode table of the mode register 320 shown in FIG. 9B, Can be set. The WCK ODT code (WCK_ODT [2: 0]) can be set to divide the inherent resistance value (RZQ) by a predetermined multiple. Illustratively, the inherent resistance value RZQ is about 240?, And [001] to [110] of the WCK ODT code WCK_ODT [2: 0] 3, 4, 5, and 6, respectively. The first WCK ODT signal WCK_ODT 60 is enabled based on the WCK ODT code WCK_ODT [2: 0] 100 and the second WCK ODT signal WCK_ODT 120 is enabled based on the WCK ODT code WCK ODT [2: 0] [010], and the third WCK ODT signal (WCK_ODT 240) may be enabled based on the WCK ODT code (WCK_ODT [2: 0]) [001].

9C, the WCK ODT circuit 920 determines the termination resistance value of the data clock signal pair (WCK, WCKB) in response to a signal that is enabled among the first through third WCK ODT signals (WCK_ODT60, WCK_ODT 120, WCK_ODT 240) . The WCK ODT circuit 920 includes first to third termination circuits 921a, 922b, and 923c connected to a data clock (WCK) line and fourth to sixth termination circuits connected to a complementary data clock (WCKB) (921a, 922b, 923c). Each of the first and fourth termination circuits 921a and 921b may be connected to a 60-ohm resistor with a transistor gated to the first WCK ODT signal WCK_ODT60. Each of the second and fifth termination circuits 922a and 922b may be connected to a 120 Ω resistor with a transistor that is gated to the second WCK ODT signal WCK_ODT 120. Each of the third and sixth termination circuits 923a and 923b may be connected to a 240 Ω resistor and a transistor that is gated to the third WCK ODT signal WCK_ODT 240.

The data clock signal pair (WCK, WCKB) terminated with a predetermined resistance value by the WCK ODT circuit 920 can be provided to the clock buffer 930. The clock buffer 930 can receive the data clock WCK based on the data clock signal pair (WCK, WCKB).

The WCK ODT control circuit 380 exemplarily outputs the data clock signal pair (WCK, WCKB) with the resistance value corresponding to the WCK ODT code (WCK_ODT [2: 0]) setting after entering the CBT mode at the time point Td1 in FIG. Termination.

10 is a block diagram illustrating an example of application of a memory system according to embodiments of the present invention to a mobile device. The mobile device may be a mobile phone, a smart phone, a computing tablet, a wireless enabled e-reader, a wearable computing device, and the like.

10, the mobile device 1100 includes a Global System for Mobile communication (GSM) block 1110, a Near Field Communication (NFC) transceiver 1120, an input / output block 1130, an application block 1140, 1150), and a display (1160). In FIG. 10, the components / blocks of the mobile device 1100 are illustratively shown. The mobile device 1100 may include more or fewer components / blocks. Also, while the present embodiment is shown using GSM technology, the mobile device 1100 may be implemented using other technologies such as Code Division Multiple Access (CDMA). The blocks of FIG. 10 will be implemented in the form of an integrated circuit. Alternatively, some of the blocks may be implemented in an integrated circuit fashion while other blocks may be implemented in a separate form.

The GSM block 1110 is coupled to the antenna 1111 and is operable to provide wireless telephone operation in a known manner. The GSM block 1110 may internally comprise a receiver and a transmitter to perform corresponding receive and transmit operations.

NFC transceiver 1120 may be configured to transmit and receive NFC signals using inductive coupling for wireless communication. Wireless communication may include a personal area network such as Bluetooth, a local area network such as WiFi and / or a wide area network such as WiMAX, or other wireless communication. NFC transceiver 1120 provides NFC signals to NFC antenna matching network system 1121 and NFC antenna matching network system 1121 can transmit NFC signals through inductive coupling. The NFC antenna matching network system 1121 can receive the NFC signals provided from other NFC devices and provide the received NFC signals to the NFC transceiver 1120.

Application block 1140 may include hardware circuits, e.g., one or more processors, and may be operable to provide various user applications provided by mobile device 1100. [ User applications may include voice call operations, data transmission, data swapping, and the like. Application block 1140 may operate in conjunction with GSM block 1110 and / or NFC transceiver 1120 to provide operating characteristics of GSM block 1110 and / or NFC transceiver 1120. Alternatively, application block 1140 may include a program for Point Of Sale (POS). Such a program can provide a credit card purchase and payment function using a mobile phone, i.e., a smart phone.

Display 1160 may display an image in response to display signals received from application block 1140. [ The video may be provided by application block 1140 or by a camera embedded in mobile device 1100. Display 1160 includes a frame buffer internally for temporary storage of pixel values, and may be configured as a liquid crystal display screen with associated control circuits.

The input / output block 1130 provides input functionality to the user and provides outputs to be received via the application block 1140. Input / output block 1130 represents hardware devices and software components associated with interaction with a user. The input / output block 1130 may be operable to manage the display 1160 and / or some hardware of the audio system. For example, input via a microphone or audio device may be provided to application block 1140. When the display 1160 includes a touch screen, the display 1160 can function as an input device that can be partially managed by the input / output block 1130. Additional buttons or switches may be present in the mobile device 1100 to provide input / output (I / O) functionality managed by the input / output block 1130. Output block 1130 may manage devices such as accelerometers, cameras, optical sensors, or other hardware that may be included in other environmental sensors, gyroscopes, global positioning systems (GPS), or mobile devices 1100.

Memory 1150 stores programs (instructions) and / or data to be used by application block 1140 and may be implemented as RAM, ROM, flash memory, and the like. Thus, the memory 1150 may include nonvolatile storage elements as well as volatility. For example, the memory 1150 may include the memory system 1000 described in FIGS. 1-9.

Memory 1150 may support a CBT mode that improves the accuracy of command bus training (CBT). The memory 1150 enters the CBT mode in response to the first logic level of the first data signal and may exit the CBT mode in response to a second logic level that is opposite the first logic level of the first data signal. In the CBT mode, the memory 1150 may receive the CBT pattern consisting of the bit configuration of the command / address signals and output the CBT pattern through the terminals of the second data signals corresponding one-to-one with the command / address signals. The memory 1150 changes the reference voltage value according to the second reference voltage setting code received at the terminals of the second data signals, and outputs the command / address CA as a resistance value corresponding to the CA ODT code setting stored in the mode register. Terminate the signal, terminate the data clock signal pair (WCK, WCKB) with the resistance value corresponding to the WCK ODT code set stored in the mode register, and turn off the ODT of the data (DQ) signals. The first data signal may be set to one of signals other than the second data signals among the data signals of the memory device in the CBT mode.

Although the present disclosure has been described with reference to the embodiments shown in the drawings, it is to be understood that various modifications and equivalent embodiments may be made by those skilled in the art without departing from the scope and spirit of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (10)

1. A memory device supporting a command bus training (CBT) mode,
A data clock signal;
Command / address signals to which a command bus training (CBT) pattern is transmitted;
Data signals including first data signals in which the CBT pattern is not output and second data signals in which the command bus training patterns are output in a one-to-one correspondence with the command / address signals in the CBT mode; And
Control to enter the CBT mode in response to a first logic level of the first data signal synchronized to the data clock signal; and in response to a second logic level opposite to the first logic level of the first data signal And control logic to control the CBT mode to escape. 2. The apparatus of claim 1,
Controls to receive the CBT pattern through the terminals of the command / address signals in the CBT mode, and outputs the CBT pattern through the terminals of the second data signals. 2. The apparatus of claim 1,
Wherein the controller controls the reference voltage setting code to change the reference voltage value according to the reference voltage setting code in the CBT mode through the terminals of the second data signals. 4. The apparatus of claim 3,
And controls to receive the CBT pattern by comparing the changed reference voltage value with the voltage level of each of the command / address signals. The memory device according to claim 1,
Further comprising a mode register for storing an on-die termination (ODT) code of the command / address signals, an on-die termination (ODT) code of the data signals or an on- Memory device. 6. The method of claim 5,
And controls each of the lines of the command / address signals to terminate in a resistance value corresponding to a setting of an ODT code of the command / address signals in the CBT mode. 7. The apparatus of claim 6,
In the CBT mode, controls the ODT code of the command / address signals to be set in correlation with a frequency setpoint operation mode signal based on an operating frequency of the memory device. 6. The method of claim 5,
In the CBT mode, controls the ODT to be turned off on the data bus through which the data signals are transmitted,
And controls the data bus to terminate the data bus on which the data signals are transmitted with a resistance value corresponding to a setting of the ODT code of the data signals in the normal mode in which the write or read operation of the memory device is performed. 6. The method of claim 5,
And controls each of the lines of the data clock signal pair to terminate with a resistance value corresponding to an ODT code setting of the data clock signal pair in the CBT mode. A method of operating a memory device supporting a command bus training (CBT) mode,
Receiving a data clock signal;
Entering the CBT mode in response to a first logic level of a first data signal synchronized to the data clock signal;
Receiving, in the CBT mode, a command bus training (CBT) pattern comprising a bit configuration of command / address signals;
In the CBT mode, outputting the CBT pattern through terminals of second data signals corresponding one-to-one with the command / address signals; And
And exiting the command bus training mode in response to a second logic level opposite to the first logic level of the first data signal synchronized to the data clock signal,
Wherein the first data signal is set to one of the data signals of the memory device in the CBT mode and not the second data signals.

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