KR20190023297A - Insulating film and circuit board having the same - Google Patents

Abstract

This disclosure relates to a resin layer comprising a polymeric material and an insulating film comprising an inorganic filler mixed with the resin layer and having a negative thermal expansion coefficient. The present disclosure also relates to an insulating film comprising a resin layer containing a polymer material and an inorganic filler containing an inorganic material having a negative thermal expansion coefficient, and a circuit board including a circuit layer in contact with the insulating film.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an insulating film,

The present disclosure relates to an insulating film and a circuit board having the insulating film.

In the recent circuit substrate technology, miniaturization, thinning, and multifunctionality are required. The miniaturization means to realize a fine line width in accordance with the trend of miniaturization of the semiconductor, to minimize the pad interval and to improve the accuracy of the alignment, and the thinning means to manufacture a thin circuit board in accordance with the trend of thinning of electronic equipment And multifunctionality means that active elements or passive elements are embedded in the circuit board to perform various roles.

To meet these requirements, circuit boards are fabricated by stacking and pressing various types of build-up insulation films one after the other. Build-up insulation films are provided in the form of very thin foils, and a variety of techniques are being actively studied to minimize the occurrence of warpage-induced strains in the circuit board during the manufacturing process.

One of the objects of the present disclosure is to provide an insulating film capable of reducing the warpage of a circuit board and thereby a circuit board with reduced warpage.

One of the solutions proposed through this disclosure is to construct an insulating film with an inorganic filler made of a material having a negative thermal expansion coefficient.

For example, the insulating film according to one embodiment proposed through the present disclosure may include a resin layer including a polymer material, and an inorganic filler mixed with the resin layer and having a negative thermal expansion coefficient have.

In addition, the circuit board according to an embodiment in which the warping is reduced through the present disclosure is an insulating film comprising a resin layer including a polymer material and an inorganic filler including an inorganic material having a negative thermal expansion coefficient, and And a circuit layer in contact with the insulating film.

It is possible to provide an insulating film capable of reducing the warpage of the circuit board as one of the effects of the present disclosure and a circuit board with reduced warpage thereby.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

1 is a cross-sectional view schematically showing an insulating film according to an embodiment of the present invention.
2 is an enlarged view showing a part of an insulating film according to an embodiment of the present invention.
3 is a cross-sectional view schematically showing a circuit board according to an embodiment of the present invention.
FIGS. 4 to 6 are cross-sectional views of main steps schematically showing a method of manufacturing a circuit board according to an embodiment of the present invention.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Insulating film

1 is a cross-sectional view schematically showing an insulating film according to an embodiment of the present invention.

Referring to FIG. 1, an insulating film 100 according to an embodiment of the present invention may include a carrier film 110, an insulating layer 120, and a cover film 130.

The insulating film 100 may be used as a build-up insulating layer for manufacturing a predetermined circuit board. For example, the insulating film 100 may be formed from a variety of different materials, including flexible printed circuit boards (flebible PCBs), rigid printed circuit boards (rigid PCBs), lightly flexible printed circuit boards And may be for the production of an interlayer insulating layer constituting a package substrate.

The carrier film 110 is a layer for moving the insulating layer 120 and may be a layer that is finally removed after laminating the insulating film 100 on the circuit board. The carrier film 110 may include, for example, polyethylene terephthalate (PET) or polyimide (PI).

The insulating layer 120 may include a resin layer including a polymer material and an inorganic filler mixed with the resin layer. The inorganic filler may be made of a material having a negative coefficient of expansion (CTE). Whereby the total coefficient of thermal expansion of the insulating layer 120 may be less than 32 ppm / K and may have a range of, for example, 24 ppm / K to 31 ppm / K. Thus, in the step of manufacturing the circuit board, occurrence of warpage in the circuit board can be minimized. This will be described in more detail below with reference to FIG.

The thickness of the insulating layer 120 may range from 10 占 퐉 to 40 占 퐉 and may have a thickness for securing the function as an interlayer insulating layer of the circuit board. If the thickness of the insulating layer 120 is less than 10 m, it may be difficult to realize a function of minimizing signal loss as an interlayer insulating layer, and if the thickness of the insulating layer 120 exceeds 40 m , It may be difficult to realize the thinning of the circuit board.

The cover film 130 is a layer for protecting the insulating layer 120 and may be removed for laminating the insulating film 100 on the circuit board. The cover film 130 may comprise, for example, polypropylene (PP) or polyethylene (PE) or the like.

In the exemplary embodiment, the insulating film 100 is formed between the carrier film 110 and the insulating layer 120, or between the cover film 130 and the insulating layer 120, The adhesive layer may further comprise an adhesive layer. The adhesive layer may be composed of, for example, a resin composition containing an epoxy resin, a curing agent, a curing accelerator, a thermoplastic resin and an inorganic filler.

2 is an enlarged view showing a part of an insulating film according to an embodiment of the present invention. Fig. 2 shows an enlarged view of one region ("A" region) of the insulating layer 120 in Fig.

Referring to FIG. 2, the insulating layer 120 may include a resin layer 122 including a polymer material and an inorganic filler 124 mixed with the resin layer 122.

The resin layer 122 may be made of resin and various other additives. For example, the resin layer 122 may be formed of an epoxy resin, a polyimide resin, a butyral resin, a polyamide imide (PAI) resin, a polyamide resin, a liquid crystal polymer a liquid crystal polymer (LCP) resin, and a cycloolefin (COP) resin. The epoxy resin may be at least one selected from the group consisting of naphthalene type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolak type epoxy resin, cresol novolak type epoxy resin, rubber modified epoxy resin, cyclic aliphatic type epoxy resin, An epoxy resin, a nitrogen-based epoxy resin, and a phosphorus-based epoxy resin, but is not limited thereto. The additives may include a curing agent, a curing accelerator, a flame retardant aid, and the like.

The inorganic filler 124 may be provided to improve the mechanical, electrical, thermal properties, etc. of the insulating layer 120. The inorganic filler 124 may be made of a material having a negative thermal expansion coefficient. That is, the inorganic filler 124 may be made of a material whose volume decreases when the temperature rises. In particular, the inorganic filler 124 may have a negative thermal expansion coefficient at a temperature of 1000 K or less.

The inorganic filler 124 may be a material having the formula AM ₂ O ₈ , B ₂ (MO ₄ ) ₃ or AN ₂ O ₇ . At least one of zirconium (Zr) and hafnium (Hf) is high, M is at least one kind of molybdenum (Mo) and tungsten (W), B is at least one of scandium (Sc), yttrium (Y) Is at least one of trivalent ions including erbium (Er), lutetium (Lu) and aluminum (Al), and N may be vanadium (V), but is not limited thereto.

Inorganic filler 124, for example, zirconium, tungsten oxide (ZrW ₂ O _8), hafnium tungsten oxide (HfW ₂ O _8), zirconium molybdenum oxide (ZrMo ₂ O _8), hafnium molybdenum oxide (HfMo ₂ O _8), At least one of scandium molybdenum oxide (Sc ₂ (MoO ₄ ) ₃ ), yttrium molybdenum oxide (Y ₂ (MoO ₄ ) ₃ ), aluminum molybdenum oxide (Al ₂ (MoO ₄ ) ₃ ) and zirconium vanadium oxide (ZrV ₂ O ₇ ) One can be included.

The inorganic filler 124 may have a thermal expansion coefficient of, for example, -2 ppm / K to -15 ppm / K. For example, if the inorganic filler 124 is cubic zirconium tungstate (ZrW ₂ O ₈ ) having a thermal expansion coefficient of -9.0 ppm / K and the resin layer 122 has a thermal expansion coefficient of 64.2 ppm / K When the inorganic filler 124 and the resin layer 122 are mixed at a ratio of 1: 1, the insulating layer 120 may have a thermal expansion coefficient of 27.5 ppm / K. Which corresponds to a thermal expansion coefficient as low as 10 ppm / K as compared to the case where silicate is used as the inorganic filler (124). Therefore, the insulating layer 120 according to the embodiment of the present invention can have a relatively low coefficient of thermal expansion, thereby minimizing the deformation caused by the difference in thermal expansion coefficient between the various layers during the manufacture of the circuit board.

The inorganic filler 124 may be mixed in a substantially uniform distribution within the resin layer 122 throughout the insulating layer 120 but may be distributed to have a high volume fraction in localized areas, . However, the embodiment of the present invention is not limited thereto. In exemplary embodiments, the inorganic filler 124 may be distributed so as to include a high-concentration layer and a low-concentration layer of the inorganic filler 124. The inorganic filler 124 may have a generally spherical shape and may have an average particle diameter in the range of 0.01 탆 to 5 탆, but the shape and size of the inorganic filler 124 are not limited thereto.

Circuit board

3 is a cross-sectional view schematically showing a circuit board according to an embodiment of the present invention.

3, a circuit board 1000 according to an embodiment of the present invention includes a substrate 200, first to third circuit layers 210, 220 and 230, and a first circuit layer 210 And may include first and second insulating layers 120a and 120b and solder resist layer 240 arranged to be disposed. The first through third circuit layers 210, 220 and 230 further include first through third vias 212, 222 and 232 connecting the first through third circuit layers 210, 220 and 230 can do.

Although the circuit board 1000 of the present embodiment is illustrated as a cored substrate, the present invention is not limited thereto. For example, the circuit board 1000 may be formed as a coreless structure.

The substrate 200 may be formed of an insulator or a copper clad laminate (CCL) in which copper foils are laminated on both sides of an insulator. For example, the copper-clad laminate may be a glass / epoxy copper clad laminate such as FR-1 to FR-5, but is not limited thereto.

The first through third circuit layers 210, 220 and 230 function as circuit patterns in the circuit board 1000 and may be made of a conductive metal. The first to third circuit layers 210, 220 and 230 may be formed of, for example, copper, aluminum, silver, tin, gold, (Pd), an alloy thereof, or the like. The first to third circuit layers 210, 220, and 230 may serve as bumps or electrodes necessary for mounting and / or embedding electronic components, etc., in addition to circuit patterns.

In this embodiment, the circuit board 1000 has a structure including three circuit layers of the first to third circuit layers 210, 220 and 230, but the embodiments of the present invention are not limited thereto. In one embodiment, the circuit board may have only two circuit layers or may further include build-up layers.

The first circuit layer 210 may include a first via 212 that is a through vias through the substrate 200 to connect the top and bottom surfaces of the substrate 200. The second and third circuit layers 220 and 230 may include a second via 222 connecting the first and second circuit layers 210 and 220 and a second and third circuit layers 220 and 230, And a third via 232 connecting the first and second vias. Accordingly, the first to third circuit layers 210, 220, and 230 disposed on different layers are electrically connected to form an electrical path to the circuit board 1000. Such an electrical path may be electrically connected to an electronic component or the like mounted and / or embedded in the circuit board 1000.

The arrangement of the second and third vias 222 and 232 is not limited to the configuration in which they are independently arranged as shown in the drawing. The second and third vias 222 and 232 of the respective layers are shifted from each other, Or may have a stack via configuration in which the second and third vias 222, 232 of each layer are stacked vertically.

Although the first to third vias 212, 222 and 232 are shown as being completely filled with the conductive metal in the drawing, the present invention is not limited thereto. For example, the conductive metal may be formed along the side wall of the via hole . Although the second and third vias 222 and 232 are tapered to have a larger diameter toward the lower surface, they may have a tapered shape or a cylindrical shape with a smaller diameter toward the lower surface.

The first and second insulating layers 120a and 120b may correspond to the insulating layer 120 described above with reference to FIGS. Accordingly, the first and second insulating layers 120a and 120b may include a resin layer including a polymer material and an inorganic filler mixed with the resin layer. The inorganic filler may be made of a material having a negative thermal expansion coefficient. Accordingly, the total thermal expansion coefficient of each of the first and second insulating layers 120a and 120b may be less than 32 ppm / K. The first and second insulating layers 120a and 120b may be made of the same material or may be made of different materials.

The solder resist layer 240 may be disposed on the upper surface of the circuit board 1000 so as to cover a peripheral portion of the circuit board 1000 while exposing a part of the third circuit layer 230. [ The solder resist layer 240 may be made of, for example, a photosensitive resin.

Method of manufacturing circuit board

FIGS. 4 to 6 are cross-sectional views of main steps schematically showing a method of manufacturing a circuit board according to an embodiment of the present invention.

Referring to FIG. 4, a substrate 200 having a first circuit layer 210 formed on its top and bottom surfaces is prepared, and a first insulating film 100a to be laminated on the substrate 200 is prepared.

The substrate 200 may include, for example, an insulator and metal layers disposed on both sides of the insulator. The first circuit layer 210 may be formed using a dry film pattern such as PVD (Physical Vapor Deposition) such as CVD (Chemical Vapor Deposition) and sputtering, subtractive method, electroless copper plating Or an additive method using electrolytic copper plating, a Semi-Additive Process (SAP), and a Modified Semi-Additive Process (MSAP).

The first insulating film 100a may include a carrier film 110a and a cover film 130a attached to the upper and lower surfaces of the first insulating layer 120a. The carrier film 110a and the cover film 130a protect the first insulating film 100a and move the first insulating film 100a from the moving device for moving the first insulating film 100a, 100a can be prevented from slipping. In order to attach the first insulating layer 120a to the substrate 200, the cover film 130a may be removed.

Referring to FIG. 5, a first insulating layer 120a may be formed on the substrate 200, and a via hole VH may be formed in the first insulating layer 120a.

The first insulating layer 120a may be formed by pressing a first insulating layer 120a on a substrate 200 using a laminator and curing the first insulating layer 120a. After the first insulating layer 120a is laminated on the substrate 200, the carrier film 110a can be finally removed. By performing the curing process in the above process, the first insulating layer 120a can be cured. In this step, since the first insulating layer 120a has a relatively low thermal expansion coefficient, deformation occurring in the stacked structure of the substrate 200 and the first insulating layer 120a can be minimized.

The via hole VH may be formed to expose the first circuit layer 210, and may be formed using a mechanical drill and / or a laser drill. The laser drill may be a CO ₂ laser or a YAG laser, but is not limited thereto.

Referring to FIG. 6, a second insulating layer 120b may be formed after a second circuit layer 220 is formed on an upper surface of the first insulating layer 120a.

The second circuit layer 220 may be formed to include a second via 222 in which a via hole VH is filled with a conductive material and may be formed using the processes described above similarly to the first circuit layer 210 . The first insulating layer 120a and the second circuit layer 220 may form one build-up layer.

The second insulating layer 120b may be formed on the first insulating layer 120a in the same manner as the first insulating layer 120a.

Next, referring to FIG. 3, a solder resist layer 240 may be formed after the third circuit layer 230 is formed on the upper surface of the second insulating layer 120b. The solder resist layer 240 may have openings for electrical connection with external electronic components and the third circuit layer 230 may be exposed through the openings.

The meaning of being connected in this disclosure includes not only a direct connection but also an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection.

The word " an embodiment " used in the present disclosure is not intended to be regarded as the same embodiment, and is provided to emphasize and illustrate different characteristic features. However, the above-described embodiments do not exclude that they are implemented in combination with the features of other embodiments. For example, although the matters described in the specific embodiment are not described in the other embodiments, other embodiments may be understood as related to the other embodiments unless otherwise described or contradicted by the other embodiments.

The terms used in this disclosure are used only to describe one embodiment and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

100: insulating film
110: carrier film
120: insulating layer
130: Cover film
200: substrate
210: first circuit layer
220: second circuit layer
230: third circuit layer
120a: first insulating layer
120b: second insulating layer
212: First Via
222: Second Via
232: Third Via
240: solder resist layer
1000: circuit board

Claims (10)

A resin layer containing a polymer material; And
And an inorganic filler mixed with the resin layer and having a negative thermal expansion coefficient.
The method according to claim 1,
The inorganic filler has the formula AM ₂ O ₈ , B ₂ (MO ₄ ) ₃ or AN ₂ O ₇ ,
Wherein M is at least one selected from the group consisting of molybdenum (Mo) and tungsten (W), B is at least one selected from the group consisting of scandium (Sc), yttrium (Y) ), Iridium (Er), lutetium (Lu) and aluminum (Al), and N is vanadium (V).
3. The method of claim 2,
Wherein the inorganic filler is zirconium tungsten oxide (ZrW ₂ O ₈ ).
The method according to claim 1,
Wherein the total thermal expansion coefficient of the resin layer and the inorganic filler is less than 32 ppm / K.
The method according to claim 1,
The resin layer may be formed of an epoxy resin, a polyimide resin, a butyral resin, a polyamide imide (PAI), a resin polyamide resin, a liquid crystal polymer (LCP) ) Resin, and a cycloolefin (COP) resin.
The method according to claim 1,
Wherein the inorganic filler is present in a high volume fraction in localized areas while being uniformly distributed within the resin layer.
The method according to claim 1,
A carrier film covering one surface of the resin layer; And
And a cover film covering the other surface of the resin layer.
An insulating film comprising an inorganic filler including a resin layer including a polymer material and an inorganic material having a negative thermal expansion coefficient; And
And a circuit layer in contact with the insulating film.
9. The method of claim 8,
The inorganic filler has the formula AM ₂ O ₈ , B ₂ (MO ₄ ) ₃ or AN ₂ O ₇ ,
Wherein M is at least one selected from the group consisting of molybdenum (Mo) and tungsten (W), B is at least one selected from the group consisting of scandium (Sc), yttrium (Y) ), Iridium (Er), lutetium (Lu) and aluminum (Al), and N is vanadium (V).
9. The method of claim 8,
Further comprising a substrate on which the circuit layer is disposed and which is bonded to the insulating film.

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