KR20190002673A - Manufacturing Method of Silicon Wafer - Google Patents

Abstract

A manufacturing method of a silicon wafer includes a growing step of growing a silicon single crystal not containing a COP and dislocation clusters by a Czochralski method, an OSF evaluation step of evaluating the generation status of OSF of an evaluation wafer obtained from a silicon single crystal, , And when the OSF is present on the evaluation wafer, the silicon wafer obtained from the same silicon single crystal as the evaluation wafer is subjected to the RTO treatment under the condition of 1310 캜 or higher. When OSF is not present in the evaluation wafer, And a heat treatment step of performing RTO treatment under the condition of

Description

Manufacturing Method of Silicon Wafer

The present invention relates to a method of manufacturing a silicon wafer.

A silicon wafer (hereinafter sometimes referred to as a " wafer ") used as a substrate of a semiconductor device is cut out from a silicon single crystal grown by a Czochralski method (hereinafter also referred to as " CZ method " Polishing, and the like. A crystal grown by the CZ method may have a crystal defect called a grown-in defect.

1 is a vertical cross-sectional view of a pulled-up silicon single crystal and schematically shows an example of a relationship between a defect distribution and V / G. V is the pulling rate of the silicon single crystal, and G is the temperature gradient in the growth direction of the silicon single crystal immediately after pulling.

The temperature gradient G is considered to be substantially constant due to the thermal properties of the hot zone structure of the furnace CZ. Therefore, V / G can be controlled by adjusting the pulling speed V. 1 shows a schematic view of a silicon single crystal grown while gradually lowering V / G along a central axis thereof, Cu attached to its cross section, and the result of observation by X-ray topography after heat treatment .

In FIG. 1, COP (Crystal Originated Particle) is an aggregate of vacancies lacking atoms which should constitute a crystal lattice when silicon single crystal is grown. The dislocation cluster is an aggregate of interstitial silicon that is excessively blown between crystal lattices.

If such COPs are blown into the oxide film at the time of thermally oxidizing the surface of the wafer, GOI (Gate Oxide Integrity) characteristics of the semiconductor device deteriorate. In addition, the dislocation cluster also causes a defective characteristic of the device.

To solve such a problem, it is considered that the pulling speed (V) or the like is adjusted to grow the silicon single crystal not including the COP and dislocation clusters.

Such a silicon single crystal includes at least one region of an OSF (Oxidation Induced Stacking Fault) region, a P _V region, and a P _I region shown in FIG. The P _V region is a defect-free region which is close to COP, which is a public agglomerate, and is dominated by vacancy-type point defects. The P _I region is a defect-free region adjacent to the dislocation cluster and dominated by interstitial silicon-type point defects.

However, even a wafer composed of a defect-free region that does not include COPs and dislocation clusters is not a completely defect-free wafer.

The P _I region contains almost no oxygen precipitation nuclei in the as-grown state, and it is difficult for oxygen precipitates to be generated even when heat treatment is performed.

However, even in the defect-free region, the OSF region is adjacent to the region where the COP is generated, and includes the plate-shaped oxygen precipitates (OSF nuclei) in the as-grown state. For this reason, when the thermal oxidation treatment is performed at a high temperature (generally, 1000 ° C to 1200 ° C), the OSF nuclei are presently present as OSFs. Further, the P _V region contains oxygen precipitation nuclei in an as-grown state, and oxygen precipitates tend to occur when the two-step heat treatment is performed at a low temperature and a high temperature (for example, 800 DEG C and 1000 DEG C) .

The defects potentially present in the OSF region and the P _V region can be obtained by performing reactive ion etching (RIE) on the as-grown wafers to remove oxygen precipitation nuclei existing in the OSF nucleus and the P _V region It can be detected by making it current as a projection on the etching surface. Hereinafter, a defect that can be detected by RIE is referred to as an RIE defect.

However, the RIE defects potentially present on the wafer occur when heat treatment is performed under specific conditions, but the influence on the yield of the device can not be ignored. For example, when the OSF is formed on the surface of the wafer, the leak current is caused and the device characteristics are deteriorated. Further, if the oxygen precipitate nuclei in the P _V region generate oxygen precipitates in the heat treatment process in the device manufacturing process, and this oxide precipitate remains in the active layer of the device of the device, a leakage current may be generated in the device.

Therefore, a manufacturing method of a wafer capable of suppressing the influence on the yield of a device has been studied (see, for example, Patent Document 1).

In the manufacturing method of Patent Document 1, a silicon single crystal containing only at least one of the P _V region and the P _I region is grown, and the wafer cut out from the silicon single crystal is subjected to rapid thermal annealing at 1300 ° C or higher and 1400 ° C or lower , The RIE defect is eliminated from the wafer surface over a depth of at least 1 mu m.

Japanese Patent Publication No. 5578172

However, in the manufacturing method as in Patent Document 1, since heat treatment is performed on all the wafers at a temperature higher than 1300 ° C regardless of the quality of the wafers, for example, heat treatment at Ta ° C sufficiently reduces RIE defects There is a possibility that heat treatment may be performed at Tb ° C lower than Ta ° C or significantly higher than Tc ° C for possible wafers. In the case of performing heat treatment at Tb 占 폚, the RIE defects can not be sufficiently reduced, and when the heat treatment is performed at Tc 占 폚, the RIE defects can be sufficiently reduced. However, unnecessary load is applied to the heat treatment apparatus due to excessive heating, There is a possibility that the heat treatment may not be performed at an appropriate temperature depending on the quality of the product.

It is an object of the present invention to provide a method of manufacturing a silicon wafer which can be manufactured by a suitable heat treatment according to the quality before heat treatment of a silicon wafer with sufficiently reduced RIE defects.

As a result of intensive studies, the present inventors have found that, in a silicon wafer not including COPs and dislocation clusters, heat treatment conditions capable of sufficiently reducing RIE defects are different depending on the occurrence of OSF before heat treatment, It has come to completion.

That is, the present invention provides a method of manufacturing a silicon wafer, comprising: a step of growing a silicon single crystal not containing COP and dislocation clusters by the Czochralski method; And performing a RTO process on a silicon wafer obtained from the same silicon single crystal as the evaluation wafer at 1310 캜 or higher when the OSF is present on the evaluation wafer, And a heat treatment step of performing an RTO treatment on the silicon wafer obtained from the same silicon single crystal as the evaluation wafer under a condition of less than 1310 캜.

Here, the RTO (Rapid Thermal Oxidation) process is a rapid heating / rapid cooling heat process performed in an oxidizing atmosphere.

According to the present invention, in any case, the RIE defects can be sufficiently reduced by the RTO process under different conditions depending on the presence or absence of the OSF. Therefore, the silicon wafer with sufficiently reduced RIE defects can be manufactured by appropriate heat treatment according to the quality before the heat treatment.

In the method of manufacturing a silicon wafer according to the present invention, an RIE defect density evaluation step of evaluating an RIE defect density of another evaluation wafer obtained from the same silicon single crystal as the evaluation wafer on which no OSF is present, wherein when the RIE defect density of not less than 5 × 10 ⁶ gae / ㎤, more than 1270 ℃ conditions for the silicon wafer obtained from the same silicon single crystal and the other evaluation wafer performs a RTO process, the RIE defect density of 5 × 10 ⁶ gae / Cm < 3 >, it is preferable that the silicon wafer obtained from the same silicon single crystal as the other evaluation wafers is subjected to the RTO treatment under the condition of 1250 DEG C or higher.

According to the present invention, RIE defects can be sufficiently reduced in any case by RTO treatment of silicon wafers on which no OSF exists, under different conditions depending on the RIE defect density.

1 is a schematic diagram showing an example of a relationship between a defect distribution and V / G in a silicon single crystal.
2 is a schematic view showing a configuration of a pulling apparatus according to an embodiment of the present invention.
3 is a schematic view showing a configuration of a heat treatment apparatus in the above embodiment.
4 is a view showing the temperature profile of the RTO process in the above embodiment.
5 is a graph showing the relationship between the RTO treatment temperature in Experiment 1 and the maximum in-plane RIE defect density before and after the RTO treatment according to the embodiment of the present invention.
6 is a graph showing the relationship between the RTO treatment temperature in Experiment 2 of the above embodiment and the maximum in-plane RIE defect density before and after the RTO treatment.

(Mode for carrying out the invention)

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

The wafer manufacturing method of the present embodiment is a wafer manufacturing method that includes a growing step of growing a silicon single crystal not containing COPs and dislocation clusters by the CZ method and an OSF evaluation step of evaluating the generation status of OSFs of the evaluation wafers acquired from the silicon single crystal And an RIE defect density evaluation step of evaluating the RIE defect density of another evaluation wafer obtained from the same silicon single crystal as that of the evaluation wafer in which OSF is not present and the evaluation result in the OSF evaluation step and the RIE defect density evaluation step And a heat treatment step of performing an RTO treatment on the silicon wafer obtained from the same silicon single crystal as the wafer.

Hereinafter, the pulling apparatus used in the growing process and the heat treatment apparatus used in the heat treatment process will be described, and then the details of the method of manufacturing the wafer will be described.

[Configuration of the apparatus]

[Configuration of Pull Up Apparatus]

As shown in Fig. 2, the pulling-up device 1 is a device used in the CZ method, and includes a pulling-up device main body 2 and a control part 3. [

The pulling device body 2 includes a chamber 21, a crucible 22 disposed in a central portion of the chamber 21, a heater 23 serving as a heating portion for heating and heating the crucible 22, A heat insulating cylinder 24, a cable 25, and a heat shield 26. [

A gas inlet 21A for introducing an inert gas such as Ar gas into the chamber 21 is formed in the upper portion of the chamber 21. [ In the lower portion of the chamber 21, a gas exhaust port 21B for exhausting the gas in the chamber 21 is formed by driving a vacuum pump (not shown).

Under the control of the control section 3, inert gas is introduced into the chamber 21 from the gas inlet 21A above the chamber 21 at a predetermined gas flow rate. The introduced gas is discharged from the gas exhaust port 21B in the lower portion of the chamber 21 so that the inert gas flows downward from above in the chamber 21. [

The crucible 22 melts silicon, which is a raw material of the wafer, into a silicon melt (M). The crucible 22 is supported by a support shaft 27 capable of rotating and lifting at a predetermined speed. The crucible 22 includes a cylindrical quartz crucible 221 having a bottom and a graphite crucible 222 for accommodating the quartz crucible 221 therein.

The heater 23 is disposed outside the crucible 22 and heats the crucible 22 to melt the silicon in the crucible 22. [

The heat insulating cylinder 24 is arranged so as to surround the crucible 22 and the heater 23.

One end of the cable 25 is connected to a pulling driver (not shown) disposed above the crucible 22, and a seed crystal (SC: Seed Crystal) is attached to the other end. The cable 25 ascends and descends at a predetermined speed under the control of the pull-up driving section by the control section 3 and rotates about the axis of the cable 25. [

The heat shield 26 blocks radiant heat radiated from the heater 23 upward.

The control unit 3 controls the gas flow rate and the furnace inside pressure in the chamber 21, the heating temperature in the chamber 21 by the heater 23, The number of revolutions of the silicon single crystal SM and the timing of raising and lowering the seed crystals SC are controlled to produce the silicon single crystal SM.

[Configuration of Heat Treatment Apparatus]

As shown in FIG. 3, the heat treatment apparatus 5 includes a chamber 51.

In the chamber 51, a wafer tray 52, a base plate 53 disposed on the wafer tray 52, and three support pins 54 erected on the base plate 53 are formed . The three support pins 54 are arranged at intervals of 120 DEG from the upper surface in order to support the circular (silicon) wafer W horizontally.

An upper heating section 55, a lower heating section 56 and a pyrometer 57 are formed outside the chamber 51. [

The upper heating section 55 includes a plurality of upper heating lamps 551 disposed on the upper side of the chamber 51 and the lower heating section 56 includes a plurality of lower heating And a lamp 561 are provided. The upper heating lamp 551 and the lower heating lamp 561 are halogen lamps, and the respective light emitting states are independently controllable. With this configuration, the temperature distribution in the surface of the wafer W can be controlled by controlling the upper heating lamp 551 and the lower heating lamp 561 individually.

The pyrometer 57 is disposed below the lower heating section 56 and measures the temperature of the wafer W. [

The chamber 51 is provided with a gas introducing port 51A for introducing an inert gas or a reactive gas into the chamber 51, a gas exhaust port 51B for discharging the gas in the chamber 51, An opening 51C for transporting the wafer W to the outside of the chamber 51 is formed. When the wafer W is transported into the chamber 51, the opening 51C is covered with an automatic shutter, not shown.

[Manufacturing method of wafers]

In manufacturing a wafer, first, a growth process is performed using the pulling apparatus 1 shown in Fig.

In this growing step, silicon is injected into the crucible 22, and the silicon is heated and melted in an Ar gas atmosphere. Subsequently, the seed crystals SC attached to the cable 25 are immersed in the silicon melt M, and the seed crystals SC are gradually pulled up while the seed crystals SC and the crucible 22 are rotated, (SM).

At this time, it is preferable to control the manufacturing conditions so that the oxygen concentration of the silicon single crystal (SM) is 9.5 x 10 ¹⁷ atoms / cm 3 or more.

Further, when pulling up, the ratio V / G of the pulling rate V and the temperature gradient G in the growth direction of the silicon single crystal SM immediately after pulling is smaller than the value corresponding to A in Fig. 1 and C The manufacturing conditions are preferably controlled so as to fall between the values corresponding to the " Thus, a silicon single crystal (SM) containing no COP and dislocation clusters can be produced. Further, it is more preferable to control the production conditions so that the ratio V / G is between the value corresponding to A in Fig. 1 and the value corresponding to B. Thus, a silicon single crystal (SM) not containing OSF, COP and dislocation clusters can be manufactured. Such a silicon single crystal SM improves the hot zone structure in which the graphite crucible 222, the heater 23, the heat insulating cylinder 24 and the heat shield 26 are disposed, and the silicon single crystal SM immediately after the pulling- (1) capable of adjusting the radial distribution of the temperature gradient (G) in the growth direction of the substrate (1).

Next, the step of obtaining the wafer W is performed.

In this obtaining step, the wafer W can be obtained by cutting the silicon single crystal (SM) into a plurality of blocks, and then performing slicing, lapping, chemical etching, mirror polishing, and other treatments.

Next, an evaluation wafer is selected from the wafer W acquired in the acquisition step, and the occurrence status of the OSF of the evaluation wafer is evaluated (OSF evaluation step).

As a method for evaluating the occurrence of OSF, there is a method in which an evaluation wafer is subjected to a heat treatment at a temperature of 1000 占 폚 占 30 占 폚 for 2 hours to 5 hours at an atmosphere of oxygen and then at a temperature of 1130 占 폚 占 30 占 폚 for 1 hour or more A method of conducting a heat treatment for 16 hours or less, conducting Secco's etching, and then observing under a microscope can be exemplified.

Next, another evaluation wafer is obtained from the same silicon single crystal (SM) as the evaluation wafer in which OSF is not present, and the RIE defect density of the evaluation wafer is evaluated (RIE defect density evaluation step). As a method for evaluating the RIE defect density, the following methods can be exemplified.

First, an evaluation wafer is loaded into a reactive ion etching apparatus, and a selection ratio of Si / SiO ₂ is set to 100 or more in an HBr / Cl ₂ / He + O ₂ mixed gas atmosphere to etch about 5 탆. Next, the evaluation wafer after the reactive ion etching is washed with a hydrofluoric acid aqueous solution, the reaction product adhered to the reactive ion etching is removed, and the RIE defect density at a plurality of locations on the etched surface is measured. Then, the maximum value is evaluated as the RIE defect density of the evaluation wafer.

Next, the wafer W obtained from the same silicon single crystal (SM) as the evaluation wafer is subjected to a heat treatment process based on the evaluation results in the OSF evaluation process and the RIE defect density evaluation process.

In this heat treatment process, the RTO process is performed on the wafer W under the conditions shown in Fig. 4 by using the heat treatment apparatus 5 shown in Fig. The basic RTO process is performed as follows.

First, the wafer W is placed on the support pins 54 in the chamber 51, which is held at the temperature T2 under the control of the upper heating section 55 and the lower heating section 56.

Then the gas is introduced from the gas inlet 51A and the gas is discharged from the gas outlet 51B so that the inside of the chamber 51 is oxidized and thereafter the upper and lower heating portions 55, The wafer W is rapidly heated to the processing temperature T3 at the heating rate? Tu. The oxidizing atmosphere is preferably 100% oxygen, but is not limited thereto. For example, a mixed gas atmosphere of oxygen and an inert gas may be used.

Next, the temperature T3 is stored and held for the storage holding time (K).

Thereafter, by controlling the upper heating section 55 and the lower heating section 56, the wafer W is rapidly cooled down to the temperature decreasing rate? Td to the temperature T1 and thereafter cooled to room temperature, (W) is obtained.

In the RTO process described above,

· OSF exists

There is no OSF and the RIE defect density before RTO treatment is

5 × 10 ⁶ / cm 3 or more

There is no OSF and the RIE defect density before RTO treatment is

When it is less than 5 × 10 ⁶ / cm 3

Is as shown in Table 1 below.

The storage holding time K is preferably 10 seconds or more and 60 seconds or less, and more preferably 30 seconds or less from the viewpoint of productivity.

When OSF is present, the treatment temperature T3 may be 1310 占 폚 or higher, but it is preferably lower than 1350 占 폚 in terms of the service life of the heat treatment apparatus.

Here, generally, the RTO process is performed by supporting the outer peripheral portion of the silicon wafer with a plurality of support pins. In this case, a slip dislocation may occur at a contact portion with the support pin due to the stress due to the self-weight of the silicon wafer acting on the contact point with the support pin or the thermal stress due to the temperature distribution .

From the viewpoint of suppressing the generation of such slip dislocations, the treatment temperature T3 is more preferably lower than the above range regardless of the presence or absence of the OSF and the RIE defect density.

As described above, in any case, the RIE defects can be sufficiently reduced by the RTO process of the presence or absence of the OSF of the evaluation wafer and the RTO process under different conditions depending on the RIE defect density before the RTO process.

Here, the reason why a wafer W sufficiently reduced in RIE defects by the RTO process as described above is obtained will be supplemented.

Generally, the silicon single crystal (SM) grown by the CZ method contains oxygen of about 10 ¹⁸ atoms / cm 3 as an impurity. This oxygen is dissolved in the crystal lattices near the melting point of silicon but part of the oxygen is precipitated as silicon oxide (SiO ₂ ) in the wafer W cut out from the silicon single crystal SM and oxygen precipitates in the P _V region To form crystal defects such as nuclei.

When the wafer W is subjected to the RTO treatment in the oxidizing atmosphere, the silicon oxide in the crystal defects in the wafer W disappears by moving the oxygen atoms constituting the crystal defects into the crystal lattice. Then, after the silicon oxide disappears, a hole remains. Since the RTO process is performed in an oxidizing atmosphere, interstitial silicon is injected from the surface side of the wafer W to fill the voids. As a result, the RIE defects attributed to the oxygen precipitation nuclei in the OSF and P _V regions due to the OSF nuclei are eliminated or reduced.

Example

Next, the present invention will be described in more detail by way of examples, but the present invention is not limited by these examples.

[Experiment 1: Relation between the RTO treatment temperature and the occurrence status of RIE defects before and after the RTO treatment in a wafer including OSF and not containing COP and dislocation clusters]

First, a V / G was controlled using the lifting device 1 described above to produce a silicon single crystal containing OSF and containing no COP and dislocation clusters. The occurrence of the OSF was confirmed by the method exemplified in the above embodiment. Next, wafers were cut out from the silicon single crystal, and the RIE defect density at a plurality of portions of the wafer was measured by the method described in the above embodiment, and the maximum value thereof was obtained as the maximum in-plane RIE defect density.

Table 2 shows the measurement results of the maximum RIE defect density in the plane.

As shown in Table 2, all of the in-plane maximum RIE defect densities of OSF-containing, COP-free and dislocation-free Examples 1 to 18 were larger than the detection limit (8 × 10 ⁴ / cm 3) .

In addition, since the samples of Experimental Examples 1 to 5, Experimental Examples 6 to 11, Experimental Examples 12 to 14, Experimental Examples 15 to 16, and Experimental Examples 17 to 18 are wafers cut from the same silicon single crystal, The values of the maximum in-plane RIE defect density before the RTO treatment in Examples 6, 12, 15 and 17 were measured in Experimental Examples 2 to 5, Experimental Examples 7 to 11, Experimental Examples 13 to 14, Experimental Examples 16, Was used as the value of Experimental Example 18.

Next, using the above-described heat treatment apparatus 5, the samples of Experimental Examples 1 to 18 were subjected to RTO treatment under the following conditions. The samples after the RTO treatment were subjected to the maximum RIE defects in the plane The density was measured.

Temperature T1: 600 ° C

Temperature T2: 800 DEG C

Treatment temperature T3: See Table 2

Holding time (K): 10 seconds

Heating rate ΔTu: 50 ° C./sec

Deceleration rate ΔTd: 33 ° C / sec

In the RTO process, not a wafer after RIE defect density measurement but a wafer cut out from the same silicon single crystal as that used in the RIE defect density measurement was used. The results are shown in Table 2. FIG. 5 shows the relationship between the RTO treatment temperature and the maximum in-plane RIE defect density before and after the RTO treatment. In FIG. 5, the number of data is considerably smaller than in Table 1, but there exist samples having the same maximum RIE defect density in the plane before and after the RTO process.

As shown in Table 2 and FIG. 5, in Experimental Examples 2 to 5 and 8 to 18 in which the treatment temperature T3 was 1310 ° C or higher, irrespective of the RIE defect density before the RTO treatment, the maximum in-plane RIE defect density was below the detection limit A wafer, that is, a wafer in which RIE defects were sufficiently reduced was obtained. On the other hand, in the case of Experimental Examples 1, 6 and 7 in which the treatment temperature T3 is less than 1310 占 폚 (1290 占 폚, 1300 占 폚), wafers having the maximum in-plane maximum RIE defect density larger than the detection limit, .

In view of the above, Experimental Examples 2 to 5 and 8 to 18 correspond to Examples of the present invention, Experimental Examples 1, 6 and 7 correspond to Comparative Examples, and wafers including OSF and COP and dislocation clusters , It was confirmed that a wafer with sufficiently reduced RIE defects can be manufactured by carrying out the RTO treatment at the treatment temperature T3 of 1310 DEG C or higher.

[Experiment 2: Relation between the RTO treatment temperature and the occurrence status of RIE defects before and after RTO treatment in wafers not containing OSF, COP and dislocation clusters]

First, by controlling the V / G of the pulling-up device 1 described above, a silicon single crystal not including OSF, COP and dislocation clusters was produced. Samples (wafers) of Experimental Examples 19 to 61 were prepared in the same manner as in Experiment 1, and the maximum in-plane RIE defect density before the RTO treatment was measured. The results are shown in Tables 3 to 5.

In Experimental Examples 19 to 53, the values of one sample were used as the values of the other samples in the same manner as in Experiment 1, in which the in-plane maximum RIE defect density before RTO treatment was the same.

As shown in Tables 3 and 4, in Experimental Examples 19 to 53 which do not include OSF, COP and dislocation clusters, the RIE defect density before RTO treatment was 5 x 10 ⁶ / cm 3 or more. On the other hand, as shown in Table 5, in Experimental Examples 54 to 61 which did not include OSF, COP and dislocation clusters, the RIE defect density before the RTO treatment was less than 5 x 10 ⁶ / cm 3.

Next, as in Experiment 1, the wafer cut out from the silicon single crystal obtained from the samples of Experimental Examples 19 to 61 was subjected to the RTO treatment and the RIE defect density of the in-plane maximum RIE defect density after the RTO treatment Measurement was carried out. The results are shown in Tables 3 to 5. The relationship between the RTO treatment temperature and the maximum in-plane RIE defect density before and after the RTO treatment is shown in Fig.

The RTO treatment was carried out in the same manner as in Experiment 1, except that the treatment temperature T3 was set under the conditions shown in Tables 3 to 5.

23, 27, 28, 32, 33, 37, 38, 42, 43 and 47 in which the treatment temperature T3 was 1270 DEG C or higher in Experimental Examples 19 to 53 as shown in Tables 3 and 4 and FIG. , 48, 52 and 53, the maximum in-plane RIE defect density after the RTO treatment was below the detection limit, but in the case of the other experimental examples in which the treatment temperature T3 was less than 1270 ° C,

In this respect, Experimental Examples 22, 23, 27, 28, 32, 33, 37, 38, 42, 43, 47, 48, 52 and 53 correspond to the examples of the present invention, 26, 29 to 31, 34 to 36, 39 to 41, 44 to 46 and 49 to 51 correspond to comparative examples, and no OSF, COP and dislocation clusters were included, and the RIE defect density before RTO treatment was 5 It was confirmed that a wafer with sufficiently reduced RIE defects can be manufactured by performing the RTO treatment at a treatment temperature T3 of 1270 DEG C or higher in the case of a wafer of x10 ⁶ / cm3 or more.

On the other hand, as shown in Table 5 and FIG. 6, in all of Examples 54 to 61, the maximum in-plane RIE defect density after the RTO treatment was below the detection limit. From the results of Experimental Examples 19 to 53, it can be inferred that the higher the treatment temperature T3, the smaller the maximum RIE defect density in the plane.

In this respect, when the RIE defect density before the RTO treatment is less than 5 x 10 < ⁶ > / cm < 3 >, the RIE defect is sufficiently reduced at the treatment temperature T3 of 1250 DEG C, It can be estimated that the defects are sufficiently reduced.

In view of the above, Experimental Examples 54 to 61 correspond to Examples of the present invention, and in the case of wafers not containing OSF, COP and dislocation clusters and having a RIE defect density before RTO treatment of less than 5 x 10 ⁶ / cm 3 , And the RTO treatment was performed at a treatment temperature T3 of 1250 占 폚 or more, it was confirmed that a wafer with sufficiently reduced RIE defects could be produced.

SM: silicon single crystal
W: Wafer

Claims (2)

A growing step of growing a silicon single crystal not containing COPs and dislocation clusters by the Czochralski method,
An OSF evaluation step of evaluating the occurrence status of OSFs of the evaluation wafers acquired from the silicon single crystal;
Wherein when the OSF is present on the evaluation wafer, an RTO process is performed on the silicon wafer obtained from the same silicon single crystal as the evaluation wafer at 1310 캜 or higher, and if the OSF does not exist on the evaluation wafer, And a heat treatment step of performing an RTO treatment on a silicon wafer obtained from the same silicon single crystal under a condition of less than 1310 占 폚. The method according to claim 1,
And an RIE defect density evaluation step of evaluating an RIE defect density of another evaluation wafer obtained from the same silicon single crystal as that of the evaluation wafer on which no OSF exists,
Wherein the RIE defect density is 5 x 10 < ⁶ > / cm < 3 > or more, the silicon wafer obtained from the same silicon single crystal as the other evaluation wafers is subjected to RTO treatment at 1270 DEG C or higher, Is less than 5 x 10 < ⁶ > / cm < 3 >, the silicon wafer obtained from the same silicon single crystal as the other evaluation wafers is subjected to RTO treatment at 1250 DEG C or higher.

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