KR20180131668A - Semiconductor device with improved thermal dissipation - Google Patents

Abstract

The present invention relates to semiconductors. An embodiment according to one aspect of the present invention provides a semiconductor having a lower metal layer with improved heat dissipation performance. A semiconductor having a lower metal layer with improved heat dissipation performance includes a substrate, an epi layer formed on the substrate and providing a path through which electrons travel, an upper layer formed on the epi layer and including an active region and an edge region, And a lower metal layer formed under the substrate, wherein a grid pattern is formed in at least a part of the lower surface of the lower metal layer.

Description

Semiconductor device with improved thermal dissipation < RTI ID = 0.0 >

The present invention relates to semiconductors.

A semiconductor device is manufactured by packaging a semiconductor device. The packaging includes a process of fixing a semiconductor element to a lead frame including a plurality of leads, and wire bonding the contact pads and the leads of the semiconductor elements.

On the other hand, heat generation is inevitable when the semiconductor device operates. In particular, power semiconductors are known to generate more heat than other types of semiconductor devices. However, when the temperature of the power semiconductor device rises to a certain temperature, for example, 125 占 폚 or more, the power semiconductor device may be destroyed by heat. To prevent this phenomenon, there are many heat dissipating technologies. In general, it is common to install a heat sink made of aluminum outside the lead frame of a power semiconductor device to prevent thermal breakdown.

The present invention intends to improve the shape of the lower metal layer of the power semiconductor device to improve the heat discharge performance. At the same time, it is intended to improve the performance of the power semiconductor device.

An embodiment according to one aspect of the present invention provides a semiconductor having a lower metal layer with improved heat dissipation performance. A semiconductor having a lower metal layer with improved heat dissipation performance includes a substrate, an epi layer formed on the substrate and providing a path through which electrons travel, an upper layer formed on the epi layer and including an active region and an edge region, And a lower metal layer formed under the substrate, wherein a grid pattern is formed in at least a part of the lower surface of the lower metal layer.

In one embodiment, the grid pattern may be a relief pattern. The grid pattern may include a plurality of vertical patterns extending in the vertical direction and a plurality of horizontal patterns extending in the horizontal direction, and a shallow trench may be formed in an area defined by the intersecting vertical pattern and the horizontal pattern. have.

In another embodiment, the grid pattern may be a relief pattern. Here, the grid pattern may include a plurality of vertical patterns extending in the vertical direction and a plurality of horizontal patterns extending in the horizontal direction, and the vertical pattern and the horizontal pattern may be formed by etching the lower metal layer from the lower surface to the inside, .

 In another embodiment, the grid pattern is formed in a central region of the lower surface, and the remaining region surrounding the central region may be flat.

In another embodiment, the grid pattern may be formed on the entire lower surface.

In another embodiment, the grid pattern is composed of a plurality of vertical patterns extending in the vertical direction and a plurality of horizontal patterns extending in the horizontal direction, and the ratio of the vertical pattern distance to the vertical pattern width is 1: 1 To 20: 1.

According to the embodiment of the present invention, the shape of the lower metal layer of the power semiconductor element is improved to improve the heat discharging performance. At the same time, the performance of the power semiconductor device is improved.

Hereinafter, the present invention will be described with reference to the embodiments shown in the accompanying drawings. For the sake of clarity, throughout the accompanying drawings, like elements have been assigned the same reference numerals. It is to be understood that the present invention is not limited to the embodiments illustrated in the accompanying drawings, but may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof. In particular, the accompanying drawings, in order to facilitate an understanding of the invention, show some of the elements in somewhat exaggerated form. It is to be understood that the breadth, thickness, etc. of the components illustrated in the figures may vary with actual implementations, since the drawings are a means for understanding the invention. In the meantime, the same components throughout the detailed description of the invention will be described with reference to the same reference numerals.
1 is a sectional view exemplarily showing a power semiconductor element with improved heat dissipation characteristics.
FIG. 2 is a view illustrating a process of manufacturing the power semiconductor device shown in FIG. 1. Referring to FIG.
FIG. 3 is a view for explaining patterns formed on the upper surface of the lower metal layer and heat discharge characteristics therefrom.
FIG. 4 is a view illustrating a pattern formed on the upper surface of the lower metal layer shown in FIG. 1. FIG.
5 is a cross-sectional view illustrating a state in which the lower metal layer shown in FIG. 4 is coupled to the lead frame.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Where an element such as a layer, region or substrate is described as being "on" or "onto" another element, the element may be directly on top of another element or may extend directly over it , Or an intervening element may exist. On the other hand, if one element is referred to as being "directly on" another element or "directly onto" another element, there are no other intermediate elements. Also, when an element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present have. On the other hand, if one element is described as being "directly connected" or "directly coupled" to another element, there are no other intermediate elements.

The terms "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" Relative terms such as " vertical "may be used herein to describe a relationship to another element, layer or region of an element, layer or region, as shown in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. For ease of understanding, a power semiconductor device of a general structure is described as an example, but the present invention is not limited to a power semiconductor device.

1 is a sectional view exemplarily showing a power semiconductor element with improved heat dissipation characteristics.

Referring to FIGS. 1 (a) and 1 (b), a power semiconductor device 200 basically includes a substrate 10, an epilayer 11, and an upper structure layer 12. In order to package the power semiconductor device 200, the lower metal layer 100 is formed on the lower surface of the substrate 10. [ The conductive solder material 14 is interposed between the lower metal layer 100 and the lead frame 13 to fix the power semiconductor element 200 to the lead frame 13.

The superstructure layer 12 includes an active region and an edge region. Depending on the structure of the active region, the power semiconductor device 200 operates as a diode or a transistor. A variety of power semiconductor devices 200, such as insulated gate bipolar transistors (IGBTs), power MOSFETs, and MISFETs, may be implemented according to the structure of the transistor. On the other hand, the edge region functions to improve the breakdown voltage by reducing the electric field applied to the side surface of the power semiconductor element 200, and can be formed in various structures like the active region.

 The epi layer 11 provides a path through which electrons travel. The epitaxial layer 11 may be formed on the substrate 10 through epitaxial growth. Here, the epitaxial layer 11 may be doped with an N-type impurity.

 A lower metal layer 100 is formed on the lower surface of the substrate 10. The bottom metal layer 100 is referred to as a collector or drain depending on the type of power semiconductor device 200. The lower metal layer 100 forms an ohmic contact with the substrate 10 to connect the active region and the lead frame 13 to the electrical path. At the same time, the lower metal layer 100 serves to transmit the heat generated by the power semiconductor element 200 to the lead frame 13. The lower metal layer 100 serves as an intermediate medium for fixing the power semiconductor element 200 to the lead frame 13. Here, the substrate 10 may be doped with an N-type impurity.

On the other hand, the surface of the lower metal layer 100 is not flat. In detail, a shallow trench 101 is formed in a partial area of the lower surface of the lower metal layer 100. The width of the shallow trenches 101, the spacing (pitch) between the shallow trenches 101, and the depth of the shallow trenches 101 may be changed. The underlying metal layer of a typical power semiconductor device is formed to be substantially flat. In contrast, the area of the bottom metal layer 100 contacting the solder material 14 is increased due to the shallow trenches 101, compared to the area of the bottom metal layer of a typical power semiconductor device contacting the solder material 14. The increased area allows heat generated by the power semiconductor device 200 to be discharged more and / or faster into the lead frame 13 through the solder material 14. [

1 (a) shows a case where the solder material 14 substantially completely fills the inner space of the shallow trench 101, (b) shows the case where the solder material 14 is filled in the inner space of the shallow trench 101 And only a part thereof is filled. if only a part of the inner space of the shallow trench 101 is filled as shown in Fig. 2 (b), the void 103 may be generated in the remaining space. In one embodiment, the voids 103 can be created in all the shallow trenches 101 formed in the bottom metal layer 100. In another embodiment, the void 103 can be created in a portion of the shallow trench 101 formed in the bottom metal layer 100. The effect of the cavity 103 will be described in detail below with reference to FIGS. 3 and 5. FIG.

FIG. 2 is a view illustrating a process of manufacturing the power semiconductor device shown in FIG. 1. Referring to FIG.

In step (a), an epi layer 12 is formed on the top of the substrate 10 to a predetermined thickness. A superstructure layer 12 is formed on top of the epi layer 12. After the upper structure layer 12 is formed, the substrate 10 is turned over. Hereinafter, one surface of the lower metal layer 100 that contacts one surface of the substrate 10 is referred to as a lower surface of the lower metal layer 100, and the other surface of the opposite lower metal layer 100 is referred to as an upper surface. In the same manner, one surface of the substrate 10 in contact with the lower surface of the lower metal layer 100 will be referred to as the upper surface of the substrate 10.

In step (b), the lower metal layer 100 'may be formed on the upper surface of the substrate 10 using any one of Ni, Ag, Ti, Pt, and Al, or an alloy thereof. The lower metal layer 100 'may be formed by laminating two or more of Ni, Ag, Ti, Pt, and Al, or an alloy thereof. When the lower metal layer 100 'is formed by laminating two or more of Ni, Ag, Ti, Pt, and Al, or an alloy thereof, the thicknesses of the respective metal layers or alloy layers may be different.

In step (c), a shallow trench 101 is formed on the upper surface of the lower metal layer 100. The shallow trenches 101 may be formed on the upper surface of the lower metal layer 100 at substantially the same pitch or at different pitches to form a uniform pattern, for example, a lattice pattern. The shallow trenches 101 may be formed by etching the upper surface of the lower metal layer 100 to a certain depth, or may be formed using various processes such as scraping and heat treatment.

FIG. 3 is a view for explaining patterns formed on the upper surface of the lower metal layer and heat discharge characteristics therefrom.

(a) shows a power semiconductor device in which the upper surface 31 has a substantially flat bottom metal layer 30. [ An active region is formed at the central portion of the power semiconductor device, and an edge region is formed at the periphery thereof. Although not shown, a gate contact and a source contact are formed on the upper surface of the power semiconductor device for electrical connection with the lead frame 13. In this structure, most of the electrons supplied through the source contact pass through the center of the underlying metal layer, which forms the shortest path. As a result, the high temperature region 32 is formed in the central region of the lower metal layer, thereby causing thermal destruction.

(b) and (c) show the upper surface of the lower metal layer 100 on which the pattern is formed. (b) shows an embodiment in which the pattern 110 is formed on the entire upper surface of the lower metal layer 100, (c) the pattern 140 is formed in the upper surface central region of the lower metal layer 100, As shown in Fig. (b) and (c), the pattern may be formed in a lattice form.

the lower metal layer 100 in which the lattice-shaped pattern shown in Figs. 5B and 5C is formed can emit heat more and / or faster than the lower metal layer 30 shown in Fig. 5A. the area in which the lower metal layer 100 and the solder material contact with each other can be increased by the lattice pattern shown in Figs. When the contact area is increased, the thermal resistance is reduced, and consequently, the temperature rise of the patterned region is suppressed.

Here, the area of the high-temperature region 120 may vary depending on the bonding state between the solder material 14 and the lower metal layer 100 by the lattice pattern. Also, the performance of the power semiconductor device may vary depending on the state of connection between the solder material 14 and the lower metal layer 100 by the lattice pattern.

If there is a void between the grid pattern of the underlying metal layer 100 and the solder material 14, the path through which the current can flow is limited to a lattice pattern. As a result, a current dispersion effect is generated, and a heat dispersion effect is generated accordingly. In detail, as shown in (a), the current concentrated in the central region of the lower metal layer 30 becomes dispersed along the lattice pattern, as shown in (b) and (c). Since the current is dispersed, heat due to the current is also dispersed, and the effect that the high-temperature region 120 is expanded occurs. Here, the current dispersion has an effect of increasing the element utilization rate of the power semiconductor element. Due to the characteristics of the electrons flowing along the shortest path, in a general power semiconductor in which a substantially flat bottom metal layer 30 is applied, only the active region located at the center of the entire active region actually operates. On the other hand, the current path is dispersed due to the lattice pattern, so that the active region located outside the center portion also operates.

If there is no gap between the grid pattern and the solder material 14 of the lower metal layer 100, the heat dissipation performance is improved, but the current dispersion effect becomes insignificant. That is, the thermal resistance decreases relatively greatly, but the high temperature region 120 does not substantially expand.

Fig. 4 exemplarily shows a pattern formed on the upper surface of the lower metal layer shown in Fig. 1, wherein (a) shows a grating pattern of a relief, and Fig. 4 (b) shows a grating pattern of a relief.

(a), a plurality of vertical patterns 101C arranged at a first interval Wt1 and a plurality of horizontal patterns 101R arranged at a second interval Wt2 are defined to define a rectangular area. The vertical pattern 101C has a width Wp1, and the horizontal pattern 101R has a width Wp2. Here, the width Wp1 and the width Wp2 may be substantially the same or different. On the other hand, the width Wp1 of each of the plurality of vertical patterns 101C may be substantially the same or different. Similarly, the width Wp2 of each of the plurality of horizontal patterns 101R may be substantially the same or different. In one embodiment, the areas defined by the plurality of vertical patterns 101C and the plurality of horizontal patterns 101R may be square-shaped. Here, the width Wp1 may be substantially the same as the width Wp2, and the interval Wt1 / width Wp1 (or the interval Wt2 / width Wp2) may be about 1 to about 20.

A shallow trench 101 is formed in the defined rectangular area. The shallow trenches 101 may be formed by etching a rectangular region by a depth Dt. It is preferable that the maximum value of the depth Dt does not exceed the thickness Tm of the lower metal layer. In one embodiment, the thickness Tm / depth Dt can be from about 1 to about 6.

The area in which the lower metal layer 100 contacts the solder material 13 is increased by the shallow trenches 101 whose horizontal or vertical cross section is square. When the area increased by one shallow trench 100 is (2 x Dt x Wt 1 + 2 x Dt x Wt 2) and the number of shallow trenches 101 formed in the bottom metal layer 100 is multiplied, . As the contact area is increased, heat generated in the power semiconductor device can be quickly discharged, so that the thermal resistance is reduced, and the performance of the power semiconductor device can be improved. In addition, since the shortest path is dispersed due to the lattice pattern, the active active region concentrated at the center can be expanded.

(b), a plurality of vertical patterns 1012C arranged at a first interval Wt1 and a plurality of horizontal patterns 102R arranged at a second interval Wt2 are intersected with each other to define a rectangular area. The vertical pattern 102C has a width Wp1, and the horizontal pattern 102R has a width Wp2. Here, the width Wp1 and the width Wp2 may be substantially the same or different. On the other hand, the width Wp1 of each of the plurality of vertical patterns 102C may be substantially the same or different. Similarly, the width Wp2 of each of the plurality of horizontal patterns 102R may be substantially the same or different. In one embodiment, the area defined by the plurality of vertical patterns 102C and the plurality of horizontal patterns 102R may be square. Here, the width Wp1 may be substantially the same as the width Wp2, and the interval Wt1 / width Wp1 (or the interval Wt2 / width Wp2) may be about 1 to about 20.

A plurality of vertical patterns 1012C and a plurality of horizontal patterns 102R are etched. The plurality of vertical patterns 1012C and the plurality of horizontal patterns 102R can be etched by the depth Dt. That is, the plurality of vertical patterns 1012C and the plurality of horizontal patterns 102R are etched to form a plurality of shallow trenches extending in the horizontal and vertical directions. A plurality of rectangular columns 102 are formed by a plurality of etched vertical patterns 1012C and a plurality of horizontal patterns 102R. It is preferable that the maximum value of the depth Dt does not exceed the thickness Tm of the lower metal layer. In one embodiment, the thickness Tm / depth Dt can be from about 1 to about 6.

The area in which the lower metal layer 100 is in contact with the solder material 13 is increased by the plurality of etched vertical patterns 1012C and the plurality of horizontal patterns 102R. The area increased by one square column 102 is (2 x Dt x Wt 1 + 2 x Dt x Wt 2) and multiplied by the number of square columns 102 formed in the bottom metal layer 100, . As the contact area is increased, heat generated in the power semiconductor device can be quickly discharged, so that the thermal resistance is reduced, and the performance of the power semiconductor device can be improved. In addition, since the shortest path is dispersed due to the lattice pattern, the active active region concentrated at the center can be expanded.

FIG. 5 is a cross-sectional view illustrating a state in which the lower metal layer shown in FIG. 4 is coupled to the lead frame. FIG. 5 (a) is a state in which the substantially flat lower metal layer 100 'is fixed to the lead frame 13, (b) is a state in which the lower metal layer 100 shown in FIG. 4 (a) is fixed to the lead frame 13, (c) is a state in which the lower metal layer 100 shown in FIG. And is fixed to the frame.

(a), the bottom metal layer 100 ', the surface of which is substantially flat, is fixed to the lead frame 13 using solder material 14.

the lower metal layer 100 on which the shallow trenches 101 are formed is fixed to the lead frame 13 by the solder material 14. [ The solder material 14 interposed between the lower metal layer 100 and the lead frame 13 fills the inside of the shallow trench 101. The distance d1 between the vertical pattern 100C and the lead frame 13 is smaller than the distance d1 between the lower metal layer 100'and the lead frame 13 when the solder material 14 is applied in the same amount as (a) Can be smaller than the distance d0. Therefore, most of the electrons pass through the vertical pattern 100C and move to the lead frame 13. On the other hand, since the plurality of shallow trenches 101 are formed by being isolated by the vertical and horizontal patterns 101R and 101C, the solder material 14 can not completely fill the inside of the shallow trenches 101, Pore may occur. In this case, as described above, the current dispersion and thus the heat dispersion effect may occur. The fixing process between the lower metal layer 100 and the lead frame 13 can proceed in a chamber which is substantially vacuum.

the lower metal layer 100 on which the horizontal and vertical patterns 101R and 101C are etched is fixed to the lead frame 13 by the solder material 14. [ The solder material 14 interposed between the lower metal layer 100 and the lead frame 13 fills the interior of the etched horizontal and vertical patterns 101R and 101C. The distance d2 between the vertical pattern 100C and the lead frame 13 is smaller than the distance d2 between the lower metal layer 100 'and the lead frame 13 shown in (a) when the same amount of solder material 14 as in (a) Is smaller than the distance d0 but may be larger than d1 shown in (b). Therefore, most of the electrons pass through the rectangular column 102 and move to the lead frame 13. On the other hand, only a part of the inside of the etched horizontal and vertical patterns 101R and 110C can be filled with the solder material to generate a gap. In this case, a heat dispersion effect may occur together with an effect of dispersing the current path.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

Claims (8)

Board;
An epi layer formed on the substrate, the epi layer providing a path through which electrons travel;
An upper structure layer formed on the epi layer and including an active region and an edge region; And
And a lower metal layer formed under the substrate,
And a lower metal layer having improved heat discharging performance in which a lattice pattern is formed in at least a part of the lower surface of the lower metal layer. The semiconductor according to claim 1, wherein the lattice pattern has a lower metal layer with improved heat discharging performance, which is a relief pattern. [2] The method of claim 2, wherein the grid pattern comprises a plurality of vertical patterns extending in the vertical direction and a plurality of horizontal patterns extending in the horizontal direction, wherein a shallow trench is formed in the area defined by the intersecting vertical pattern and the horizontal pattern A semiconductor having a bottom metal layer with improved heat dissipation performance. The semiconductor according to claim 1, wherein the grid pattern has a recessed pattern and a lower metal layer with improved heat dissipation performance. 5. The method of claim 4, wherein the grid pattern is comprised of a plurality of vertical patterns extending in a vertical direction and a plurality of horizontal patterns extending in a horizontal direction, wherein the vertical pattern and the horizontal pattern form the lower metal layer A semiconductor having a bottom metal layer formed by etching and having improved heat dissipation performance. The semiconductor according to claim 1, wherein the grid pattern is formed in a central region of the lower surface, and the remaining region surrounding the central region has a lower metal layer with improved flat heat discharging performance. The semiconductor according to claim 1, wherein the grid pattern has a lower metal layer formed on the entire lower surface and having improved heat discharging performance. [2] The method of claim 1, wherein the grid pattern comprises a plurality of vertical patterns extending in the vertical direction and a plurality of horizontal patterns extending in the horizontal direction, wherein a ratio of the vertical pattern distance to the vertical pattern width is 1: Semiconductor with a lower metal layer with improved heat dissipation performance of 20: 1.

Images