KR20180105978A - Operation method for electronic device comprising on-chip network - Google Patents

Abstract

A method for operating an electronic device including a processor, first and second memory devices, and an on-chip network connecting the processor and the first and second memory devices includes the steps of: providing a data transmission command to the first memory device through the on-chip network in the processor; providing data read in the first memory device to the second memory device through the on-chip network in response to the transmission command; writing the provided data in the second memory device; and providing a data writing completion signal to the processor through the on-chip network in the second memory device. Accordingly, the present invention can improve data communication efficiency.

Description

[0001] OPERATION METHOD FOR ELECTRONIC DEVICE COMPRISING ON-CHIP NETWORK [0002]

The present invention relates to electronic devices, and more particularly, to a method of operating an electronic device including an on-chip network.

System on Chip (SoC) is a technology that intensively implements a complex system that performs various functions on one chip. Conventional system-on-chip uses a bus to interconnect IPs (Intellectual Property) in a system-on-chip. However, as the demand for integration and high performance of system-on-chip is raised, the degree of integration of system-on-chip increases and the number of IPs is increasing. In addition, the amount of information for communication between IPs is rapidly increasing. Therefore, the topology design using the bus has limitations on information processing in that data is shared through the common wiring.

In order to overcome the structural limitations of the system-on-a-chip, on-chip network technology for connecting IPs by applying computer network technology in a chip is emerging. IPs can communicate with each other through the network interface units of the on-chip network. In this on-chip network technology, there is still a need to efficiently transmit a large amount of data.

SUMMARY OF THE INVENTION The present invention provides a method of operating an electronic device including an on-chip network for efficiently transmitting a large amount of data.

An operating method of an electronic device including a processor, a first and a second memory device, and an on-chip network connecting a processor and first and second memory devices according to an embodiment of the present invention, Providing the data read from the first memory to the second memory via the on-chip network in response to the transfer command, writing the provided data in the second memory, And in a second memory, providing a data write completion signal to the processor via the on-chip network.

The operation method of the electronic device including the on-chip network according to the embodiment of the present invention can increase the data communication efficiency. Further, since the DMA unit is not used, the area and power consumption of the electronic device can be reduced.

1 is a diagram illustrating an exemplary configuration and data transmission method of an electronic device including an on-chip network.
2 is a block diagram illustrating the configuration of the on-chip network shown in FIG.
3 is a diagram illustrating a configuration of an electronic device and a data transmission method according to an embodiment of the present invention.
FIG. 4 and FIG. 5 are diagrams showing a packet format and an embodiment of the transmission command shown in FIG.
6 and 7 are diagrams showing a packet format and an embodiment of the write command shown in FIG.
FIG. 8 and FIG. 9 are diagrams showing the packet format and the embodiment of the write completion signal shown in FIG.
10 is a flowchart for explaining the operation of the second network interface unit shown in FIG.
11 is a flowchart for explaining the operation of the third network interface unit shown in FIG.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a diagram illustrating an exemplary configuration and data transmission method of an electronic device including an on-chip network. 1, an electronic device 100 includes a processor 110, a first memory 120, a second memory 130, a DMA (Direct Memory Access) unit 140, and an on-chip network 150 can do. For example, the electronic device 100 may be implemented as a SoC (System on Chip) in which the above-described components are integrated on one chip. Alternatively, the electronic device 100 may be configured such that at least one of the components described above is implemented as a module or a chip.

The electronic device 100 may be a computing device (e.g., a personal computer, a peripheral device, a digital camera, a PDA, a portable media player (PMP), a smartphone, A tablet, a wearable device, or the like). However, the present invention is not limited to the above-mentioned examples.

The processor 110 may perform various arithmetic / logic operations to manage and process the overall operations of the electronic device 100. For example, the processor 110 may be a processor circuit or system that includes a general purpose processor or an application processor. The processor 110 is connected to the on-chip network 150 via port a. The processor 110 may communicate with the DMA unit 140, the first memory 120, and the second memory 130 via the on-chip network 150.

The first and second memories 120 and 130 are connected to the on-chip network 150 via ports c and d, respectively. The first and second memories 120 and 130 may each store data provided from the processor 110 or data to be provided to the processor 110 via the on-chip network 150. [ Through the on-chip network 150, the first and second memories 120 and 130 can communicate with each other or with the DMA unit 140, respectively.

The first memory or the second memory 120, 130 may each be implemented in any storage medium including volatile memory or non-volatile memory. For example, when the first or second memory 120 or 130 includes a volatile memory, the first or second memory 120 or 130 may be a dynamic random access memory (DRAM), a static random access memory (SRAM) memory, TRAM (Thyristor RAM), Zero RAM (Z-RAM), or Twin transistor RAM (TTRAM), MRAM, and the like. For example, the first and second memories 120 and 130 may include an unbuffered dual in-line memory module (UDIMM), a registered random access memory (RDIMM), a load reduced random access memory (LRDIMM) can do.

For example, when the first memory or the second memory 120 or 130 includes a non-volatile memory, the first memory or the second memory 120 and 130 may be electrically erasable programmable read-only memory (EPROM) (MRAM), a conductive bridging RAM (CBRAM), a FeRAM (Ferroelectric RAM), a PRAM (Phase change RAM), a Resistive RAM (RRAM) ), Nanotube RRAMs, polymer RAMs (PoRAMs), nano floating gate memories (NFGMs), holographic memories, Molecular Electronics Memory Devices, , Or an Insulation Resistance Change Memory. One or more bits may be stored in the unit cell of the non-volatile memory. The above-mentioned examples are not intended to limit the present invention.

Hereinafter, for convenience of explanation, it is assumed that each of the first and second memories 120 and 130 includes a single memory device. However, as described above, it will be readily understood that the present invention can be applied to various memory devices.

DMA unit 140 is coupled to on-chip network 150 via port b. The DMA unit 140 collectively processes a plurality of successive data in response to a data transfer command provided from the processor 110. [ The DMA unit 140 may communicate with the processor 110, the first memory 120, and the second memory 130 via the on-chip network 150.

Unlike FIG. 1, the electronic device 100 may not include the DMA unit 140. In this case, during operation of the electronic device 100, the processor 110 may provide a data transfer command to the first memory 120. In the following, for example, the data transfer command is assumed to be a command for transferring 32 pieces of data stored in the first memory 120 to the second memory 130. [ In order to transfer data, first, the processor 110 reads data stored in the first memory 120 and stores it in a buffer (not shown) included in the processor 110. [ Then, the processor 110 writes the data stored in the buffer (not shown) into the second memory 130. [ The processor 110 repeats this process for 32 pieces of data.

On the other hand, as shown in FIG. 1, the electronic device 100 may include a DMA unit 140. The DMA unit 140 can simplify the above-described data transfer process. The operation in which the electronic device 100 including the DMA unit 140 transmits a plurality of data will be described below.

The on-chip network 150 connects the processor 110, the first and second memories 120 and 130, and the DMA unit 140 to each other. For example, the on-chip network 150 may be comprised of a single module or a single chip. An exemplary configuration of the on-chip network 150 will be described with reference to FIG.

The on-chip network 150 has scalability and flexibility. The on-chip network 150 may be designed or configured with a network structure selected according to the data traffic of the electronic device 100. The on-chip network 150 supports a variety of settings to ensure various bandwidth, latency, quality of service (QoS), etc. required in the system design of the electronic device 100.

The operation in which the electronic device 100 shown in FIG. 1 transfers a plurality of pieces of data from the first memory 120 to the second memory 130 is as follows. First, the processor 110 provides a data transfer command to the DMA unit 140 via the port a, the on-chip network 150, and the port b (step 1). As described above, the data transfer command may be a command for transferring the 32 data stored in the first memory 120 to the second memory 130. For example, in conjunction with a data transfer command, the processor 110 may determine the ID of the network interface unit (not shown) to which the first memory 120 is connected, the address in the first memory 120 where the data is stored, 2 memory 130 and the like to the DMA unit 140.

In response to the data transfer command, the DMA unit 140 generates a read command. The DMA unit 140 transmits a read command to the first memory 120 via the port b, the on-chip network 150, and the port d (step 2). In response to the read command, the first memory 120 reads the stored data. For example, the read data may include the first of the 32 data. Depending on the burst length, the number of data output by the first memory 120 in response to the read request may vary. Hereinafter, it is assumed that the burst length of the first memory 120 is 1. For convenience of explanation, it is assumed that the data pad of the first memory 120 is one. In this case, the first memory 120 can output one data for one read command. However, the present invention is not limited to the above-mentioned examples.

The first memory 120 provides the read data to the DMA unit 140 (step 3). The DMA unit 140 stores the provided data in the buffer 141. The DMA unit 140 provides the write command to the second memory 130 (step 4). The DMA unit 140 provides the data stored in the buffer 141 to the second memory 130 together with the write command. The second memory 130 stores the provided data. After the second memory 130 stores the data, the first memory 120, the second memory 130, and the DMA unit 140 repeat steps 2, 3, and 4 for all 32 data.

After the second memory 130 stores all 32 data, the second memory 130 transmits a write completion signal to the DMA unit 140 (step 5). The DMA unit 140 feeds back a write completion signal to the processor 110 (step 6). In the embodiment of FIG. 1, the electronic device 100 must have a DMA unit 140 to transfer a plurality of contiguous data from the first memory 120 to the second memory 130.

2 is a block diagram illustrating the configuration of the on-chip network shown in FIG. 2, the on-chip network 150 includes ports a, b, c, and d, first to fourth network interface units (NIU) 151 to 154, . ≪ / RTI >

The on-chip network 150 shown in FIG. 2 is configured as a packet switching network. (E. G., Processor 110, first and second memories 120 and 130, and first and second memories 120 and 130 shown in FIG. 1) connected to ports a, b, c and d of the on- DMA unit 140, etc.) is in the form of a packet.

The packet may include a header field, an address field, and a data field. The header field may contain information such as routing information of the packet, the type of the packet, the size of the packet, and the like. The address field may contain the address of the destination of the packet. For example, the address field may include an ID of a network interface unit to which the IP core is connected, an address in a memory where data is stored, and the like. The data field may include a payload carrying a plurality of data. The size of the data field may be specified in the header field.

The first network interface unit 151 is connected between the port a and the switch unit 155. The second network interface unit 152 is connected between the port c and the switch unit 155. The third network interface unit 153 is connected between the port d and the switch unit 155. The fourth network interface unit 154 is connected between the port b and the switch unit 155.

Although not shown, the first to fourth network interface units 151 to 154 may include at least one of a master network interface unit and a slave network interface unit, respectively. For convenience of explanation, the first to fourth network interface units 151 to 154 will be described by taking the first and third network interface units 151 and 153 as an example. For example, the first network interface unit 151 may include a master network interface unit, and the third network interface unit 153 may include a slave network interface unit.

The master interface unit of the first network interface unit 151 receives information from the master IP (e.g., the processor 110 of FIG. 1) and forwards the information to the switch unit 155. The master interface unit can packetize the information received from the master IP and output it to the switch unit 155. The master interface unit can request a transaction to the on-chip network 150. [

The slave interface unit of the third network interface unit 153 transfers information to the slave IP (for example, the first memory 120). The slave interface unit interprets the packetized information and provides interpreted information to the slave IP. In addition, the slave interface unit may receive and packetize the corresponding information from the slave IP to convey information to the switch unit 155. [ The slave interface unit can provide service in response to a transaction request.

The switch unit 155 may provide the information output from the first to fourth network interface units 151 to 154 to the selected one of the first to fourth network interface units 151 to 154. For example, the switch unit 155 may supply information received from the master interface unit of the first network interface unit 151 to at least one slave interface unit of the second to fourth network interface units 152 to 154 . Alternatively, the switch unit 155 may provide information received from at least one of the slave interface units of the second to fourth network interface units 152 to 154 to the master interface unit of the first network interface unit 151 . However, the present invention is not limited to the above-mentioned examples.

Although not shown, the switch unit 155 may include a plurality of switches capable of changing the signal transmission path to configure the network. Each of the plurality of switches can receive packetized information. Each of the plurality of switches can provide information to the appropriate port based on the address contained in the packetized information. That is, each of the plurality of switches performs a function of a router for connecting the packets provided to the input port to the appropriate output port according to the destination address stored in the packet header. The number of the plurality of switches passed for information transmission can be determined in consideration of the characteristics of each of the switches, the efficiency of the network, and the required information transmission path.

The first network interface unit 151 can transmit information to at least one of the second to fourth network interface units 152 to 154 via the switch unit 155. [ The second network interface unit 152 may communicate information to at least one of the first, third, and fourth network interface units 151, 153, 154 via the switch unit 155. The third network interface unit 153 may communicate information to at least one of the first, second and fourth network interface units 151, 152 and 154 via the switch unit 155. The fourth network interface unit 154 may transmit information to at least one of the first to third network interface units 151 to 153 via the switch unit 155. [

3 is a diagram illustrating a configuration of an electronic device and a data transmission method according to an embodiment of the present invention. 3, an electronic device 1000 may include a processor 1100, first and second memories 1200 and 1300, and an on-chip network 1400. The configuration and functions of the first to third network interface units 1410 to 1430 included in the processor 1100, the first and second memories 1200 and 1300 and the on-chip network 1400 are shown in FIGS. 1 and 2 Are the same as those described with reference to FIG.

In contrast to the electronic device 100 of FIG. 1, the electronic device 1000 of FIG. 3 does not include the DMA unit 140 shown in FIG. With this configuration, the electronic device 1000 of FIG. 3 can process the data transfer command through a simpler process.

The operation in which the electronic device 1000 shown in FIG. 3 transmits a plurality of data is as follows. First, the processor 1100 is connected to the first memory 1200 (a ') via a port a', a first network interface unit 1410, a switch unit 1440, a second network interface unit 1420, and a port b ' (Step < 1 >). As described in FIG. 1, the data transfer command may be a command for transferring 32 pieces of data stored in the first memory 1200 to the second memory 1300. The packet format of the data transfer command and its embodiment will be described in detail with reference to FIG. 4 and FIG.

In response to the data transfer command, the first memory 1200 reads the stored data from the memory cell. Through the port b ', the second network interface unit 1420, the switch unit 1440, the third network interface unit 1430 and the port c', the first memory 1200 stores the read data To the second memory 1300 together with the data write command (step 2). For example, the read data may include the first of the 32 data. The packet format of the write command of the data and its embodiment will be described in detail with reference to Figs. 6 and 7. Fig.

As assumed in FIG. 1, it is assumed that the burst length of the first memory 1200 is 1, and that the first memory 1200 includes one data pad. To output all 32 data, the first memory 1200 may repeat step (2) 32 times. Depending on the burst length of the first memory 1200 or the number of data pads, the number of times the first memory 1200 performs step 2 may vary. For example, when the number of burst lengths or data pads increases, the number of data that the first memory 1200 outputs by one read command increases. In this case, the number of times the first memory 1200 performs step (2) may be reduced.

The second memory 1300 writes the provided 32 pieces of data to the memory cell. After the writing is completed, the second memory 1300 generates a writing completion signal. Through the port c ', the third network interface unit 1430, the switch unit 1440, the first network interface unit 1410 and the port a', the second memory 1300 receives a write complete signal Processor 1100 (step 3). The packet type of the write completion signal and its embodiment will be described in detail with reference to FIGS. 8 and 9. FIG.

As described above, the electronic device 1000 of Fig. 3 does not include a DMA unit. The process of transferring a plurality of data in the electronic device 1000 of FIG. 3 is performed without going through the DMA unit. That is, the data is directly transferred from the first memory 1200 to the second memory 1300 by the data transfer command. Therefore, the data transmission process is simplified. As a result, the transmission speed of a plurality of data between IP cores according to the transmission command can be increased.

FIG. 4 and FIG. 5 are diagrams showing a packet format and an embodiment of the transmission command shown in FIG. 4 and 5 will be described with reference to FIG. 4, a packet of a transmission command includes a Command field, a Target ID_From field, a Source ID field, a Target ID_To field, a Target Address_From field, a Target Address_To field, and a Payload field . The names of the fields are illustrative, and the present invention is not limited thereto.

The command field defines the type of the packet. In the command field, information such as a read command, a write command, write data, and read data can be described. In the embodiment of FIG. 5, a command for transmitting data is described in the command field. As described above with reference to FIGS. 1 to 3, the data transfer command may be a command for transferring the 32 data stored in the first memory 1200 to the second memory 1300.

4, the ID of the network interface unit connected to the IP (for example, the first memory 1200) in which the data to be transferred is stored is described in the Target ID_From field. The source ID field describes the ID of the source network interface. In the Target ID_To field, the ID of the network interface unit connected to the IP (for example, the second memory 1300) to which data is to be transmitted is described. In the Target Address_From field, the address where data is stored in the IP where the data to be transmitted is stored is described. The Target Address_To field describes the address at which data is to be written in the IP to which data is to be transmitted. The payload field describes the read data or the write data.

That is, in the embodiment of FIGS. 4 and 5, information about the first memory 1200 will be described in the Target ID_From field and the Target Address_From field. In the source ID field, information about the processor 1100 will be described. In the Target ID_To field and the Target Address_To field, information about the second memory 1300 will be described.

Referring to Fig. 5, an exemplary embodiment of a transmission command packet is shown. By referring to the transmission command written in the command field, it can be seen that the packet of Fig. 5 is a packet of the transmission command. The packet is provided from the first network interface unit 1410 described in the source ID. That is, it can be seen that the transfer command is provided from the processor 1100 connected to the first network interface unit 1410. In addition, the packet defines a transfer command to transfer data from the second network interface unit 1420 described in the Target ID_From field to the third network interface unit 1430 described in the Target ID_To field. That is, data is transferred from the first memory 1200 connected to the second network interface unit 1420 to the second memory 1300 connected to the third network interface unit 1430 by the transfer command included in the packet.

5, the data is read from the address '0x00001000' of the first memory 1200 described in the Target Address_From field. For example, 32 pieces of data can be read out in order from the address '0x00001000' of the first memory 1200. The read data is written to the address '0x0000F000' of the second memory 1300 written in the Target Address_To field. The second network interface unit 1420 interprets the packet of the transmission command provided and generates a packet of the writing command shown in Figs. 6 and 7. The information described in the above-mentioned fields may be similarly applied to Figs.

6 and 7 are diagrams showing a packet format and an embodiment of the write command shown in FIG. 6 and 7 will be described with reference to FIG. Referring to FIG. 6, the packet of the write command may include a command field, a Target ID_To field, a source ID field, a Target Address_To field, and a write data field. The command field, the Target ID_To field, the source ID field, and the Target Address_To field are as described in FIGS.

In the write data field, data read from the address '0x00001000' of the first memory 1200 is written. 1, it is assumed that the burst length of the first memory 1200 is 1, and that the first memory 1200 includes one data pad. In the embodiment of FIGS. 4 and 5, one data read from the address '0x00001000' of the first memory 1200 may be written in the write data field. In order to provide all 32 data to the second memory 1300, the first memory 1200 generates 32 packets of the write command and provides it to the second memory 1300. Each of the 32 write command packets includes 32 data read out sequentially from the address '0x00001000'.

Referring to FIG. 7, an exemplary embodiment of a write command packet is shown. By referring to the write command written in the command field, it can be seen that the packet of Fig. 7 is a packet of the write command. The ID of the first network interface unit 1410 is described in the source ID field. The information in the source ID field can be used to set the destination of the packet of the write completion signal, which will be described in Figs.

The final destination of the packet is the third network interface unit 1430 described in the Target ID_To field. Referring to the information described in the packet of FIG. 7, the data included in the write data field is sequentially written to the address '0x0000F000' of the second memory 1300 described in the Target Address_To field. After the third network interface unit 1430 transmits all the 32 data to the second memory 1300, the third network interface unit 1430 generates the packet of the write completion signal shown in FIGS. 8 and 9 .

FIG. 8 and FIG. 9 are diagrams showing the packet format and the embodiment of the write completion signal shown in FIG. Referring to FIG. 8, the packet of the write completion signal may include a command field, a Target ID_To field, and a source ID field. The command field, Target ID_To field, and Source ID field are as described in FIGS.

Referring to FIG. 9, an exemplary embodiment of a packet of a write completion signal is shown. Referring to the write completion information written in the command field, it can be seen that the packet of Fig. 9 is a packet of a write completion signal. That is, the packet of the write completion signal of FIG. 9 includes information that the data transmission to the third network interface unit 1430 described in the Target ID_To field is completed. The final destination of the packet is the first network interface unit 1410 described in the source ID field. Referring to the source ID field, a packet of the write completion signal is transmitted to the first network interface unit 1410. Accordingly, the processor 1100 can receive feedback that the transfer command that was provided to the first and second memories 1200 and 1300 through the first network interface unit 1410 has been performed.

10 is a flowchart for explaining the operation of the second network interface unit shown in FIG. The second network interface unit 1420 receives the packet of the transmission command from the first network interface unit 1410 (S110). The information contained in the packet of the transfer command is provided to the first memory 1200. The first memory 1200 reads data from the address included in the information. The second network interface unit 1420 receives data read from the first memory 1200 (S120). The second network interface unit 1420 interprets the packet of the transmission command and generates a packet of the writing command based on the interpreted packet and the read data.

The second network interface unit 1420 transmits the packet of the write command to the third network interface unit 1430 (S130). In order to count the number of data transmitted through the packet of the write command, the second network interface unit 1420 increments the count of i by one (S140). Here, it is assumed that the initial value of i is 1.

The second network interface unit 1420 confirms whether i is greater than n (S150). n means the number of data to be transmitted. In the example shown in Figs. 4 to 9, the number of data to be transmitted is 32, so that n becomes 32. The assumptions for i and n apply equally to Fig. If i is less than or equal to n (NO direction), the second network interface unit 1420 performs step S120 again. When i is larger than n (Yes direction), the second network interface unit 1420 completes the operation of Fig. 10 because all the data has been transferred.

11 is a flowchart for explaining the operation of the third network interface unit shown in FIG. The third network interface unit 1430 receives the packet of the write command from the second network interface unit 1420 (S210). The third network interface unit 1430 transmits the data, the write command, and the address included in the packet of the received command to the second memory 1300 (S220). The second memory 1300 writes the transferred data in the memory cell corresponding to the provided address.

To count the number of received data, the third network interface unit 1430 increments the count of i by one (S230). The third network interface unit 1430 checks whether i is greater than n (S240). If i is less than or equal to n (No direction), the third network interface unit 1430 performs step S220 again. If i is greater than n (Yes direction), the third network interface unit 1430 performs step S250.

When i is larger than n, since n pieces of data have all been transferred from the first memory 1200 to the second memory 1300, the third network interface unit 1430 generates a packet of the write completion signal. The third network interface unit 1430 transmits the packet of the write completion signal to the first network interface unit 1410 (S250). According to the embodiment of Figs. 10 and 11, the electronic device 1000 of Fig. 3 transfers a plurality of data from the first memory 1200 to the second memory 1300. Fig.

The above description is specific embodiments for carrying out the present invention. The present invention will also include embodiments that are not only described in the above-described embodiments, but also can be simply modified or changed easily. In addition, the present invention will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

100, 1000: electronic device 110, 1100: processor
120, 1200: first memory 130, 1300: second memory
140: DMA unit 141: buffer
150, 1400: on-chip network 151, 1410: NIU1
152, 1420: NIU2 153, 1430: NIU3
154: NIU4

Claims (1)

In an operating method of an electronic device,
The electronic device includes an on-chip network coupled to the processor, a first memory coupled to the on-chip network, and a second memory coupled to the on-
The method of operation of the electronic device comprises:
Providing, in the processor, a data transfer command to the first memory device via the on-chip network;
Providing data read from the first memory to the second memory via the on-chip network in response to the data transfer command;
In the second memory, writing the provided data; And
And in the second memory, providing a data write completion signal to the processor over the on-chip network.

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