KR20180042871A - Organic Light Emitting Display Device And Driving Method Thereof - Google Patents

Abstract

The organic light emitting display of the present invention includes a display panel having a plurality of pixels; And a gate drive circuit for generating a scan control signal for sensing according to a gate shift clock for sensing in a display off interval and applying the generated scan control signal to pixels located on a pixel line to be sensed in the display panel, ; And a sensing unit for sensing the electrical characteristics of the pixels according to the sensing scan control signal to acquire sensing data, wherein the sensing gate shift clock includes a scan control signal for display for writing the input image data to the pixels, And is different from the gate shift clock for display required to generate a signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display and a driving method thereof.

An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, and has a high response speed, a high luminous efficiency, a high brightness and a wide viewing angle There are advantages.

The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form, and adjusts the brightness of an image implemented in pixels according to gray levels of image data. The driving TFT controls a driving current flowing in the OLED according to a voltage (hereinafter referred to as "gate-source voltage") applied between the gate electrode and the source electrode of the driving TFT. The light emission amount of the OLED is determined according to the driving current, and the brightness of the image is determined according to the amount of light emitted from the OLED.

In general, when the driving TFT operates in the saturation region, the driving current Ids flowing between the drain and the source of the driving TFT is expressed by the following equation (1).

[Equation 1]

Ids = 1/2 * (μ * C * W / L) * (Vgs-Vth) ²

In the equation (1), μ represents the electron mobility, C represents the capacitance of the gate insulating film, W represents the channel width of the driving TFT, and L represents the channel length of the driving TFT. Vgs represents the gate-source voltage of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT. According to the pixel structure, the gate-source voltage (Vgs) of the driving TFT can be the difference voltage between the data voltage and the reference voltage. Since the data voltage is an analog voltage corresponding to the gradation of the image data and the reference voltage is a fixed voltage, the gate-source voltage Vgs of the driving TFT is programmed (or set) according to the data voltage. Then, the drive current Ids is determined according to the programmed gate-source voltage Vgs.

The electrical characteristics of the pixel such as the threshold voltage Vth of the driving TFT, the electron mobility of the driving TFT, and the threshold voltage of the OLED are factors for determining the driving current Ids, Should be. However, electrical characteristics between the pixels may be varied due to various causes such as process characteristics, time-varying characteristics, and the like. Such electrical characteristic deviations cause a luminance deviation, which is a limitation on a desired image.

An external compensation technique for sensing electrical characteristics of a pixel and correcting digital data of an input image based on the sensing result is known in order to compensate for luminance deviation between pixels. In order for the luminance deviation to be compensated, a current change by? Y must be ensured when the data voltage applied to the pixel is changed by? X. Therefore, the external compensation technique is to realize the same brightness by calculating Δx for each pixel and applying the same driving current to the OLED. That is, the external compensation technique adjusts the gray level value to compensate for the brightness of each pixel.

Conventional external compensation techniques are performed in the power-on sequence period before the display driving starts, or in the power-off sequence period after the display driving is finished. If sensing and compensation are performed outside the display driving period, it is difficult to compensate for the change in the electrical characteristics of the pixel during the display driving in real time. Since the electrical characteristics of the driving TFT continue to change in the process of driving the display, it is necessary to compensate for the change in the electrical characteristics of the driving TFT in real time in order to improve the compensation performance.

Accordingly, it is an object of the present invention to provide an organic light emitting display device and a driving method thereof that can enhance compensation performance by sensing and compensating electrical characteristics of pixels in real time during the progress of display driving.

Other objects and advantages of the present invention will become apparent to those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an OLED display including: a display panel including a plurality of pixels; And a gate drive circuit for generating a scan control signal for sensing according to a gate shift clock for sensing in a display off interval and applying the generated scan control signal to pixels located on a pixel line to be sensed in the display panel, ; And a sensing unit for sensing the electrical characteristics of the pixels according to the sensing scan control signal to acquire sensing data, wherein the sensing gate shift clock includes a scan control signal for display for writing the input image data to the pixels, And is different from the gate shift clock for display required to generate a signal.

The display off period may include a first display period for displaying the first display period in the first group from the first stage where the gate start pulse is applied to the sensing stage to the sensing stage for outputting the sensing scan control signal, A first period for applying the clocks to sequentially drive the stages of the first group, and a second period for applying the carry signal from the sensing gate shift clock and the first group of stages to the sensing stage, And the second group of stages are sequentially driven by applying the gate shift clocks for display to the second group of stages from immediately after the sensing stage to the last stage.

And the input of the gate shift clocks for display to the gate driving circuit is stopped in the second period.

The sensing gate shift clock includes a first pulse and a second pulse following the first pulse.

The organic light emitting display of the present invention applies the black gradation data voltage to the pixels positioned in the pixel line to be sensed in the display panel in synchronization with the sensing gate shift clock of the first pulse, And a data voltage supply unit for applying a sensing data voltage in synchronization with the sensing gate shift clock to pixels located in a sensing target pixel line of the display panel.

Wherein the data voltage supply unit supplies the black gradation data voltage to the pixel located on the sensing target pixel line of the display panel in synchronization with the gate shift clock of the display having the fastest phase among the display gate shift clocks of the third period Lt; / RTI >

The display-off interval indicates a vertical blanking period in which no image data is written to the pixels.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting display, including: generating a scan control signal for sensing according to a gate shift clock for sensing in a display off interval and applying the generated scan control signal to pixels located in a pixel line to be sensed; And sensing the electrical characteristics of the pixels according to the sensing scan control signal to obtain sensing data, wherein the sensing gate shift clock includes a scan control signal for display for writing the input image data to the pixels, And is different from the gate shift clock for display required to generate a signal.

The present invention can enhance the compensation performance by sensing and compensating the electrical characteristics of the pixel in real time in the display off interval during the display driving.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram illustrating an organic light emitting display according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a data voltage supply unit, a sensing unit, and a connection configuration of a pixel according to an embodiment of the present invention.
3 is a diagram illustrating a data voltage supply unit, a sensing unit, and other connection structures of pixels according to an embodiment of the present invention.
4 is a diagram showing an internal configuration of a timing controller required for compensation.
5 is a view showing a display section in which an image is displayed and a display-off section in which real-time sensing is performed.
6 is a diagram illustrating a concept of performing real-time sensing in a vertical blanking period.
7 is a view showing an example of a pixel array suitable for reducing the size of a gate driving circuit.
Fig. 8 is a diagram showing one equivalent circuit of pixels constituting the pixel array of Fig. 7; Fig.
FIG. 9 is a diagram showing an exemplary configuration of a gate driving circuit for driving the pixel array of FIG. 7; FIG.
10 is a diagram showing waveforms of all signals for explaining a real-time sensing operation performed during a vertical blank period.
11 to 13 are diagrams showing various implementations of the external compensation module.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an organic light emitting display according to an exemplary embodiment of the present invention. 2 is a diagram illustrating a data voltage supply unit, a sensing unit, and a connection configuration of a pixel according to an embodiment of the present invention. 3 is a diagram illustrating a data voltage supply unit, a sensing unit, and other connection structures of pixels according to an embodiment of the present invention. 4 is a diagram showing an internal configuration of a timing controller required for compensation.

Referring to FIG. 1, an OLED display includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a memory 17. . ≪ / RTI >

The display panel 10 is provided with a plurality of pixels P, a plurality of data lines 14, a plurality of reference lines 15, and a plurality of gate lines 16.

The pixels P of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel P is connected to one of the data lines 14 to which the data voltage is supplied and to one of the reference lines 15 to which the reference voltage is supplied and to the gate lines 16 ). ≪ / RTI > Each pixel P is configured to receive a high potential driving power supply and a low potential driving power supply from a power generation unit. For example, the power generation section may supply the high potential driving power through the high potential drive power supply wiring or the pad part. And the low potential driving power can be supplied through the low potential driving power supply wiring or the pad portion.

In an embodiment, the OLED display may include at least one external compensation circuit. The external compensation circuit technology means a technique of sensing the electrical characteristics of the driving TFT and / or the OLED provided in the pixels P and correcting the input image data (DATA) according to the sensing value. For example, the external compensation circuit can be configured to sense the threshold voltage of the driving TFT and the electron mobility of the driving TFT by the electrical characteristics of the driving TFT, and compensate for the luminance deviation between the pixels P accordingly. The external compensation circuit may be configured to sense the threshold voltage of the OLED and compensate for the luminance deviation between the pixels P accordingly. The external compensation circuit may include a memory 17, a data voltage supply unit 20, a sensing unit 30, a timing controller 11, and the like.

The data driving circuit 12 includes a data voltage supply unit 20 for supplying a data voltage to the display panel 10 and may further include a sensing unit 30 for external compensation.

The data voltage supply unit 20 is connected to the pixels P through the data lines 14. [ The data voltage supply unit 20 includes a plurality of digital-to-analog converters (hereinafter, DAC). The data voltage supplier 20 converts digital image data DATA input from the timing controller 11 into data voltages for display through a digital-to-analog converter DAC and supplies the data voltages to the data lines 14 . The data voltage supply unit 20 generates a sensing data voltage through the digital-analog converter (DAC) under the control of the timing controller 11 in the sensing operation, and supplies the data voltage to the data lines 14. The sensing data voltage is a voltage applied to the gate electrode of the driving TFT provided in each pixel P during the sensing operation.

The sensing unit 30 is connected to the pixels P via the reference lines 15. [ The sensing unit 30 generates a reference voltage Vpre during display driving and supplies the reference voltage Vpre to the reference lines 15 according to a scan control signal for display. The sensing unit 30 senses the electric characteristics of the driving TFT and / or the OLED of the pixels P through the reference lines 15 according to a scan control signal for sensing at the time of sensing driving. The sensing unit 30 may be implemented as a voltage sensing type or a current sensing type.

The voltage sensing type includes a sample-and-hold circuit SH, an analog-to-digital converter (ADC) and first and second switches SW1 and SW2 as shown in Fig. The source electrode voltage of the TFT, that is, the source electrode voltage of the driving TFT stored in the line capacitor of the reference line 15 is sensed. The first and second switches SW1 and SW2 are selectively turned on. The first switch SW1 is a switch for supplying the reference voltage Vpre to the reference line 15 and the second switch SW2 is a switch for being turned on at the same time as the sensing operation. The ADC converts the sampled analog sensing values in the sample and hold circuit (SH) to digital sensing values (SD).

As shown in FIG. 3, the current sensing type further includes a current integrator at the front end of the sample-and-hold circuit to directly sense the driving current of the driving TFT flowing through the sensing line. Referring to FIG. 3, the current sensing type may include a current integrator and a sample and hold unit. The current integrator integrates the current information flowing through the reference line 15 to generate an analog sensing voltage. The current integrator includes an inverting input terminal (-) receiving the current of the driving TFT from the reference line 15, a non-inverting input terminal (+) receiving the reference voltage Vpre, and an amplifier AMP including an output terminal, An integral capacitor Cfb connected between the inverting input terminal (-) and the output terminal of the amplifier AMP and a reset switch RST connected to both ends of the integrating capacitor Cfb. The current integrator is connected to the ADC through a sample and hold section. The sample and hold unit includes a sampling switch SAM for sampling the analog sensing voltage output from the amplifier AMP and storing the sampled analog sensing voltage in the sampling capacitor Cs, a holding switch HOLD for transmitting the sensing voltage stored in the sampling capacitor Cs to the ADC, ). The ADC converts the sampled analog sensing values in the sample and hold section into digital sensing values (SD).

The gate drive circuit 13 generates a scan control signal for a display to be supplied to the gate lines 16 when the display is driven. The scan control signal for display is a signal synchronized with the supply timing of the display data voltage. The gate drive circuit 13 generates a scan control signal for sensing to be supplied to the gate lines 16 during the sensing operation. The sensing scan control signal is a signal synchronized with the supply timing of the sensing data voltage.

The gate drive circuit 13 includes a level shifter and a gate shift register.

The level shifter receives a control signal including a gate start pulse (Gate Start Pulse) and an N phase (N is an integer of 2 or more) gate shift clocks from the timing controller 11. The level shifter level shifts the TTL (Transistor-Transistor-Logic) logic level voltage of the control signal to a gate high voltage and a gate low voltage that can switch the TFT of the gate shift register. The level shifter supplies the level shifted gate start pulse, N phase gate shift clocks to the gate shift register.

The gate shift register includes stages for shifting a gate start pulse according to N phase gate shift clocks within a driving period determined according to a gate start pulse and sequentially outputting a scan control signal. The stages are connected to each other, the uppermost stage is activated by the gate start pulse, and the remaining stages can be activated according to the output signal (carry signal) of any of the preceding stages.

The gate shift register 14 may be formed directly on the lower substrate of the display panel 10 in a GIP (Gate In Panel) manner. In the GIP scheme, the level shifter can be mounted on the PCB. The gate shift register is formed in the non-display area (i.e., the bezel area) outside the pixel array in the display panel 10, and can be formed in the same TFT process as the pixel array.

The timing controller 11 receives image data DATA, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE from the application processor (or the host system) And the like. However, the present invention is not limited thereto.

The timing controller 11 outputs a data timing control signal DDC1 for controlling the operation timing of the data driving circuit 12 at the time of display driving and a data timing control signal DDC1 for controlling the operation timing of the data driving circuit 12 at the time of sensing driving, A gate timing control signal GDC1 for controlling the operation timing of the gate driving circuit 13 in driving the display and an operation timing of the gate driving circuit 13 in sensing driving, And to generate a gate timing control signal GDC2 for controlling the gate control signal GDC2.

The data timing control signals DDC1 and DDC2 include a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driving circuit 12. The source sampling clock is a clock signal that controls sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the data driving circuit 12.

The gate timing control signals GDC1 and GDC2 include a gate start pulse (Gate Start Pulse), an N-phase gate shift clock, and the like. The gate start pulse is applied to the stage of the gate driving circuit 13 which generates the first output to control the operation of the stage. The N-phase gate shift clock is a clock signal commonly input to the stages, and is a clock signal for shifting the gate start pulse. The N-phase gate shift clocks are composed of a combination of a display gate shift clock and a sensing gate shift clock. The sensing gate shift clock is generated in synchronization with a predetermined sensing timing.

The timing controller 11 can control the sensing drive for sensing the electrical characteristics of the pixel P and updating the compensated value thereof, and the display drive for displaying the input image with the compensation value reflected. For example, the timing controller 11 can be configured to separate the sensing drive and the display drive according to a predetermined control sequence. For this purpose, the timing controller 11 may generate timing control signals DDC1 and GDC1 for driving the display and timing control signals DDC2 and GDC2 for sensing driving differently. But is not limited thereto.

For example, by the control of the timing controller 11, the sensing drive can be performed in the display off period during the real time display drive. The display off period may be a vertical blank period. The vertical blanking period is a period during which input image data (DATA) is not written, and is arranged between display intervals (that is, vertical active intervals) in which input image data (DATA) for one frame is written. Compensating for changes in the electrical characteristics of pixels during real-time display driving increases the accuracy of compensation.

The display-off period is not limited to the vertical blanking period. For example, the timing controller 11 can detect a standby mode, a sleep mode, a low power mode, and the like according to a predetermined sensing process, and control all operations for sensing driving. That is, the sensing operation may be performed in a state where only the screen of the display device is turned off during the period in which the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like.

The timing controller 11 may further include a compensation coefficient calculation unit 40 and a data correction unit 50 as shown in FIG. 4 for data compensation. The compensation coefficient calculator 40 may calculate a compensation coefficient capable of compensating for a change in the electrical characteristic of the pixel P based on the digital sensing values SD inputted from the sensing unit 30 and store the compensation coefficient in the memory 17 have. The compensation factor may include offset and gain. The data correction unit 50 can correct the input image data DATA based on the offset and the gain stored in the memory 17. [ To this end, the data correction unit 50 may include a multiplier (MTX) and an adder (ADD). The multiplier (MTX) multiplies the input image data (DATA) by the gain. The adder ADD adds an offset to the input image data (DATA) multiplied by the gain. The data correction unit 50 may supply the corrected input image data DATA to the data driving circuit 20. [

On the other hand, the compensation coefficient calculating unit 40 and the data correcting unit 50 may be mounted outside the timing controller 11. [ As an example, the compensation coefficient calculating unit 40 and the data correcting unit 50 may be embedded in the application processor.

The memory 17 stores the compensation coefficient (offset, gain) calculated by the timing controller 11. [ The memory 50 may be implemented as a flash memory, but is not limited thereto.

5 is a view showing a display section in which an image is displayed and a display-off section in which real-time sensing is performed. 6 is a diagram showing a concept of performing real-time sensing in the vertical blank period.

5 and 6, according to the present invention, a display data voltage is sequentially written to all pixels of a display panel in accordance with a scan control signal for display within a display period DP within one frame, thereby displaying an image. According to the present invention, during a vertical blanking period (VB) excluding a display period (DP) in one frame, a data voltage for sensing is written in pixels arranged in a pixel line to be sensed according to a scan control signal for sensing, Sensing electrical characteristics. This real-time sensing is performed within the vertical blank period VB for the pixel line to be sensed. At this time, the pixel line to be sensed may include at least one pixel line per one frame. The pixel lines to be sensed may be sequentially selected in accordance with the data refresh order, i.e., the data scan direction), and may be selected in a non-sequential manner regardless of the data scan direction. Here, the electrical characteristics of the pixels include the threshold voltage and mobility of the driving TFT, the threshold voltage of the OLED, and the like.

7 is a diagram showing an example of a pixel array suitable for reducing the size of a gate driving circuit. Fig. 8 is a diagram showing one equivalent circuit of pixels constituting the pixel array of Fig. 7; Fig. 9 is a diagram showing an exemplary configuration of a gate drive circuit for driving the pixel array of FIG.

Referring to FIG. 7, the one pixel array of the present invention includes a plurality of pixel lines L1, L2, L3, and L4 of pixels P. In each of the pixel lines L1, L2, L3, and L4, horizontally adjacent pixels P are connected to different data lines 14, respectively. In each of the pixel lines L1, L2, L3 and L4, horizontally adjacent pixels P are connected to different reference lines 15 by M (M is a positive integer of 2 or more) .

8, horizontally adjacent pixels P may be connected to the first gate line 16A and the second gate line 16B in each of the pixel lines L1, L2, L3 and L4 . The first gate line 16A may be individually connected to each pixel line L1, L2, L3, L4 and the second gate line 16B may be shared with adjacent pixel lines. In other words, the first and second pixel lines L1 and L2 may share one second gate line 16B, and the third and fourth pixel lines L3 and L4 may share another one of the second The gate line 16B can be shared. By designing the pixel array so as to share some gate lines, the aperture ratio of the display panel can be increased, and the gate drive circuit can be simplified to reduce the area of the bezel where the gate drive circuit is mounted.

Referring to FIG. 8, each of the pixels P constituting the pixel array includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, And a TFT (ST2). The pixel configuration in Fig. 8 is merely an example, and the technical idea of the present invention is not limited to the pixel configuration.

The OLED has an anode electrode connected to the first node N1 of the gate electrode of the driving TFT DT, a cathode electrode connected to the input terminal of the low-potential driving voltage VSS, and a cathode electrode connected between the anode electrode and the cathode electrode. .

The driving TFT DT controls the current input to the OLED according to the gate-source voltage Vgs. The driving TFT DT has a gate electrode which is a first node N1, a drain electrode which is connected to an input terminal of a high potential driving voltage VDD and a source electrode which is a second node N2. The storage capacitor Cst is connected between the first node N1 and the second node N2. The first switch TFT ST1 applies the data voltage Vdata on the data line 14 or the data voltage Vdata_SEN for sensing to the first node N1 in response to the first scan control signal SCAN1. The first switch TFT (ST1) has a gate electrode connected to the first gate line 16A, a drain electrode connected to the data line 14, and a source electrode connected to the first node N1. The second switch TFT (ST2) switches the current flow between the second node (N2) and the reference line (15) in response to the second scan control signal (SCAN2). The second switch TFT (ST2) has a gate electrode connected to the second gate line 16B, a drain electrode connected to the reference line 15, and a source electrode connected to the second node N2.

9, the gate driving circuit 13 according to an embodiment of the present invention includes a first scan driver 13A (first scan driver) for generating a first scan control signal SCAN1 to be supplied to the first gate lines 16A, And a second scan driver 13B for generating a second scan control signal SCAN2 to be supplied to the second gate lines 16B.

More specifically, the gate driving circuit 13 includes a first scan driver 13A having stages (SCAN1-STG1 to SCAN1-STG2100) as the pixel lines (L1 to L2100) of the pixel array, And a second scan driver 13B having stages (SCAN2-STG1 to SCAN1-STG1050) of half the number of stages (L1 to L2100).

SCAN1-DUM, SCAN2-DUM, EM-DUM, SCAN1-MNT, SCAN2-MNT and EM-MNT mean dummy stages. L Dummy indicates a dummy pixel line. VGH, VEH and VGL applied to the stages indicate the driving power. But is not limited thereto, and the dummy stage may optionally be included or excluded. The dummy stage and the dummy pixel lines may be arranged in the first outline (upper side) and the second outline (lower side) of the pixel array. Or the signal of the pixel line adjacent to the dummy pixel line can be stabilized by the dummy stage and the dummy pixel line of the pixel array. This can help to reduce kickback of adjacent pixel lines. The pixel of the dummy pixel line is similar to the pixel (P) of the pixel array, but does not emit light. That is, the dummy pixel line is configured not to include at least the OLED, or the data voltage is configured to be unauthorized or not to receive the scan control signal.

The first scan driver 13A generates a first scan control signal SCAN1 for display according to the gate control signal GDC during the display driving and generates a first scan control signal SCAN1 for sensing according to the gate control signal GDC, And a shift register for generating the signal SCAN1. The first scan control signal SCAN1 for display and the first scan control signal SCAN1 for sensing may be different.

For example, each of the stages SCAN1-STG1 to SCAN1-STG2100 constituting the first scan driver 13A may be individually connected to one pixel line. Each of the stages SCAN2-STG1 to SCAN1-STG1050 constituting the second scan driver 13B may be commonly connected to two pixel lines. The present invention is advantageous in that a narrow bezel can be realized by reducing the number of stages of the second scan driver 13B to half the number of stages of the first scan driver 13A.

The stages SCAN1-STG1 to SCAN1-STG2100 of the first scan driver 13A successively shift the first gate start pulse G1Vst according to the first gate shift clock group G1CLK1 to G1CLK4, 1 scan control signal SCAN1 or a first scan control signal SCAN1 for sensing.

The second scan driver 13B generates a second scan control signal SCAN2 according to the gate control signal GDC during the display driving and generates a second scan control signal for sensing according to the gate control signal GDC SCAN2). ≪ / RTI > The second scan control signal SCAN2 for display driving and the second scan control signal SCAN2 for sensing may be different.

For example, the stages SCAN2-STG1 to SCAN2-STG1050 of the second scan driver 13B sequentially shift the second start pulse G2Vst in accordance with the second gate shift clock group G2CLK1 to G2CLK4, And generates a second scan control signal SCAN2 for display or a first scan control signal SCAN2 for sensing.

10 is a diagram showing waveforms of all signals for explaining a real-time sensing operation performed during a vertical blank period.

Referring to FIG. 10, the first gate shift clocks G1CLK1 to G1CLK4 applied to the gate driving circuit 13 include gate shift clocks for display and gate shift clocks for sensing. The gate shift clocks for display and the gate shift clock for sensing are also included in the second gate shift clock group (G2CLK1 to G2CLK4).

The sensing gate shift clock for generating the sensing scan control signal is different from the gate shift clock for display for generating the scan control signal for display. Each of the gate shift clocks for display is implemented as a single pulse having the same pulse width, while the gate shift clock for sensing may be composed of a combination of the first pulse P1 and the second pulse P2 successively. The pulse widths of the first pulse P1 and the second pulse P2 may be the same or different from each other.

The display off interval (i.e., the vertical blank interval VB) in which the real-time sensing operation is performed may include a first period X1, a second period X2, and a third period X3.

The first period X1 is a period during which stages connected to the previous stage of a specific stage (hereinafter, referred to as a sensing stage) for driving the pixel line to be sensed are driven to search the pixel line to be sensed. In the first period X1, by applying the gate shift clocks for display to the first group of stages from the first stage where the gate start pulses G1Vst and G2Vst are applied to the sensing stage before the sensing scan control signal is outputted The stages of the first group are sequentially driven.

The second period X2 is a period for driving the sensing stage for driving the pixel line to be sensed. In the second period X2, a sensing gate shift clock and a carry signal from any one of the stages of the first group are applied to the sensing stage to generate the sensing scan control signal. In the second period X2, the gate shift clocks for display are not inputted to the gate drive circuit.

The sensing operation is performed according to the sensing scan control signal generated in the second period X2. The sensing scan control signal is synchronized with the sensing gate shift clock of the first pulse P1 and the sensing gate shift clock of the second pulse P2.

In the second period X2, the data voltage supply unit supplies the black gradation data voltage Vdata_black to the pixels positioned in the pixel line to be sensed in the display panel in synchronization with the gate shift clock for sensing the first pulse P1 , The potential of the second node (the source electrode voltage of the driving TFT) of the reference line and the pixels can be initialized prior to sensing. Then, the data voltage supply unit may apply the sensing data voltage (Vdata_SEN) to the pixels located on the sensing target pixel line of the display panel in synchronization with the sensing gate shift clock of the second pulse (P2). The sensing unit senses electrical characteristic values of pixels according to a sampling (SEN) signal, and converts the sensed analog sensing voltage into sensing data through the ADC.

The third period X3 is a period for initializing the gate driving circuit by driving all of the remaining stages after the sensing stage so that normal display driving is realized in the next frame. If there is no operation in the third period X3, the gate drive circuit may not operate normally during the display driving of the next frame, and two scan control signals may be generated at the same time. In order to prevent this, in the third period (X3), gate shift clocks for display are applied to the second group of stages from immediately after the sensing stage to the last stage, and the stages of the second group are sequentially driven.

In the third period (X3), the data voltage supplier supplies the black gradation data voltage (Vdata_black) or the original display data voltage (Vdata_black) in synchronization with the gate shift clock for the display having the highest phase among the gate shift clocks for display during the third period Vdata_RC) to the pixels positioned on the pixel line to be sensed in the display panel, thereby preventing the OLEDs of the pixel line to be sensed from being unnecessarily emitted in the display-off period.

The third period X3 is started with the source electrode voltage of the driving TFT being sufficiently high by the driving current flowing in the driving TFT of each pixel during the second period X2. Therefore, the potential of the second node provided in the pixels in the third period X3 is the same as the black gradation data voltage Vdata_black applied to the gate electrode of the driving TFT, that is, the first node, (Vdata_RC), the driving TFT is turned off during the third period (X3), and the OLEDs of the pixel line to be sensed can be prevented from unnecessary light emission.

11 to 13 are diagrams showing various implementations of the external compensation module.

11, the OLED display of the present invention includes a driver IC (DIC) mounted on a chip on film (COF), a flexible printed circuit board , A storage memory and a power IC (PIC) mounted on a flexible printed circuit board (FPCB), and a host system mounted on a system printed circuit board (SPCB).

The driver IC (DIC) includes the sensing unit, the control unit, the compensation unit, and the compensation memory, which are the above-described source driver 12 and the timing controller 11, which are formed as a single chip. The control unit calculates a compensation coefficient for compensating a change in the electrical characteristics of the pixel based on the digital sensing values input from the sensing unit during sensing operation, and stores the compensation coefficient in a storage memory. The control unit generates various control signals necessary for the operation of the gate driver. The compensation unit reads the compensation parameter from the storage memory at the time of driving the display, stores it in the compensation memory, and corrects the digital data of the input image based on the compensation parameter. The control unit and the compensation unit correspond to the timing controller 11 described above. The storage memory is implemented as a ROM (Read Only Memory), and may be, for example, a flash memory. The compensation memory may be implemented as a random access memory (RAM), for example, a DDR SDRAM (Double Date Rate Synchronous Dynamic RAM).

The power IC (PIC) generates various driving power required for operating the module.

The host system outputs the digital data of the input image to the driver IC (DIC) together with the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE, Lt; / RTI > The host system may be replaced by an application processor.

12, the OLED display of the present invention includes a driver IC (DIC) mounted on a chip-on-film (COF), a storage memory mounted on a flexible printed circuit board (FPCB) A power supply IC (PIC), and a host system mounted on a system print substrate (SPCB). The external compensation module in Fig. 12 is different from Fig. 11 in that the compensation unit and the compensation memory are mounted on the host system without being mounted on the driver IC (DIC). The external compensation module of FIG. 12 is meaningful in that the structure of the driver IC (DIC) is simplified.

Referring to FIG. 13, the organic light emitting diode display of the present invention includes a source IC (SIC) mounted on a chip on film (COF), a storage memory mounted on a flexible printed circuit (FPCB) A compensation IC, a compensation memory and a power IC (PIC), and a host system mounted on a system printed substrate (SPCB). In the external compensation module of Fig. 13, only the sensing part is mounted on the source IC (SIC) to further simplify its configuration, and the control part and the compensation part are mounted on a compensation IC manufactured separately. The compensation IC, the storage memory, and the compensation memory are mounted together on the flexible printed circuit board (FPCB) to facilitate the up-loading and down-loading operations of the compensation parameter.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
20: Data voltage supply unit 30:

Claims (14)

A display panel having a plurality of pixels;
And a gate drive circuit for generating a scan control signal for sensing according to a gate shift clock for sensing in a display off interval and applying the generated scan control signal to pixels located on a pixel line to be sensed in the display panel, ; And
And a sensing unit for sensing the electrical characteristics of the pixels according to the sensing scan control signal to acquire sensing data,
Wherein the sensing gate shift clock is different from the gate shift clock for display necessary for generating a scan control signal for display for writing input image data into the pixels. The method according to claim 1,
The display-
The display gate shift clocks are applied to the first group of stages from the first stage to which the gate start pulse is applied to the sensing stage to the sensing stage to output the sensing scan control signal, A first period for sequentially driving the first group of stages,
A second period for applying the sensing gate shift clock and the carry signal from any one of the first group of stages to the sensing stage to generate the sensing scan control signal,
And a third period in which the gate shift clocks for display are applied to the second group of stages from immediately after the sensing stage to the last stage to sequentially drive the stages of the second group. 3. The method of claim 2,
And the input of the gate shift clocks for display is stopped in the gate driving circuit in the second period. 3. The method of claim 2,
Wherein the sensing gate shift clock includes a first pulse and a second pulse following the first pulse. 5. The method of claim 4,
Applying a black gradation data voltage to pixels located in a pixel line to be sensed in the display panel in synchronization with the sensing gate shift clock of the first pulse,
And a data voltage supply unit for applying a sensing data voltage to pixels positioned in a sensing target pixel line of the display panel in synchronization with the sensing gate shift clock of the second pulse. 6. The method of claim 5,
Wherein the data voltage supply unit supplies the black gradation data voltage to the pixel located on the sensing target pixel line of the display panel in synchronization with the gate shift clock of the display having the fastest phase among the display gate shift clocks of the third period To the organic light emitting display device. The method according to claim 1,
Wherein the display off interval indicates a vertical blanking period in which no image data is written to the pixels. Generating a scan control signal for sensing according to a gate shift clock for sensing in a display off interval and applying the generated scan control signal to pixels located in a pixel line to be sensed in a display panel; And
And sensing the electrical characteristics of the pixels according to the sensing scan control signal to obtain sensing data,
Wherein the sensing gate shift clock is different from a gate shift clock for display necessary for generating a scan control signal for display for writing input image data into the pixels. 9. The method of claim 8,
The display-
The display gate shift clocks are applied to the first group of stages from the first stage to which the gate start pulse is applied to the sensing stage to the sensing stage to output the sensing scan control signal, A first period for sequentially driving the first group of stages,
A second period for applying the sensing gate shift clock and the carry signal from any one of the first group of stages to the sensing stage to generate the sensing scan control signal,
And a third period in which the gate shift clocks for display are applied to the second group of stages from immediately after the sensing stage to the last stage to sequentially drive the stages of the second group . 10. The method of claim 9,
And the input of the gate shift clocks for display is stopped in the second period. 10. The method of claim 9,
Wherein the sensing gate shift clock includes a first pulse and a second pulse following the first pulse. 12. The method of claim 11,
Applying a black gradation data voltage to pixels located in a pixel line to be sensed in the display panel in synchronization with the sensing gate shift clock of the first pulse; And
And applying a sensing data voltage to pixels located in a sensing target pixel line of the display panel in synchronization with the sensing gate shift clock of the second pulse. 10. The method of claim 9,
The step of applying the black gradation data voltage to the pixels located in the pixel line to be sensed in the display panel in synchronization with the gate shift clock of the display having the highest phase among the display gate shift clocks in the third period Wherein the organic light emitting display device further comprises: 9. The method of claim 8,
Wherein the display off interval indicates a vertical blanking period during which no video data is written to the pixels.

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