KR20170140624A - Display Device Including Power Supplying Part - Google Patents

Abstract

Provided is a liquid crystal display apparatus comprising: a display panel; a gate driving part; a data driving part; a timing control part; and a power supply part. According to the present invention, heat generation is reduced, deterioration is prevented, and power consumption is reduced by providing a gate control signal to the power supply part from the timing control part to control a switching operation of the power supply part.

Description

A display device including a power supply unit (Display Device Including Power Supply Part)

The present invention relates to a display apparatus, and more particularly to a display apparatus including a power supply unit that minimizes a switching operation according to a gate control signal of a timing control unit, thereby reducing heat generation and reducing power consumption.

As the information society has developed in recent years, the demand for the display field has been increasing in various forms. In response to this demand, various flat panel displays (FPDs) having characteristics such as thinning, light weight, and low power consumption have been developed, A liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been studied.

Such a display device includes a display panel for displaying an image and a driver for supplying a drive signal to the display panel, and the driver includes a timing controller, a gate driver, a data driver and a power supply.

Here, the power supply unit supplies the gate high voltage and the gate low voltage to the gate driving unit, and the gate driving unit generates the gate signal using the gate high voltage and the gate low voltage and supplies the gate signal to the display panel. .

1 is a timing diagram of input / output signals of a driver of a conventional display device.

Although not shown, a driving unit of a conventional display device includes a timing control unit, a gate driving unit, a data driving unit, and a power supply unit.

The timing control section generates a gate output enable (GOE) indicating the output timing of the gate driving section and supplies it to the gate driving section.

The gate driver generates a plurality of gate signals VG1, VG2 and VG3 synchronizing with the gate output enable GOE using the gate high voltage VGH and the gate low voltage VGL, And sequentially supplies signals VG1, VG2, and VG3 to the display panel.

At this time, the gate output enable GOE has a high level for the first time period TP1 and a low level for the second time period TP2, and the gate signals VG1, VG2, and VG3 are the gate output enable (GOE) has a gate high voltage (VGH) in synchronization with one of the second time period (TP2) which is a low level and has a gate low voltage (VGL) during the remaining time period.

The power supply unit generates the gate high voltage VGH and supplies it to the gate driving unit. Specifically, the gate high voltage output signal I_VGH output from the power supply unit

Has a low level for one time period TP1 and a high level for a second time period TP2.

In this conventional display device, the power supply unit continuously performs the switching operation in accordance with the gate high voltage switching signal S_VGH in order to keep the output gate high voltage VGH constant, and the gate high voltage output signal I_VGH, The gate high voltage switching signal S_VGH has a high level even during the first time period TP1 in which the gate signals VG1, VG2 and VG3 have low levels and the power supply unit performs the switching operation do.

That is, when the gate high voltage VGH is not outputted from the power supply unit and the gate signals VG1, VG2 and VG3 of the gate high voltage VGH are not outputted from the gate driving unit and the gate high voltage VGH is not generated Since the power supply unit performs the switching operation even during the first time period TP1, there is a problem that the power supply unit unnecessarily operates to increase the heat generation and power consumption of the power supply unit and increase the deterioration.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display apparatus including a power supply unit that improves the efficiency of a switching operation by controlling a switching operation using a gate output enable .

It is another object of the present invention to provide a display device including a power supply portion for reducing the heat generation and reducing power consumption by stopping the switching operation for a time period during which no gate high voltage is supplied.

According to an aspect of the present invention, there is provided a display device including a display panel for displaying an image, a gate driver and a data driver for supplying a gate signal and a data signal to the display panel, A timing controller for supplying the data driver with the video data and the data control signal and a power supply for generating a gate high voltage using the gate control signal and supplying the gate high voltage to the gate driver, Device.

The timing control unit generates a gate output enable signal, which is one of the gate control signals, and supplies the gate output enable signal to the power supply unit and the gate driving unit.

The power supply unit supplies a first time period TP1 in which the gate output enable signal GOE has a high level and the gate high voltage output signal I_VGH has a low level and the gate signals VG1, VG2, and VG3 have a low level, (GOE) is at a low level and the gate high voltage output signal I_VGH is at a low level

And performs the switching operation only during the second time period TP2 having the evelay and having the gate signals VG1, VG2, and VG3 at the high level.

The present invention has an effect that the efficiency of the switching operation is improved by controlling the switching operation using the gate output enable.

The present invention has the effect of reducing the heat generation and reducing power consumption by stopping the switching operation for a time period during which the gate high voltage is not supplied.

1 is a timing diagram of input / output signals of a driver of a conventional display device.
2 shows a display device according to an embodiment of the present invention.
3 is a view showing a power supply unit of a display device according to an embodiment of the present invention.
4 is a timing diagram of input / output signals of a driver of a display device according to an embodiment of the present invention.

2 is a view showing a display device according to an embodiment of the present invention.

2, the display device according to the embodiment of the present invention includes a display panel 118, a gate driving unit 110, a data driving unit 112, a timing control unit 114, and a power supply unit 116 The gate driving unit 110, the data driving unit 112, the timing control unit 114, and the power supply unit 116 constitute a driving unit.

The display panel 118 displays an image using the gate signal and the data signal.

Such a display panel may be a liquid crystal panel or an organic light emitting diode panel.

The liquid crystal panel may include a first substrate on which a gate wiring, a data wiring, a thin film transistor, and a pixel electrode are formed, a second substrate on which a common electrode is formed, and a liquid crystal layer between the pixel electrode and the common electrode.

Here, the gate wiring and the data wiring intersect each other to define a pixel region, and the thin film transistor of each pixel region is connected to the gate wiring and the data wiring, and the pixel electrode of each pixel region can be connected to the thin film transistor.

The organic light emitting diode panel may include a first substrate including a gate wiring, a data wiring, a power wiring, a switching thin film transistor, a driving thin film transistor and a light emitting diode, and a second substrate which is an encapsulation substrate.

Here, the gate wiring, the data wiring and the power wiring intersect each other to define a pixel region, and the switching thin film transistor of each pixel region is connected to the gate wiring and the data wiring, and the driving thin film transistor of each pixel region is composed of a switching thin film transistor and power And the light emitting diode can be connected to the driving thin film transistor.

The gate driver 110 generates a gate signal using a plurality of gate control signals, and supplies the generated gate signal to the display panel 118.

The data driver 112 generates a data signal using the image data and a plurality of data control signals, and supplies the generated data signal to the display panel 118.

The gate driver 110 and the data driver 112 may be formed as a plurality of driving integrated circuits (D-ICs), and the plurality of driving integrated circuits may be formed on a chip on glass (COG) The display panel 118 may be mounted on the display panel 118. [

The timing controller 114 receives a plurality of control signals such as a video signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from an external system (not shown) such as a graphic card or a television system, And supplies the generated image data and the data control signal to the data driver 112, and supplies the generated gate control signal to the gate driver 110. The gate driver 110 supplies the gate driver 110 with the image data, the data control signal, and the gate control signal.

For example, the gate control signal generated by the timing controller 114 includes a gate output enable (GOE), a gate start pulse (GSP), and a gate shift clock (GSC).

The gate output enable GOE serves to indicate the output timing of the gate driver 110 and the gate start pulse GSP serves to indicate the timing of the start line of the picture, And the gate shift clock GSC serves to indicate the turn-on timing of the thin film transistor of the display panel 118. [

The power supply unit 116 generates a plurality of driving voltages using the power control signal and supplies the generated driving voltages to the timing controller 114, the data driver 112, the gate driver 110, and the display panel 118.

This power supply 116 may be in the form of a power supply control integrated circuit (PMIC) using a booster converter scheme, for example, the power supply control integrated circuit may boost or reduce the input voltage provided from an external system A gate high voltage VGH and a gate low voltage VGL can be generated in accordance with the digital logic voltage VCC, the high potential voltage VDD, the common voltage VCOM, the gamma reference voltage GMA,

Here, the high-potential voltage VDD may be used as the voltage corresponding to the highest gradation or the lowest gradation of the data signal, the gamma reference voltage GMA may be used as the voltage corresponding to the intermediate gradations of the data signal, The voltage VGH can be used as the high level of the gate signal, and the gate low voltage VGL can be used as the low level of the gate signal.

The power supply 116 supplies the gate high voltage VGH and the gate low voltage VGL which turn-on and turn-off the pixel thin film transistor of the display panel 118, And supplies it to the gate driver 110.

In particular, the power supply unit 116 receives the gate output enable (GOE) of the gate control signal generated by the timing control unit 114 and uses it for outputting the gate high voltage VGH.

That is, the power supply unit 116 stops the switching operation in synchronization with the high level period of the gate output enable (GOE), thereby reducing the heat generation in the section in which the current of the gate high voltage VGH is not generated, Which will be described in detail with reference to the drawings.

FIG. 3 is a view showing a power supply unit of a display device according to an embodiment of the present invention, and FIG.

As shown in FIG. 3, the power supply unit includes a power supply integrated circuit 120 and a booster converter 122.

The booster converter 122 includes an inductor L1, a switching element Q1, a reflux diode D1, a capacitor C1 and a resistor R1.

The power supply integrated circuit 120 generates the gate high voltage switching signal S_VGH, point a in synchronization with the gate output enable GOE and supplies the generated gate high voltage switching signal S_VGH, point a to the switching element Q1 .

More specifically, when the switching element Q1 is turned on according to the gate high voltage switching signal (S_VGH, point a), energy is stored in the inductor Ll, the charge stored in the capacitor C1 is discharged, When the device Q1 is turned off, the energy stored in the inductor L1 and the input voltage Vi are added to the voltage across the capacitor C1 and output as the gate voltage output signal I-VGH.

4 is a timing diagram of input / output signals of a driver of a display device according to an embodiment of the present invention, which will be described with reference to FIGS. 2 and 3. FIG.

As shown in FIG. 4, the timing controller 114 generates a gate output enable (GOE), which is one of the gate control signals, and supplies the gate output enable signal GOE to the power supply unit 116 and the gate driving unit 110.

Here, the gate output enable GOE has a high level for the first time period TP1 and a low level for the second time period TP2.

The gate driving unit 110 uses a gate high voltage VGH and a gate low voltage VGL to generate a gate output enable signal GOE, a gate start pulse GSP, a plurality of gate synchronizing clocks GSC And sequentially supplies the generated gate signals VG1, VG2, and VG3 to the display panel 118. The gate signals VG1, VG2,

Here, the gate signals VG1, VG2 and VG3 have a gate high voltage VGH in synchronization with one of the second time periods TP2 in which the gate output enable GOE is low level, Voltage VGL.

Also, the power supply unit 116 generates the gate high voltage VGH using the gate output enable (GOE) and supplies it to the gate driver 110. [

Specifically, the gate high voltage output signal I_VGH output from the power supply unit 116 has a low level during the first time period TP1 and a high level during the second time period TP2.

Here, the power supply unit 116 continuously performs the switching operation according to the gate high voltage switching signal S_VGH in order to keep the output gate high voltage VGH constant, and the power supply unit 116 supplies the gate output enable By generating the gate high voltage switching signal S_VGH using the gate high voltage switching signal GOE and the gate high voltage switching signal S_VGH during the first time period TP1 in which the gate output enable GOE is high level The gate high voltage switching signal S_VGH has a high level during the second time period TP2 in which the gate output enable signal GOE is at the low level.

Therefore, the power supply integrated circuit 120 of the power supply unit 116 has the gate output enable (GOE) of the high level and the gate high voltage output signal I_VGH of the low level and the gate signals VG1, VG2, and VG3 The switching operation is stopped during the first time period TP1 having the low level and the gate output enable signal GOE has the low level and the gate high voltage output signal I_VGH has the high level and the gate signals VG1, VG3) has a high level during the second time period TP2.

That is, in the display apparatus according to the embodiment of the present invention, the gate high voltage VGH is not outputted from the power supply unit 116 and the gate signals VG1, VG2, VG3 of the gate high voltage VGH from the gate driving unit 110 The power supply integrated circuit 120 of the power supply unit 116 stops the switching operation during the first time period TP1 during which the current of the gate high voltage VGH is not generated, Unnecessary operations are eliminated, heat generation is reduced, deterioration is prevented, and consequently power consumption is reduced.

110: Gate driver 112: Data driver
114: timing control unit 116: power supply unit
118: Display panel VGH: Gate high voltage
VGL: Gate low voltage GOE: Gate output enable

Claims (7)

A display panel for displaying an image;
A gate driver and a data driver for supplying a gate signal and a data signal to the display panel, respectively;
A timing controller for supplying a gate control signal to the gate driver and supplying the video data and the data control signal to the data driver;
Generating a gate high voltage using the gate control signal, and supplying the gate high voltage to the gate driver,
.
The method according to claim 1,
Wherein the gate control signal includes a gate output enable, a gate start pulse, and a gate shift clock.
3. The method of claim 2,
Wherein the power supply generates the gate high voltage using the gate output enable. The method of claim 3,
The gate output enable having a high level for a first time interval and a low level for a second time interval,
Wherein the power supply unit stops the switching operation for keeping the gate high voltage constant for the first time period in synchronization with the gate output enable and for switching the display device .
5. The method of claim 4,
And the power supply unit includes a power supply integrated circuit performing the switching operation to generate a gate high voltage switching signal.
6. The method of claim 5,
Wherein the gate high voltage switching signal has a low level during the first time period and a high level during the second time period.
The method of claim 3,
And the gate driver generates the gate output enable signal, the gate start pulse, and the gate signal synchronized with the gate shift clock signal by using the gate high voltage.

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