KR20170088261A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a fin-shaped pattern protruding from a substrate and extended in a first direction, first and second gate electrodes extended in parallel to each other in a second direction crossing the first direction on the fin-shaped pattern, a recess formed in the fin-shaped pattern between the first and second gate electrodes, and a source/drain which fills the recess and includes a first region and a second region formed on both sides of the first region. The thickness of the first region is smaller than the thickness of the second region. The driving characteristic of the semiconductor device can be improved.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

The present invention relates to a semiconductor device and a manufacturing method thereof.

As one of scaling techniques for increasing the density of semiconductor devices, there is a scaling technique for forming a fin body or a nanowire-shaped silicon body on a substrate and forming a gate on the surface of the silicon body (multi gate transistors have been proposed.

Since such a multi-gate transistor uses a three-dimensional channel, scaling is easy. Further, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

A problem to be solved by the present invention is to provide a semiconductor device with improved operational characteristics.

Another problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device with improved operating characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a pin-shaped pattern protruding from a substrate and extending in a first direction; a pin-like pattern protruding from the substrate in a second direction crossing the first direction; And a recess formed in the fin-shaped pattern between the first and second gate electrodes and filling the recess, wherein the first region and the second region are formed on both sides of the first region, 2 region, wherein a thickness of the first region is smaller than a thickness of the second region.

The top surface of the second region may be higher than the top surface of the first region.

The lower surface of the second region may be lower than the lower surface of the first region.

The recess may comprise first downwardly convex dimples and second downwardly convex dimples.

And a convex portion convex upwardly between the first and second dimples.

The first and second dimples may be located on the opposite side with respect to the first region, and the first and second dimples may overlap with the second region.

The source / drain may comprise Si: P.

The upper surfaces of the first and second regions may be flat.

The source / drain may comprise SiGe.

The top of the second region may be higher than the bottom of the first and second gate electrodes.

The lowermost portion of the first region may be lower than the lower surface of the first and second gate electrodes.

The lowermost portion of the first region may be higher than the lower surface of the first and second gate electrodes.

The lower surface of the second region may be U-shaped.

The inclination of the lower surface of the source / drain may be continuous.

According to an aspect of the present invention, there is provided a semiconductor device including a first fin-shaped pattern protruding from a substrate and extending in a first direction, a second fin-shaped pattern extending in a second direction crossing the first direction on the first fin- First and second gate electrodes extending in parallel to each other, a first recess formed in the fin-shaped pattern between the first and second gate electrodes, the bottom surface of the first recess having a first And a first source / drain that fills the recess and includes a top dimple downwardly convex on the top surface, the first recess including a second dimple and a convex located between the first and second dimples.

Wherein the substrate has a first fin-shaped pattern formed on the first region and a second fin-shaped pattern formed on the second region, the second fin-shaped pattern including first and second regions, Third and fourth gate electrodes intersecting the first gate electrode and the second gate electrode and extending parallel to each other and a second recess formed in the pinned pattern between the third and fourth gate electrodes, A second recess that does not include a convex portion, and a second source / drain that fills the second recess.

The spacing between the first and second gate electrodes may be greater than the spacing between the third and fourth gate electrodes.

The upper surface of the second source / drain may be convex upward.

The upper surface of the second source / drain may be flat.

The source / drain may include a first region and a second region formed on both sides of the first region, and the top dimple may be formed in the first region.

The top surface of the second region may be higher than the top surface of the first region.

The first regions may have first and second side surfaces which are opposite to each other and the heights of the upper surface of the second region contacting the first side surface and the height of the upper surface of the second region contacting the second side surface may be different from each other.

The height of the lowermost portion of the first and second dimples may be the same.

The slopes of the surfaces of the first and second dimples may be continuous.

The inclination of the surface of the convex portion may be continuous.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including first and second regions, a first finned pattern formed on the first region, a first finned pattern formed on the second region, A second fin-shaped pattern, first and second gate electrodes crossing the first fin-shaped pattern on the first fin-shaped pattern, third and fourth gate electrodes crossing the second fin-shaped pattern on the second fin- A first recess formed between the first and second gate electrodes, the first recess being formed on the first fin-shaped pattern, the first recess being downwardly convex on the bottom surface, the first recess formed between the third and fourth gate electrodes, A second recess formed on the second fin-shaped pattern and including third and fourth dimples convex down on the bottom surface, a first recess filling the first recess, and a top dimple downwardly convex on the top surface The first source / drain and the second recess are filled, And a second source / drain having a flat upper surface.

The first recess may include a first convex portion formed between the first and second dimples, and the second recess may include a second convex portion formed between the third and fourth dimples.

The first distance between the lowermost part of the surface of the first and second dimples and the uppermost part of the surface of the first convex part is the second distance between the lowermost part of the surfaces of the third and fourth dimples and the uppermost part of the surface of the second convex part, .

The depth of the first recess may be less than the depth of the second recess.

The width of the first recess may be smaller than the width of the second recess.

The top surface of the first source / drain may be higher than the bottom surface of the first and second gate electrodes, and the top surface of the second source / drain may be the same as the bottom surface of the third and fourth gate electrodes.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a fin-shaped pattern protruding on a substrate and extending in a first direction; Forming a gate electrode extending in a second direction and etching the pin-shaped pattern on at least one side of the gate electrode to form a recess, the recess including first and second dimples convex downward, Forming a source / drain filling the sce, wherein the source / drain comprises a top dimple downwardly convex on the top surface.

Wherein forming the recess comprises forming a U-shaped first recess, wherein the first recess includes first and second sidewalls opposing each other, and wherein a portion of the first sidewall is removed to form a first dimple And removing a portion of the second sidewall to form a second dimple.

The first dimple and the second dimple may be formed at the same time.

The forming of the first recess may include forming a convex convex upward between the first and second dimples.

The upper surface dimple may overlap with the convex portion.

Further comprising forming a gate spacer on a side surface of the gate electrode, wherein the gate spacer and the source / drain are in contact with each other.

The side wall of the first recess may be continuous with an outer wall of the gate spacer.

The source / drain may be in contact with the lower surface of the gate spacer.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention.
2 is a cross-sectional view taken along line A-A 'in Fig.
3 is an enlarged cross-sectional view for explaining the portion J1 in FIG. 2 in detail.
4 is a cross-sectional view taken along line C-C 'of Fig.
5 is a sectional view taken along the line E-E 'in Fig.
6 is a cross-sectional view taken along the line B-B 'in Fig.
7 is an enlarged cross-sectional view for explaining J2 portion of 4 in detail.
8 is a cross-sectional view taken along line D-D 'in Fig.
9 is a cross-sectional view taken along line F-F 'in Fig.
10 is a cross-sectional view taken along line A-A 'and B-B' in Fig. 1;
11 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
12 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
13 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
14 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
15 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
FIGS. 16 to 22 are intermediate-level diagrams for explaining a semiconductor device manufacturing method according to some embodiments of the present invention. FIG.
23 is a block diagram of a SoC system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.
24 is a block diagram of an electronic system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle.

Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above" indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, with reference to FIGS. 1 to 5, a layout design system according to some embodiments of the present invention, a semiconductor device using the layout design system, and a manufacturing method thereof will be described.

FIG. 1 is a layout view for explaining a semiconductor device according to some embodiments of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A 'in FIG. FIG. 3 is an enlarged cross-sectional view for explaining the portion J1 in FIG. 2 in detail, and FIG. 4 is a cross-sectional view taken along line C-C ' 5 is a sectional view taken along the line E-E 'in Fig.

1 to 5, a semiconductor device according to some embodiments of the present invention includes a substrate 10, a first fin pattern F1, a second fin pattern F2, first through third shallow trenches ST1 The first and second trenches T1 and T2, the first interlayer insulating film 20, the second interlayer insulating film 30, the first gate electrode 200, the second gate electrode 300, (130, 140), a gate spacer (160), a first source / drain (E1), and the like.

The substrate 10 may be, for example, bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide . Alternatively, the substrate 10 may have an epilayer formed on the base substrate.

The substrate 10 may include a first active region ACT1. The second trench T2 can be in contact with the first active region ACT1. That is, the first active area ACT1 may be located between the first trench T1 and the second trench T2.

Referring to FIG. 1, the first fin-shaped pattern F1 may be elongated in the first direction X. In FIG. 1, the first fin-shaped pattern F1 is shown in a rectangular shape, but the present invention is not limited thereto. If the first fin-shaped pattern F1 is a rectangular shape, the first fin-shaped pattern F1 may include a long side extending in the first direction X and a short side extending in the second direction Y. [ At this time, the second direction Y may be a direction that is not parallel to the first direction X but intersects with the first direction X.

The first fin type pattern F1 may be plural and the first fin type patterns F1 may be arranged to be spaced apart from each other in the second direction Y. [

The plurality of first fin-shaped patterns F1 may be defined by the first to third shallow trenches ST1 to ST3. That is, in the first region I, the first fin type pattern F1 is defined by the first trench T1, the second trench T2, and the first through third shallow trenches ST1 through ST3.

The depths of the first to third shallow trenches ST1 to ST3 may be shallower than the depths of the first and second trenches T1 and T2. However, the widths of the first to third shallow trenches ST1 to ST3 may be narrower than the widths of the first and second trenches T1 and T2. The volume of the first interlayer insulating film 20 formed in the first and second trenches T 1 and T 2 is equal to the volume of the first interlayer insulating film 20 formed in the first to third shallow trenches ST 1 to ST 3 May be greater than the volume.

The first fin type pattern F1 may be formed by etching a part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. [ The first fin-shaped pattern F1 may comprise, for example, silicon or germanium, which is an elemental semiconductor material. Further, the first fin type pattern F1 may include a compound semiconductor, and may include, for example, an IV-IV group compound semiconductor or a III-V group compound semiconductor.

For example, in the case of the IV-IV group compound semiconductors, the first fin type pattern F1 may be a binary pattern including at least two of carbon (C), silicon (Si), germanium (Ge) A binary compound, a ternary compound, or a compound doped with a Group IV element thereon.

The first fin-shaped pattern F1 is a group III element, and at least one of aluminum (Al), gallium (Ga), and indium (In) and phosphorus (P), which is a group V element, arsenic Based compound, ternary compound, or siliceous compound in which one of As (As) and antimony (Sb) is bonded and formed.

In some embodiments of the present invention, the first fin pattern F1 may be a nanowire structure in which silicon and silicon germanium are crossed and stacked. However, the first pinned pattern F1 of the semiconductor device according to the embodiments of the present invention will be described as including silicon.

The first interlayer insulating film 20 may fill a portion of the first to third shallow trenches ST1 to ST3 and the first and second trenches T1 and T2. The first interlayer insulating film 20 may surround a part of the side surface of the first fin-shaped pattern F1.

The first interlayer insulating film 20 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material having a lower dielectric constant than silicon oxide. Low dielectric constant materials include, for example, FOX (Flowable Oxide), TONZ Silicon (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), Borophosphosilicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate, Fluoride Silicate Glass, CDO, Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG, Parylene, Bis-benzocyclobutenes, material, or a combination thereof.

The first interlayer insulating film 20 may have a specific stress characteristic. That is, after the first interlayer insulating film 20 is deposited, its volume may be shrunk by heat treatment to have tensile stress characteristics. The slope of the first fin type pattern F1 can be determined according to the volume of the first interlayer insulating film 20 due to the tensile stress characteristic of the first interlayer insulating film 20. [ That is, when the volumes of the first interlayer insulating films 20 located on both sides are different from each other, the larger the difference in the volume, the larger the slope of the fin pattern. This is because the shrinking rate of the large-volume first interlayer insulating film 20 is smaller than the shrinkage rate of the first interlayer insulating film 20 having a small volume.

Specifically, the first fin-shaped pattern F1 directly contacting the first trench T1 and the second trench T2 among the first fin-shaped patterns F1 extends in the direction of the first trench T1 and the second trench T2 . ≪ / RTI >

That is, the first trench T1 of the first fin-shaped pattern F1 and the uprising of the second trench T2 in the direction of the second trench T2, which are in direct contact with the first trench T1 and the second trench T2, The angles are the first angle? 1 and the second angle? 2, respectively.

The first and second angles? 1 and? 2 may be acute angles. That is, the first fin-shaped pattern F1 can be tilted by an acute angle in the direction of the larger trench among the trenches that are in contact with each other.

The first gate electrode 200 and the second gate electrode 300 may extend in parallel with each other. The first gate electrode 200 and the second gate electrode 300 may extend in the second direction Y. The first gate electrode 200 and the second gate electrode 300 may be spaced apart from each other in the first direction X. [ The first gate electrode 200 may be separated from the second gate electrode 300 by a first distance D1.

The first gate electrode 200 may extend in the second direction Y. [ The first gate electrode 200 may intersect each of the first fin-shaped patterns F1. That is, the first gate electrode 200 may include a plurality of first pin-shaped patterns F1 spaced from each other and overlapping each other. The first fin-shaped pattern F1 may include a portion overlapping the first gate electrode 200 and a portion overlapping the first gate electrode 200, respectively.

The second gate electrode 300 may extend in the second direction. The second gate electrode 300 may intersect each of the first fin-shaped patterns F1. That is, the second gate electrode 300 may include a portion overlapping with the plurality of first fin-shaped patterns F1 spaced from each other. The first fin pattern F1 may include a portion overlapping the second gate electrode 300 and a portion not overlapping the second gate electrode 300, respectively.

Referring to FIGS. 2 and 4, the first gate electrode 200 may include a first work function metal 210 and a first fill metal 220. The first work function metal 210 functions to adjust the work function and the first fill metal 220 functions to fill a space formed by the first work function metal 210. The first work function metal 210 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

In some embodiments of the present invention, the first region I may be a PMOS region, so that the first work function metal 210 and the third work function metal 310 may be an N-type work function metal and a P- Lt; / RTI > For example, the first work function metal 210 and the third work function metal 310 may be at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, But is not limited thereto. The first fill metal 220 and the third fill metal 320 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, , But is not limited thereto.

The first gate electrode 200 and the second gate electrode 300 may be formed through, for example, a replacement process or a gate last process, but are not limited thereto .

The gate insulating films 130 and 140 are formed on the first fin pattern F1 and the first and second gate electrodes 200 and 300 and between the first interlayer insulating film 20 and the first and second gate electrodes 200 and 300, As shown in FIG.

The gate insulating layers 130 and 140 may include an interfacial layer 130 and a high-permittivity layer 140.

The interface film 130 may be formed by oxidizing a part of the first fin-shaped pattern F1. The interface film 130 may be formed along the profile of the first fin-shaped pattern F1 protruding above the upper surface of the first interlayer insulating film 20. [ In the case of the silicon fin type pattern in which the first fin type pattern F1 includes silicon, the interface film 130 may include a silicon oxide film.

4, the interface film 130 is not formed along the upper surface of the first interlayer insulating film 20, but the present invention is not limited thereto. Depending on the method of forming the interface film 130, the interface film 130 may be formed along the upper surface of the first interlayer insulating film 20. [

Alternatively, even if the first interlayer insulating film 20 contains silicon oxide, if the physical properties of the silicon oxide included in the first interlayer insulating film 20 and the physical properties of the silicon oxide film included in the interface film 130 are different, The film 130 may be formed along the upper surface of the first interlayer insulating film 20.

The high-permittivity film 140 may be formed between the interface film 130 and the first and second gate electrodes 200 and 300. Can be formed along the profile of the first fin-shaped pattern (F1) protruding above the upper surface of the first interlayer insulating film (20). In addition, the high-permittivity film 140 may be formed between the first and second gate electrodes 200 and 300 and the first interlayer insulating film 20.

The high-permittivity film 140 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. The high-permittivity film 140 may be formed of, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, Zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, And may include at least one of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate But is not limited thereto.

The gate spacers 160 may be disposed on the sidewalls of the first and second gate electrodes 200 and 300 extending in the second direction Y. [ Gate spacers 160 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon nitride pellets (SiOCN) and at least one of a combination of the two.

Although the gate spacer 160 is illustratively shown as a single film in the drawing, it may be a multiple spacer in which a plurality of films are stacked. The shape of gate spacer 160 and the shape of each of the multiple spacers forming gate spacer 160 may be I or L or a combination thereof depending on the manufacturing process or application.

2, 3, and 5, the first source / drain E1 is formed on both sides of the first gate electrode 200 and the second gate electrode 300 in the first direction X, Can be formed on the pattern F1, respectively. The first source / drain E1 may be the source / drain region of each transistor on the first fin pattern F1.

Fig. 2 is a sectional view in the first direction X, and Fig. 5 is a sectional view in the second direction Y. Fig.

2, in the first region I, the first source / drain E1 may be formed to fill the first recess Flr formed on the upper surface of the first fin pattern F1. At this time, since the first gate electrode 200 and the second gate electrode 300 are formed on the upper surface of the first fin-shaped pattern F1 where the first recess Flr is not formed, (E1) may be formed between the first gate electrode 200 and the second gate electrode 300.

The first source / drain E1 may have the same top surface as the first fin pattern F1. That is, the height of the top surface of the first source / drain E1 and the top surface of the first fin pattern F1 may be the same. The top surface of the first source / drain E1 may be flat. A portion of the top surface of the first source / drain E1 may overlap a portion of the lower surface of the gate spacer 160.

The first source / drain E1 may comprise an epilayer formed by an epitaxial process. Also, the first source / drain E1 may be an elevated source / drain. Since the first active region ACT1 may be a PMOS region, the first source / drain E1 may be, for example, a SiGe epitaxial layer. The first source / drain E1 may fill the first recess F1r of the first fin-shaped pattern F1. Accordingly, the first source / drain E1 may have a W-shaped bottom portion along the bottom surface of the first recess Flr. In some embodiments of the present invention, the first source / drain E1 may have a W-shaped or U-shaped continuous bottom portion of the "UU" type, depending on the formation of the first recess Fl.

Likewise, the first source / drain E1 may become narrower in the depth direction. The first source / drain E1 is formed on both sides of the first gate electrode 200 and the second gate electrode 300, and a region between the first source / drain E1 on both sides of the gate electrode May be used as the first channel region. The length D2 of the first channel region, that is, the distance D2 between the first source / drain E1 may be equal to each other in the first active region ACT1. However, the distance between the first source / drain E1 can be wider as it goes toward the depth direction. That is, the distance D2 between the first source / drain E1 can be a wider spacing D2 'at the deeper level.

Referring to FIG. 3, the first source / drain E1 may overlap gate spacer 160. Specifically, the first source / drain E1 may include an overlap region OR overlapping the gate spacer 160 and a nonoverlap region NOR non-overlapping with the gate spacer 160.

The overlap region OR includes a region overlapping the gate spacer 160 formed on the side surface of the first gate electrode 200 and a region overlapping the gate spacer 160 formed on the side surface of the second gate electrode 300 can do. That is, the overlap region OR can be divided into two regions. However, the present invention is not limited thereto. The overlap region OR may exist only in at least one of the two regions.

The non-overlap region NOR may be located between the two overlap regions OR. The non-overlap region NOR can be formed deeper than the overlap region OR.

The bottom surface of the first recess F1r may include a first dimple DP1 and a second dimple DP2. The first dimple DP1 and the second dimple DP2 may be convex downward. A first convex portion CV1 may be provided between the first dimple DP1 and the second dimple DP2. That is, the first and second dimples DP1 and DP2 may be formed on both sides of the first convex portion CV1. The height of the lowermost portions of the first dimple DP1 and the second dimple DP2 may be equal to each other.

The first source / drain E1 may fill the first recess F1r. The first source / drain E1 may include a first region E1-1 and a second region E1-2. The first area E1-1 may be located between the two second areas E1-2. That is, the second region E1-2 may be located on both sides of the first region E1-1.

The first region E1-1 may be a region overlapping the first convex portion CV1 of the first recess Flr. The second area E1-2 may be an area overlapping the first dimple DP1 and the second dimple DP2 of the first recess F1r, respectively. That is, the lower surface of the second area E1-2 may be U-shaped. The thickness EH1 of the first region E1-1 may be thinner than the thickness EH2 of the second region E1-2. Particularly, since the top surface of the first source / drain E1 is flat, the difference between the thickness EH1 of the first area E1-1 and the thickness EH2 of the second area E1-2 is equal to the thickness of the first dimple DP1), the second dimple DP2 and the first convex portion CV1.

The slope of the lower surface of the first source / drain E1 may be continuous. That is, the lower surface of the first source / drain E1 is formed only in a curved surface, and no corner may be formed. That is, the slopes of the surfaces of the first dimple DP1, the second dimple DP2 and the first convex portion CV1 are all continuous, and the slope of each connecting portion may be continuous. However, the present invention is not limited thereto.

Referring to FIG. 5, the outer peripheral surface of the first source / drain E1 may have various shapes. For example, the outer peripheral surface of the first source / drain E1 may be at least one of a diamond shape, a circular shape, and a rectangular shape. In Fig. 5, a diamond shape (or a pentagonal shape or a hexagonal shape) is exemplarily shown.

In the first active area ACT1, the semiconductor device according to the embodiment of the present invention is a PMOS transistor, so that the first source / drain E1 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. For example, the compressive stress material can increase the mobility of carriers in the channel region by applying compressive stress to the first pinned pattern F1.

The first source / drain E1 may each have a convex polygonal shape. At this time, the plurality of first source / drain E1 may have the same shape. In this case, "identical" does not mean only completely identical shapes but includes concepts in which the internal angles of the convex polygons are the same.

Also, the first source / drain E1 may be symmetrical with respect to each other. In addition, the first source / drain E1 includes a lower region and an upper region formed on the lower region, the width of the lower region being increased as the height is higher, and the width of the upper region Can be narrowed.

The upper region may include a first outer surface and a second outer surface that are symmetrical to each other, and a normal direction of the first and second outer surfaces may be the same at the first source / drain (E1).

The plurality of first source / drain (E1) may be identical to each other. In some embodiments of the present invention, the interior angle may refer to only three interior angles that do not touch the first pinned pattern F1. That is, the three internal angles of the first source / drain E1 can only have a constant value depending on the crystal direction.

Since the first active region ACT1 is a PMOS region, the first source / drain E1 may include SiGe, and the epitaxial growth thereof may be carried out smoothly in the crystal direction. Thus, the first source / drain E1 may have the same shape.

Hereinafter, a semiconductor device according to some embodiments of the present invention will be described with reference to Figs. 1, 6 to 9. The portions overlapping with the above description will be simplified or omitted.

FIG. 6 is a cross-sectional view taken along line B-B 'of FIG. 1, and FIG. 7 is an enlarged cross-sectional view for explaining J2 portion of FIG. 4 in detail. 8 is a sectional view taken along the line D-D 'in FIG. 1, and FIG. 9 is a sectional view taken along the line F-F' in FIG.

Referring to Figures 1 and 6 to 9, the substrate 10 may include a second active area ACT2. The third trench T3 may be in contact with the second active region ACT2. That is, the second active region ACT2 may be located between the first trench T1 and the third trench T3.

Referring to FIG. 1, the second fin-shaped pattern F2 may be elongated in the first direction X. As shown in FIG. Although the second fin-shaped pattern F2 is shown in a rectangular shape in Fig. 1, it is not limited thereto. If the second fin type pattern F1 is rectangular, the second fin type pattern F2 may include a long side extending in the first direction X and a short side extending in the second direction Y. [ At this time, the second direction Y may be a direction that is not parallel to the first direction X but intersects with the first direction X.

The second fin-shaped patterns F2 may be plural and the second fin-shaped patterns F2 may be disposed apart from each other in the second direction Y. [

The plurality of second fin-shaped patterns F2 may be defined by the fourth to sixth shallow trenches ST4 to ST6. That is, in the second region II, the second fin type pattern F2 is defined by the first trench T1, the third trench T3 and the fourth to sixth shallow trenches ST4 to ST6.

The depths of the fourth to sixth shallow trenches ST4 to ST6 may be shallower than the depths of the first and third trenches T1 and T3. However, the widths of the fourth to sixth shallow trenches ST4 to ST6 may be narrower than the widths of the first and third trenches T1 and T3. The volume of the first interlayer insulating film 20 formed in the first and third trenches Tl and T3 is smaller than the volume of the first interlayer insulating film 20 formed in the fourth to sixth shallow trenches ST4 to ST6 May be greater than the volume.

The second fin type pattern F2 may be formed by etching a part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. [ The second fin-shaped pattern F2 may comprise, for example, silicon or germanium, which is an elemental semiconductor material. Further, the second fin type pattern F2 may include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor.

In some embodiments of the present invention, the second fin-shaped pattern F2 may be a nanowire structure in which silicon and silicon germanium are stacked and crossed. However, the second pinned pattern F2 of the semiconductor device according to the embodiments of the present invention is described as including silicon.

The first interlayer insulating film 20 may fill part of the fourth through sixth shallow trenches ST4 through ST6 and the first and third trenches T1 and T3. The first interlayer insulating film 20 may surround a part of the side surface of the second fin-shaped pattern F2.

The second fin type pattern F2 directly contacting the second trench T2 and the third trench T3 of the second fin pattern F2 is tilted in the direction of the second trench T2 and the third trench T3 .

That is, the second trench T2 of the second fin-shaped pattern F2 and the upstanding trench T2 of the third trench T3, which are in direct contact with the second trench T2 and the third trench T3, The angles are the third angle [theta] 3 and the fourth angle [theta] 4, respectively.

The third and fourth angles? 3 and? 4 may be acute angles. That is, the second fin-shaped pattern F2 can be tilted by an acute angle in the direction of the larger trench among the trenches that are in contact with each other.

The third gate electrode 201 and the fourth gate electrode 301 may extend in parallel with each other. The third gate electrode 201 and the fourth gate electrode 301 may extend in the second direction Y. [ The third gate electrode 201 and the fourth gate electrode 301 may be spaced apart from each other in the second direction Y. [ The third gate electrode 201 may be spaced apart from the fourth gate electrode 301 by a first distance D1. That is, the distance in which the two gate electrodes are spaced apart from each other in the first region I and the second region II may be the same.

The third gate electrode 201 may extend in the second direction Y. [ And the third gate electrode 201 may cross the second fin-shaped pattern F2, respectively. That is, the third gate electrode 201 may include a portion overlapping each of the plurality of second fin-shaped patterns F2 spaced from each other. The second fin pattern F2 may include a portion overlapping the third gate electrode 201 and a portion not overlapping the third gate electrode 201, respectively.

The fourth gate electrode 301 may extend in the second direction Y. [ And the fourth gate electrode 301 may intersect each of the second fin-shaped patterns F2. That is, the fourth gate electrode 301 may include a portion overlapping each of the plurality of second fin-shaped patterns F2 spaced from each other. The second fin-shaped pattern F2 may include a portion overlapping the fourth gate electrode 301 and a portion not overlapping the fourth gate electrode 301, respectively.

Referring to FIGS. 6 and 8, the third gate electrode 201 may include a third work function metal 211 and a third fill metal 221. The third work function metal 211 functions to adjust the work function and the third fill metal 221 functions to fill the space formed by the third work function metal 211. The third work function metal 211 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

The fourth gate electrode 301 may include a fourth work function metal 311 and a fourth fill metal 321. The fourth work function metal 311 controls the work function and the fourth fill metal 321 functions to fill a space formed by the fourth work function metal 311. The fourth work function metal 311 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

In some embodiments of the present invention, the second region II may be an NMOS region, so that the second work function metal 211 and the fourth work function metal 311 may be N-type work function metals. The second work function metal 211 and the fourth work function metal 311 may comprise at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, However, the present invention is not limited thereto. The second fill metal 221 and the fourth fill metal 321 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, , But is not limited thereto.

The third gate electrode 201 and the fourth gate electrode 301 may be formed through, for example, a replacement process or a gate last process, but are not limited thereto .

The gate insulating films 130 and 140 are formed between the second fin pattern F1 and the third and fourth gate electrodes 201 and 301 and between the first interlayer insulating film 20 and the third and fourth gate electrodes 201 and 301, As shown in FIG.

The gate insulating layers 130 and 140 may include an interfacial layer 130 and a high-permittivity layer 140.

The interface film 130 may be formed by oxidizing a part of the second fin-shaped pattern F2. The interface film 130 may be formed along the profile of the second fin-shaped pattern F2 protruding above the upper surface of the first interlayer insulating film 20. [ In the case of the silicon fin type pattern in which the second fin type pattern F2 includes silicon, the interface film 130 may include a silicon oxide film.

8, the interface film 130 is not formed along the upper surface of the first interlayer insulating film 20. However, the present invention is not limited thereto. Depending on the method of forming the interface film 130, the interface film 130 may be formed along the upper surface of the first interlayer insulating film 20. [

Alternatively, even if the first interlayer insulating film 20 contains silicon oxide, if the physical properties of the silicon oxide included in the first interlayer insulating film 20 and the physical properties of the silicon oxide film included in the interface film 130 are different, The film 130 may be formed along the upper surface of the first interlayer insulating film 20.

The high-permittivity film 140 may be formed between the interface film 130 and the third and fourth gate electrodes 201 and 301. Can be formed along the profile of the second fin-shaped pattern F2 protruding above the upper surface of the first interlayer insulating film 20. [ In addition, the high-permittivity film 140 may be formed between the third and fourth gate electrodes 201 and 301 and the first interlayer insulating film 20.

The high-permittivity film 140 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. The high-permittivity film 140 may be formed of, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, Zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, And may include at least one of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate But is not limited thereto.

The gate spacers 160 may be disposed on the sidewalls of the third and fourth gate electrodes 201 and 301 extending in the second direction Y. [ Gate spacers 160 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon nitride pellets (SiOCN) and at least one of a combination of the two.

Although the gate spacer 160 is illustratively shown as a single film in the drawing, it may be a multiple spacer in which a plurality of films are stacked. The shape of gate spacer 160 and the shape of each of the multiple spacers forming gate spacer 160 may be I or L or a combination thereof depending on the manufacturing process or application.

6, 7, and 9, the second source / drain E2 is formed on both sides of the third gate electrode 201 and the fourth gate electrode 301 in the first direction X, May be formed on the pattern F2, respectively. The second source / drain E2 may be the source / drain region of each transistor on the second fin-shaped pattern F2.

Fig. 6 is a sectional view in the first direction (X), and Fig. 9 is a sectional view in the second direction (Y).

6, in the second region II, the second source / drain E2 may be formed to fill the second recess F2r formed on the upper surface of the second fin-shaped pattern F2. Since the third gate electrode 201 and the fourth gate electrode 301 are formed on the upper surface of the second fin pattern F2 where the second recess F2r is not formed, The second gate electrode E2 may be formed between the third gate electrode 201 and the fourth gate electrode 301.

And the second source / drain E2 may have a top surface higher than the second fin-shaped pattern F2. That is, the height of the upper surface of the second source / drain E2 may be higher than the height of the upper surface of the second fin-shaped pattern F2.

The second source / drain E2 may be formed on the second fin-shaped pattern F2 on both sides of the third gate electrode 201 and the fourth gate electrode 301 in the first direction X, respectively. The second source / drain E2 may be the source / drain region of each transistor on the second fin-shaped pattern F2.

The second source / drain E2 may comprise an epi layer formed by an epi process. Also, the second source / drain E2 may be an elevated source / drain. Since the second active region ACT2 may be an NMOS region, the second source / drain E2 may be an Si epitaxial layer. At this time, the second source / drain E2 may include Si: P or SiPC doped with SiC, P at a high concentration.

The second source / drain E2 may fill the second recess F2r of the second fin-shaped pattern F2. Accordingly, the second source / drain E2 may have a W-shaped bottom portion along the bottom surface of the second recess F2r. In some embodiments of the present invention, the first source / drain E1 may have a W-shaped or U-shaped continuous bottom portion of the "UU" type, depending on the formation of the first recess Fl.

Likewise, the second source / drain E2 may become narrower in the depth direction. The second source / drain E2 is formed on both sides of the third gate electrode 201 and the fourth gate electrode 301, and a region between the second source / drain E2 on both sides of the gate electrode Can be used as the second channel region. The length D3 of the second channel region, that is, the distance D3 between the second source / drain E2, may be the same in the second region II. However, since the lower surface of the second source / drain E2 is formed in a U-shape, the distance between the second source / drain E2 can be widened toward the depth direction. That is, the spacing D3 between the second source / drain E2 can be a wider spacing D3 'at a deeper level.

Referring to FIG. 7, the second source / drain E2 may not overlap the gate spacer 160.

The bottom surface of the second recess F2r may include a third dimple DP3 and a fourth dimple DP4. The third dimple DP3 and the fourth dimple DP4 may be convex downward. A second convex portion CV2 may be provided between the third dimple DP3 and the fourth dimple DP4. That is, the third and fourth dimples DP3 and DP4 may be formed on both sides of the second convex portion CV2. The height of the lowermost portions of the third dimple DP3 and the fourth dimple DP4 may be equal to each other.

And the second source / drain E2 may fill the second recess F2r. The second source / drain E2 may include a first region E2-1 and a first region E2-2. The first area E2-1 may be located between the two first areas E2-2. That is, the first region E2-2 may be located on both sides of the first region E2-1.

The upper surface of the first area E2-1 can be convex downward. The second region can be convex upward. The upper surface of the first area E2-1 and the upper surface of the first area E2-2 may be continuous. That is, the upper surface of the second source / drain may include a downwardly convex upper surface dimple, and the upper surface dimple may be formed in the first region E2-1. The first area E2-2 may be shaped to be inclined toward the first area E2-1 by the upper surface dimples of the first area E2-1.

The uppermost portion of the first region E2-2 may be formed higher than the lower surfaces of the third gate electrode 201 and the fourth gate electrode 301. [ The slope of the lower surface of the second source / drain E2 may be continuous. That is, the lower surface of the second source / drain E2 is formed only in a curved surface, and no corner may be formed. In other words, the slopes of the surfaces of the third dimple DP3, the fourth dimple DP4 and the second convex portion CV2 are all continuous, and the slope of each connecting portion may be continuous. However, the present invention is not limited thereto.

The first region E2-1 may be an area overlapping the second convex portion CV2 of the second recess F2r. The first area E2-2 may be an area overlapping the third dimple DP3 and the fourth dimple DP4 of the second recess F2r, respectively. That is, the lower surface of the first area E2-2 may be U-shaped. The thickness EH3 of the first region E2-1 may be thinner than the thickness EH4 of the first region E2-2.

Referring to FIG. 9, the outer circumferential surface of the second source / drain E2 may have various shapes. For example, the outer circumferential surface of the second source / drain E2 may be at least one of a diamond shape, a circular shape, and a rectangular shape. In Fig. 9, a diamond shape (or a pentagonal shape or a hexagonal shape) is exemplarily shown.

In the second region II, when the semiconductor device according to the embodiment of the present invention is an NMOS transistor, the second source / drain E2 may include a tensile stress material. For example, when the second fin type pattern F2 is silicon, the second source / drain E2 may comprise a material having a smaller lattice constant than silicon (e.g., SiC, SiPC, SiP). For example, the tensile stress material may apply tensile stress to the second fin-shaped pattern F2 to improve the mobility of carriers in the channel region.

Referring to FIG. 9, the second source / drain E2 of the second region II may have a convex polygonal shape. The convex polygon may be pentagonal. At this time, the "convex polygon" does not necessarily mean only a figure having a flat surface other than the cabinet but has a plurality of internal angles which are greatly characterized, and includes a shape connecting the plural internal angles to a curved surface. That is, as shown in Fig. 9, the "convex polygon " in the present specification is characterized by a large angle of the cabinet, other cabinets, and the plane connecting each cabinet may not be plane.

The second source / drain E2 may have a different shape. Specifically, the internal angles of the second source / drain E2 may be different from each other.

Since the second region II is an NMOS region, the second source / drain E2 may include Si, SiPC, or SiP, and epitaxial growth thereof may be performed in a crystal direction unlike the first region I . Thus, the plurality of second source / drain E2 may have different shapes.

The second source / drain E2 includes a lower region and an upper region formed on the lower region, and the width of the lower region is increased as the height is higher, and the width of the upper region is narrower as the height is higher. Can be.

In the second source / drain (E2), the upper region includes a third outer surface and a fourth outer surface that are symmetrical to each other, and the normal direction of the third and fourth outer surfaces is parallel to each other in the third and fourth epitaxial patterns can be different.

The semiconductor device according to some embodiments of the present invention may be formed with an air gap G as portions of the second source / drain E2 contact with each other in the second region II.

The air gap G may be formed between the two second source / drain regions E2 that are in contact with each other. The air gap G may be formed on the first interlayer insulating film 20. The air gap G may be covered by two second source / drain E2 that are in contact with each other.

Hereinafter, with reference to Figs. 1 to 10, a semiconductor device according to some embodiments of the present invention will be described. The portions overlapping with the above description will be simplified or omitted.

10 is a cross-sectional view taken along line A-A 'and B-B' in Fig. 1;

1 to 10, the substrate 10 may include a first region I and a second region II. The first region I and the second region II may be adjacent to each other or may be spaced apart from each other. Therefore, the first fin type pattern F1 of the first region I and the second fin type pattern F2 of the second region II may extend in different directions. However, for convenience of explanation, it is assumed that the first fin type pattern F1 of the first region I and the second fin type pattern F2 of the second region II extend in the same direction.

Transistors of different conductivity types may be formed in the first region I and the second region II. For example, the first region I may be a region where a PMOS is formed, and the second region II may be a region where an NMOS is formed, but the present invention is not limited thereto.

The first region I and the second region II may be defined by a first trench T1, a second trench T2 and a third trench T3. The first trenches T1 may have first and second sides facing each other. The first trench T1 may be in contact with the first region I on the first side and the second region II on the second side.

The first gate electrode 200 and the third gate electrode 201 may or may not be connected to each other. Similarly, the second gate electrode 300 and the fourth gate electrode 301 may or may not be connected to each other.

The first source / drain E1 and the second source / drain E2 may each be narrowed in width. In addition, the width of the first source / drain E1 may be smaller than the width of the second source / drain E2.

The width of the first recess F1r may be greater than the width of the second recess F2r. In this case, the "width" may mean the width of the first direction X. That is, the width of the first recessed portion F1r in the first direction X may be greater than the width of the second recessed portion F2r in the first direction X. Therefore, the first recess Flr may be deeper than the second recess F2r, and the first recess Flr may be wider in the first direction X than the second recess F2r. Thus, the first source / drain E1 may have a larger volume than the second source / drain E2. In addition, the lowermost portion of the lower surface of the first source / drain E1 may be lower than the lowermost portion of the lower surface of the second source / drain E2. The width of the first source / drain E1 in the first direction X may be greater than the width of the second source / drain E2 in the first direction X. [

The distance between the source / drain in the first region I and the second region II, that is, the distance D2 between the first source / drain E1 and the distance between the second source / drain E2 D3 may be different from each other. That is, the distance D2 between the first source / drain E1 may be larger than the distance D3 between the second source / drain E2. This is because the distance D1 between the first gate electrode 200 and the second gate electrode 300 in the first direction X and the distance D1 between the third gate electrode 201 and the fourth gate electrode 301 The widths of the first recesses F1r and the second recesses F2r in the first direction X may be different from each other. That is, since the first direction X of the first recess Fl is larger than the width of the second recess F2r in the first direction X, the first region I and the second region II The spacing between the source and the drain may be different from each other.

The height of the interface at which the first source / drain E1 and the first fin-shaped pattern F1 meet in the first region I is greater than the height of the second source / drain E2 in the second region II and the second fin- May be lower than the height of the interface at which the second interface F2 meets. That is, the lower surface of the first source / drain E1 may be lower than the lower surface of the second source / drain E2.

This is because the recessed depth of the first fin-shaped pattern F1 in the first region I is deeper. The first source / drain E1 is regularly formed in the first region I, and therefore, the first source / drain E1 is formed in the first region I according to the degree of the first recess F1r of the first fin type pattern F1. (E1) can be determined. That is, the distance from the substrate 10 in the pin-shaped pattern can be narrowed. Accordingly, the deeper the first recess Flr, the wider the width of the upper surface of the recessed pin-shaped pattern. That is, since the entire volume of the first source / drain E1 is formed along the crystal direction, it can be determined according to the width of the upper surface of the exposed fin-shaped pattern.

On the other hand, in the second region II, the shape of the second source / drain E2 is irregular, so that the width of the upper surface of the exposed pin-like pattern does not affect the volume of the second source / drain E2 . However, the volume of the second source / drain E2 can be determined by how long the second source / drain E2 has grown for a given time. Therefore, unlike the first region (I), it is not necessary to deeply form the recess of the pin-shaped pattern in the second region (II). Therefore, the height of the interface between the fin-shaped pattern and the epitaxial pattern of the first region I may be lower than the height of the interface between the fin-shaped pattern of the second region II and the epitaxial pattern.

The upper surface of the second fin-shaped pattern F2 of the second region II may be higher than the upper surface of the first fin-shaped pattern F1 of the first region I. The width of the upper surface of the second fin type pattern F2 of the second region II may be narrower than the width of the upper surface of the first fin type pattern F1 of the first region I.

Some of the second source / drain E2 of the second region II may be in contact with each other. That is, some of the second source / drain E2 may be merged with each other.

The first source / drain E1 of the first region I may not be in contact with each other and may be spaced apart from each other. On the other hand, at least one of the second source / drain E2 may be in contact with each other. This is because the width of the second source / drain E2 of the second region II is larger than that of the first source / drain E1 of the first region I.

3 and 7, the height h3 of the first convex portion CV1 may be lower than the height h4 of the second convex portion CV2. That is, the heights of the convex portions in the NMOS region and the PMOS region may be different from each other. That is, the height of the first convex portion CV1 in the PMOS region may be lower than the height of the second convex portion CV2 in the NMOS region.

Hereinafter, with reference to FIGS. 11 and 12, a semiconductor device according to some embodiments of the present invention will be described. The portions overlapping with the above description will be simplified or omitted.

FIG. 11 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and FIG. 12 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 11, a semiconductor device according to some embodiments of the present invention includes a third active region ACT2 ', which is similar to the second active region ACT2.

The third source / drain E2 'in the third active region ACT2' may be formed to fill the third recess F2r 'formed on the upper surface of the third fin pattern F2'. At this time, since the fifth gate electrode 201 'and the sixth gate electrode 301' are formed in the portion where the third recess F2r 'is not formed on the upper surface of the third fin pattern F2' 3 source / drain E2 'may be formed between the fifth gate electrode 201' and the sixth gate electrode 301 '.

The third source / drain E2 'may have a higher top surface than the third fin pattern F2'. That is, the height of the top surface of the third source / drain E2 'may be higher than the height of the top surface of the third fin pattern F2'. The upper surface of the third source / drain E2 'may have a convex portion CV.

The convex portion CV on the upper surface of the third source / drain E2 'may be formed to be convex from the upper surface of the third fin pattern F2'. The third source / drain E2 'is formed on the third pinned pattern F2' on both sides of the fifth gate electrode 201 'and the sixth gate electrode 301' in the first direction X, . The second source / drain E2 may be the source / drain region of each transistor on the second fin-shaped pattern F2.

The third source / drain E2 'may fill the second recess Flr' of the third pinned pattern F2 '. Likewise, the third source / drain E2 'may fill the third recess F2r' of the third fin pattern F2 '. Thus, the third source / drain E2 'may have a U-shaped bottom along the bottom surface of the third recess F2r'. The third recess F2r 'may have a U-shaped bottom surface, and accordingly, the width may become narrower toward the depth direction.

Hereinafter, a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 13 and 14. FIG. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

FIG. 13 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention, and FIG. 14 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

13 and 14, a semiconductor device according to some embodiments of the present invention includes a capping layer 150 and a first silicide layer 150 formed on the first source / drain E1 and the second source / (S1) and a second silicide (S2).

The capping layer 150 may be formed on the high-permittivity layer 140 and the first gate electrode 200. The capping layer 150 may comprise, for example, SiN. The capping layer 150 may contact the inner wall of the gate spacer 160. The top surface of the capping layer 150 may be at the same level as the top surface of the gate spacer 160, but is not limited thereto. The upper surface of the capping layer 150 may be higher than the upper surface of the gate spacer 160.

The first and second silicides S1 and S2 may be formed on the first source / drain E1 and the second source / drain E2. The silicide may be formed by partially deforming the first source / drain E1 and the second source / drain E2. The silicide may comprise a metal. The metal may include at least one of Ni, Co, Pt, Ti, W, Hf, Yb, Tb, Dy, Er, Pd and their alloys.

The contact holes ch1 and ch2 penetrate the second interlayer insulating film 30 and the third interlayer insulating film 40 and expose at least a part of the first and second silicides S1 and S2. The barrier layers L1 and L2 are conformally formed along the side surfaces and the bottom surfaces of the contact holes ch1 and ch2 and the contacts C1 and C2 are formed on the barrier layers L1 and L2 with the contact holes ch1 and ch2 As shown in Fig.

The first source / drain E1 and the second source / drain E2 protrude from the surface of the substrate 10, that is, the surfaces of the first fin type pattern F1 and the second fin type pattern F2, And may include protrusions surrounding both sides of the second silicide (S1, S2).

As shown, the protrusions may be of a shape that becomes narrower as the distance from the surface of the substrate 10 becomes smaller.

In addition, the protrusions may have a shape that covers at least 1/2 of the vertical length of the first and second silicides S1 and S2. In the figure, protrusions are shown in the form of wrapping the entire side surfaces of the first and second silicides S1 and S2, but are not limited thereto.

The first and second silicides S1 and S2 may not be formed on at least a part of the surfaces of the first source / drain E1 and the second source / drain E2. 12, in the region between the first and second silicides S1 and S2 and the first to fourth gate electrodes 200, 201, 300, and 301, / Drain E1 and the surface of the second source / drain E2.

The first and second silicides S1 and S2 may be a reversed cone type, as shown. Therefore, the narrow tip region can be located downward (toward the substrate 10), and the bottom surface can be positioned upward (opposite to the substrate 10). Further, since the first and second silicides S1 and S2 are narrow in the lower part and widened in the upward direction, the side faces can be inclined at a predetermined angle?. The predetermined angle may be, for example, 30 DEG to 70 DEG, but is not limited thereto. More specifically, the predetermined angle may be 40 ° or more and 60 °, but is not limited thereto.

In addition, the tip regions of the first and second silicides S1 and S2 may be positioned higher than the surface of the substrate 10. [ By doing so, the channel length of the transistor can be sufficiently secured, and the operation characteristics of the transistor can be enhanced.

The first silicide S1 may be formed on the first source / drain E1. Accordingly, the upper surface of the first silicide S1 can be flat. However, a recess may be formed by the portion where the first contact C1 and the first barrier layer L1 are formed in the first silicide S1. That is, the upper surface of the first silicide S1 can be flattened by the first source / drain E1, except for the portion where the first contact C1 and the first barrier layer L1 are formed.

The first contact hole ch1 may be formed in a part of the upper portion of the first silicide S1. That is, a recess may be formed in a part of the upper portion of the first silicide S1. The recess may be semicircular as shown. However, the present invention is not limited to this, and may be a square or another shape.

And the second silicide S2 may be formed on the second source / drain E2. Thus, the upper surface of the second silicide S2 can be convex upward. However, a recess may be formed by the portion where the second contact C2 and the second barrier layer L2 are formed in the second silicide S2. That is, the upper surface of the second silicide S2 except the portion where the second contact C2 and the second barrier layer L2 are formed can be convexed upward by the second source / drain E2.

And the second contact hole ch2 may be formed in a part of the upper portion of the second silicide S2. That is, a recess may be formed in a part of the upper portion of the second silicide S2. The recess may be semicircular in shape as shown. However, the present invention is not limited thereto.

Hereinafter, with reference to FIG. 15, a semiconductor according to some embodiments of the present invention will be described. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

15 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 15, the third dimple DP3 and the fourth dimple DP4 may have different shapes. The height of the lowermost portion of the third dimple DP3 may be lower than the height of the lowermost portion of the fourth dimple DP4. Accordingly, the thicknesses of the second regions E2-2 of the second source / drain E2 can be different from each other. Specifically, the thickness EH4 of the second area E2-2 formed on the third dimple DP3 and the thickness EH4 of the second area E2-2 formed on the fourth dimple DP4 May differ from one another.

However, the thicknesses EH4 and EH4 'of the second area E2-2 may be greater than the thickness of the first area E2-1.

Hereinafter, with reference to Figs. 6 and 16 to 22, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described. The portions overlapping with the above-described embodiment are briefly omitted or omitted.

FIGS. 16 to 22 are intermediate-level diagrams for explaining a semiconductor device manufacturing method according to some embodiments of the present invention. FIG. The semiconductor device manufactured by Figs. 16 to 22 is the semiconductor device of Fig.

First, referring to FIG. 16, a second fin-shaped pattern F2 protruding on the substrate 10 is formed.

The substrate 10 may be, for example, bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide . Alternatively, the substrate 10 may have an epilayer formed on the base substrate.

The second fin type pattern F2 may be formed by etching a part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. [ The second fin-shaped pattern F2 may comprise, for example, silicon or germanium, which is an elemental semiconductor material. Further, the second fin type pattern F2 may include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor.

17, the first dummy gate structures 40a, 41a and 42a and the second dummy gate structures 40b, 41b and 42b are formed on the second fin pattern F2.

The first dummy gate structures 40a, 41a and 42a may include a first dummy gate insulating film 41a, a first dummy gate electrode 40a, and a first dummy gate capping film 42a. The second dummy gate structures 40b, 41b and 42b may include a second dummy gate insulating film 41b, a second dummy gate electrode 40b and a second dummy gate capping film 42b. The first dummy gate structures 40a, 41a and 42a may have a structure in which a first dummy gate insulating film 41a, a first dummy gate electrode 40a, and a first dummy gate capping film 42a are sequentially stacked. The second dummy gate structures 40b, 41b and 42b may have a structure in which a second dummy gate insulating film 41b, a second dummy gate electrode 40b and a second dummy gate capping film 42b are sequentially stacked.

18, gate spacers 160 are formed on both sides of the first dummy gate structures 40a, 41a, and 42a and the second dummy gate structures 40b, 41b, and 42b.

The gate spacers 160 may be disposed on the sidewalls of the first dummy gate structures 40a, 41a and 42a and the second dummy gate structures 40b, 41b, and 42b extending in the second direction Y. [ Gate spacers 160 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon nitride pellets (SiOCN) and at least one of a combination of the two.

Although the gate spacer 160 is illustratively shown as a single film in the drawing, it may be a multiple spacer in which a plurality of films are stacked. The shape of gate spacer 160 and the shape of each of the multiple spacers forming gate spacer 160 may be I or L or a combination thereof depending on the manufacturing process or application.

19, using the first dummy gate structures 40a, 41a, and 42a, the second dummy gate structures 40b, 41b, and 42b, and the gate spacers 160 as a mask, a pre- ).

The free recess (F2r-P) may have a U-shaped bottom surface. The free recess F2r-P may not overlap with the gate spacer 160. [ The step of forming the free recesses F2r-P may be performed by isotropic etching. However, the present invention is not limited thereto.

The free recess (F2r-P) can make the approximate shape of the recess by isotropic etching, but the intended size or fine shape may not be completed by the etching. Thus, an additional etch process may be required.

Next, referring to FIGS. 20 and 21, the third dimple DP3 and the fourth dimple DP4 can be formed by etching both sides of the free recess F2r-P.

According to the secondary step of forming the free recesses F2r-P and then forming the third dimple DP3 and the fourth dimple DP4, a recess filled with the source / drain can be formed in a desired size have. That is, the etching of the large frame can be performed through the pre-recesses F2r-P, and the second recesses F2r can be completed through an additional secondary etching process.

Next, referring to FIG. 22, a second source / drain E2 filling the second recess F2r may be formed.

And the second source / drain E2 may have a top surface higher than the second fin-shaped pattern F2. That is, the height of the upper surface of the second source / drain E2 may be higher than the height of the upper surface of the second fin-shaped pattern F2.

The second source / drain E2 may comprise an epi layer formed by an epi process. Also, the second source / drain E2 may be an elevated source / drain. Since the second active region ACT2 may be an NMOS region, the second source / drain E2 may be an Si epitaxial layer. At this time, the second source / drain E2 may include Si: P or SiPC doped with SiC, P at a high concentration.

The second source / drain E2 may fill the second recess F2r of the second fin-shaped pattern F2. Accordingly, the second source / drain E2 may have a W-shaped bottom portion along the bottom surface of the second recess F2r. In some embodiments of the present invention, the first source / drain E1 may have a W-shaped or U-shaped continuous bottom portion of the "UU" type, depending on the formation of the first recess Fl.

Likewise, the second source / drain E2 may become narrower in the depth direction. The second source / drain E2 is formed on both sides of the third gate electrode 201 and the fourth gate electrode 301, and a region between the second source / drain E2 on both sides of the gate electrode Can be used as the second channel region. The length D3 of the second channel region, that is, the distance D3 between the second source / drain E2, may be the same in the second region II. However, since the lower surface of the second source / drain E2 is formed in a U-shape, the distance between the second source / drain E2 can be widened toward the depth direction. That is, the spacing D3 between the second source / drain E2 can be a wider spacing D3 'at a deeper level.

6, the first dummy gate structures 40a, 41a and 42a and the second dummy gate structures 40b, 41b and 42b are removed and the third gate electrode 201 and the fourth gate electrode 301 and the gate insulating films 130 and 140 can be formed.

The third gate electrode 201 may include a third work function metal 211 and a third fill metal 221. The third work function metal 211 functions to adjust the work function and the third fill metal 221 functions to fill the space formed by the third work function metal 211. The third work function metal 211 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

The fourth gate electrode 301 may include a fourth work function metal 311 and a fourth fill metal 321. The fourth work function metal 311 controls the work function and the fourth fill metal 321 functions to fill a space formed by the fourth work function metal 311. The fourth work function metal 311 may be, for example, an N-type work function metal, a P-type work function metal, or a combination thereof.

In some embodiments of the present invention, the second region II may be an NMOS region, so that the second work function metal 211 and the fourth work function metal 311 may be N-type work function metals. The second work function metal 211 and the fourth work function metal 311 may comprise at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, However, the present invention is not limited thereto. The second fill metal 221 and the fourth fill metal 321 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, , But is not limited thereto.

The interface film 130 may be formed by oxidizing a part of the second fin-shaped pattern F2. The interface film 130 may be formed along the profile of the second fin-shaped pattern F2 protruding above the upper surface of the first interlayer insulating film 20. [ In the case of the silicon fin type pattern in which the second fin type pattern F2 includes silicon, the interface film 130 may include a silicon oxide film.

The high-permittivity film 140 may be formed between the interface film 130 and the third and fourth gate electrodes 201 and 301. Can be formed along the profile of the second fin-shaped pattern F2 protruding above the upper surface of the first interlayer insulating film 20. [ In addition, the high-permittivity film 140 may be formed between the third and fourth gate electrodes 201 and 301 and the first interlayer insulating film 20.

The high-permittivity film 140 may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. The high-permittivity film 140 may be formed of, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, Zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, And may include at least one of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate But is not limited thereto.

23 is a block diagram of a SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 23, the SoC system 1000 includes an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC system 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a bus 1030 may have a multi-layer structure. For example, the bus 1030 may be a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI). However, the present invention is not limited thereto.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the elements of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

24 is a block diagram of an electronic system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 24, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver.

Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an SRAM.

The semiconductor device according to the embodiments of the present invention described above may be provided in the storage device 1130 or may be provided as a part of the controller 1110, the input / output device 1120, the I / O, and the like.

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: substrate F1: first pinned pattern
F2: first fin type pattern 200: first gate electrode
201: third gate electrode 300: second gate electrode
301: fourth gate electrode E1: first source / drain
E2: Second source / drain

Claims (20)

A pinned pattern protruding from the substrate and extending in a first direction;
First and second gate electrodes extending in parallel to each other in a second direction crossing the first direction on the pinned pattern;
A recess formed in the fin-shaped pattern between the first and second gate electrodes; And
And a source / drain that fills the recess and includes a first region and a second region formed on both sides of the first region, wherein the thickness of the first region is smaller than the thickness of the second region. The method according to claim 1,
And the upper surface of the second region is higher than the upper surface of the first region. The method according to claim 1,
And the lower surface of the second region is lower than the lower surface of the first region. The method according to claim 1,
Wherein the recess comprises first and second dimples convex downward. 5. The method of claim 4,
And a convex portion convex upward between the first and second dimples. 5. The method of claim 4,
Wherein the first and second dimples are located on the opposite sides with respect to the first region,
And the first and second dimples overlap with the second region. The method according to claim 1,
Wherein the source / drain comprises Si: P. The method according to claim 1,
And the upper surfaces of the first and second regions are flat. The method according to claim 1,
And the uppermost portion of the second region is higher than the lower surfaces of the first and second gate electrodes. 10. The method of claim 9,
And the lowermost portion of the first region is lower than the lower surface of the first and second gate electrodes. 10. The method of claim 9,
And a lowermost portion of the first region is higher than a lower surface of the first and second gate electrodes. The method according to claim 1,
And the lower surface of the second region is U-shaped. 13. The method of claim 12,
And the inclination of the lower surface of the source / drain is continuous. A first fin-shaped pattern protruding from the substrate and extending in a first direction;
First and second gate electrodes extending in parallel to each other in a second direction crossing the first direction on the first fin pattern;
A first recess formed in the fin-shaped pattern between the first and second gate electrodes, the bottom surface of the first recess having first and second dimples convex downward, and a second dimple between the first and second dimples, A first recess including a convex portion positioned in the recess; And
And a first source / drain that fills the recess and includes a top dimple downwardly convex on the top surface. 15. The method of claim 14,
The substrate includes first and second regions, wherein a first fin-shaped pattern is formed in the first region,
A second fin-shaped pattern formed in the second region,
Third and fourth gate electrodes crossing the second fin-shaped pattern on the second fin-shaped pattern and extending in parallel with each other,
A second recess formed in the fin-shaped pattern between the third and fourth gate electrodes, the bottom surface of the second recess not including a convex portion,
And a second source / drain to fill the second recess. 16. The method of claim 15,
Wherein an interval between said first and second gate electrodes is larger than an interval between said third and fourth gate electrodes. 16. The method of claim 15,
And an upper surface of the second source / drain is convex upward. 16. The method of claim 15,
And the upper surface of the second source / drain is flat. 15. The method of claim 14,
Wherein the source / drain includes a first region and a second region formed on both sides of the first region,
And the upper surface dimple is formed in the first region. A substrate comprising first and second regions;
A first fin-shaped pattern formed on the first region;
A second fin-shaped pattern formed on the second region;
First and second gate electrodes crossing the first fin pattern on the first fin pattern;
Third and fourth gate electrodes crossing the second fin-shaped pattern on the second fin-shaped pattern;
A first recess formed between the first and second gate electrodes, the first recess being formed on the first fin pattern and including first and second dimples convex down on a bottom surface;
A second recess formed between the third and fourth gate electrodes, the second recess being formed on the second fin-shaped pattern and including third and fourth dimples convex downward on the bottom surface;
A first source / drain that fills the first recess and includes a top dimple downwardly convex on the top surface; And
And a second source / drain that fills the second recess and has a flat top surface.

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